JP2001008298A - Method for using memory of signal delay device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for using memory of a signal delay device, where a signal delay buffer can be realized by using idle areas dotted in a memory space and number of components of an AV device or an audio device is decreased so as to reduce product cost. SOLUTION: A higher-order bit string of a reference register 110 is used for an index section 11, and a lower-order bit string is used for an offset section 112. Idle areas used for a signal delay buffer among idle areas dotted in a memory space are used for a memory block, and a start address table 120 is produced, which stores a start address of each memory block in cross- reference with a value indicated by the index section 111. Then the value of the reference register 110 is added, and a bit string outputted from the offset section 112 is added to the start address outputted from the start address table 120 to designate an address of a storage area to/from which data are given/ outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of using a memory of a signal delay device used in AV (Audio Visual) equipment and audio equipment.

[0002]

2. Description of the Related Art In recent years, AV systems using DVD (digital video disk) players and AV (audiovisual) amplifiers have become widespread. These A
The V system can reproduce high-definition video and generate a realistic sound field using surround functions such as AC-3 (trademark of Dolby Laboratories) and DTS (trademark of Digital Theater System Company). Is possible.

By the way, a signal delay technique is indispensable for reproducing a sound field having a sense of reality. For example, in a concert hall, the listener hears not only the sound in front but also the sound reflected from the side and rear walls. The sound reflected from a wall or the like arrives later than the sound directly reaching the listener from the performer, and the delay time differs between the reflected sound from the side and the reflected sound from behind. These various sounds having different delay times are extremely important in obtaining a sense of reality.
In the AV system, by controlling the delay time of a signal that reaches a listener, a sound field having a sense of presence, such as listening to a performance in a concert hall, is generated.

FIG. 1 is a circuit block diagram showing an example of a signal delay device used in an AV system. Both the left channel input signal Lin and the right channel input signal Rin input to the signal delay device are digital signals. The input signal Lin is an attenuator (attenuator) 21, 27, 31,
33, 47 and the input signal Rin is applied to the attenuator 2
2, 26, 30, 51 and 65 are input. Those attenuators 21, 22, 26, 27, 30, 31, 3
3, 47, 51, and 65 attenuate the signal at a predetermined attenuation rate and output.

The outputs of the attenuators 26 and 27 are supplied to the mixer 2
After being mixed at 8 and attenuated at a predetermined attenuation rate by the attenuator 29, it is converted to an analog signal by a D / A converter (not shown) and supplied to the center speaker C. The outputs of the attenuators 30 and 31 are mixed by the mixer 32, attenuated at a predetermined attenuation rate by the attenuator 69, converted to an analog signal by a D / A converter (not shown), and supplied to the subwoofer SW. You.

The outputs of the attenuators 21 and 22 are
After being mixed at 3, the signal is input to the digital filter 11. The digital filter 11 is a low-pass filter (Low-
pass filter) or Band-pass filter
er), and passes only a signal of a predetermined frequency. The signal output from the digital filter 11 is input to the signal delay buffer 12 via the mixer 24.

The signal delay buffer 12 has a storage capacity for a predetermined time and is divided into a number of storage areas having different addresses. One word of data is stored in one storage area, and one address is set in one storage area. Here, the signal delay buffer 12 is 200
Assume that it has a storage capacity for msec. The signal delay buffer 12 stores sequentially input signals in each storage area according to the order of addresses. When a signal (also referred to as data) is stored in each storage area, new data is overwritten from the storage area at the first address. Thus, the signal delay buffer 12 has a delay time of 0 m.
The signal from sec to 200 msec is stored. The signal delayed by the maximum delay time (200 msec) in the signal delay buffer 12 is attenuated by the attenuator 25 and then mixed by the mixer 2.
4 and is again input to the signal delay buffer 12.

By reading data from a predetermined position in the signal delay buffer 12, a signal delayed by a predetermined time can be extracted. In the circuit shown in FIG. 1, a1 to a8 are read as left channel delay signals, and b1 to b8 are read as right channel delay signals. The delay signals a1 to a4 are input to the mixer 41 via the attenuators 37 to 40. The mixer 41 mixes and outputs the delayed signals a1 to a4. The output of the mixer 41 is
The signal is input to the mixer 35 via the attenuator 34, and is mixed with the output of the attenuator 33 by the mixer 35. The output of the mixer 35 is input to a D / A converter (not shown) via an attenuator 36, is converted into an analog signal, and is supplied to a left front speaker L.

The delay signals a5 to a8 are input to the mixer 46 via the attenuators 42 to 45. Mixer 4
6 mixes and outputs these delayed signals a5 to a8.
The output of the mixer 46 is supplied to the mixer 4 via an attenuator 48.
9 and is mixed with the output of the attenuator 47 by the mixer 49. The output of the mixer 49 is an attenuator 50
, Is input to a D / A converter (not shown), is converted into an analog signal, and is supplied to the left rear speaker Ls.

The delay signals b1 to b4 are input to the mixer 59 via the attenuators 55 to 58. Mixer 5
9 mixes and outputs these delayed signals b1 to b4.
The output of the mixer 59 is supplied to the mixer 5 via the attenuator 52.
3 and is mixed with the output of the attenuator 51 by the mixer 53. The output of the mixer 53 is an attenuator 54
, Is input to a D / A converter (not shown), is converted into an analog signal, and is supplied to the right front speaker R.

The delay signals b5 to b8 are input to the mixer 64 via the attenuators 60 to 63. Mixer 6
4 mixes and outputs the delayed signals b5 to b8.
The output of the mixer 64 is supplied to the mixer 6 via an attenuator 66.
7 and is mixed with the output of the attenuator 65 by the mixer 67. The output of the mixer 67 is an attenuator 68
, Is input to a D / A converter (not shown), is converted into an analog signal, and is supplied to the right rear speaker Rs.

As described above, in the AV system, by outputting the delayed signal from the left front speaker L, the right front speaker R, the left rear speaker Ls, and the right rear speaker, the sound reflected from the side and rear walls and the like is output. Reproduce,
A realistic sound field space can be formed.

[0013]

In the AV equipment, various processes are performed by a microcomputer or a DSP (digital signal processor), and a memory (hereinafter, referred to as a main memory) for performing those processes is provided. I have. Conventional AV equipment requires an external memory for signal delay buffer separately from the main memory. This is for the following reason.

The signal delay buffer requires a relatively large storage capacity corresponding to the maximum delay time. Further, when storing data in the signal delay buffer, the memory address is incremented (added by 1) and the data is sequentially stored in the order of the addresses. Therefore, the addresses of the respective storage areas need to be continuous. On the other hand, various programs are loaded into the main memory in accordance with processing executed by the microcomputer or the DSP. In the main memory, a work area used when the microcomputer or the DSP executes processing is also secured. For this reason, the empty areas are scattered in the memory space, and it is difficult to secure a large-capacity empty area with continuous addresses. Therefore, conventionally, in order to secure a large-capacity memory space in which addresses are continuous, it is necessary to prepare an external memory dedicated to a signal delay buffer separately from the main memory as described above.
This leads to an increase in the number of parts and an increase in product cost.

The present invention provides a signal delay device which can realize a signal delay buffer by using empty areas scattered in a memory space, thereby reducing the number of parts of AV equipment or audio equipment and reducing product cost. It is intended to provide a memory usage method.

[0016]

An object of the present invention is to provide a method of using a memory of a signal delay device using a plurality of memory blocks having discontinuous addresses as a signal delay buffer, wherein an upper bit string of a reference register is used as an index portion. With the lower bit string as an offset portion, a start address table is created in which each start address of the memory block is stored in association with the value indicated by the index portion, and the value of the reference register is incremented.
A method of using a memory of a signal delay device is characterized in that an address of a storage area for inputting / outputting data is specified by a start address output from the start address table and a bit string output from the offset unit.

The above-mentioned problem is also a method of using a memory of a signal delay device using a plurality of memory blocks having discontinuous addresses as a signal delay buffer, wherein an upper bit sequence of a reference register is used as an index portion, and a lower bit sequence is stored in a lower register. As an offset unit, a start address table is created in which each start address of the memory block is stored in association with the value indicated by the index unit, and the storage capacity of each memory block is stored in association with each memory block. A size table is created, the value of the reference register is incremented, and a start address output from the start address table and a bit string output from the offset unit are used to specify an address of a storage area for inputting / outputting data. , The memo to which the specified storage area belongs When the capacitance value stored in the size table of the block and the value of the offset section match, reset the value of the offset section of the reference register, and increment the value of the index section. The problem is solved by the method of using the memory of the signal delay device.

Hereinafter, the operation of the present invention will be described. In the present invention, a reference register is used, and an upper bit sequence of the reference register is an index portion, and a lower bit sequence is an offset portion. In the present invention, an area used as a signal delay buffer among free areas scattered in the memory space is used as a memory block, and a start address of each memory block is stored in a start address table.
Then, the address of the storage area for inputting / outputting data is specified by the start address output from the start address table and the bit string output from the offset unit.

For example, a value obtained by adding a bit string output from the offset unit to a start address output from the start address table is set as an address of a storage area for inputting / outputting data. Also, for example, only the upper address of the start address of each memory block is stored in the start address table, and the bit string output from the start address table according to the value of the index portion of the reference register is set as the upper address, and the bit sequence output from the offset A bit string having a lower address may be used as a lower address, and a value obtained by combining the upper address and the lower address may be used as an address of a storage area for input / output of data.

In either case, when the value of the offset part overflows, the value of the index part is incremented, and the start address of the next memory block is output from the start address table. In this way, each time the value of the reference register is incremented, one storage area is selected from the plurality of memory blocks, and data writing or data reading is performed on the selected storage area. As described above, in the present invention, it is possible to sequentially select each of the storage areas of the plurality of memory blocks by incrementing the value of the reference register, and it is possible to select a memory block having discontinuous addresses as if the addresses are continuous. Can be used like memory space.

If the capacity of each memory block is not uniform, a size table is provided and the capacity of each memory block is stored in the size table. When the value of the offset section matches the capacity of the memory block selected by the start address table, the value of the offset section is reset (each bit is set to 0), and the value of the index section is incremented. This makes it possible to use a plurality of memory blocks having non-uniform capacities as if they were memory spaces with consecutive addresses.

Each of the start address table and the size table can be realized by using an empty area of the memory, and it is not necessary to provide a dedicated element or the like.
Further, for convenience of expressing the capacity value of the memory block by a binary number, it is preferable that the capacity value of each memory block be 2 to the power of n (where n is an integer).

[0023]

Embodiments of the present invention will be described below with reference to the accompanying drawings. (First Embodiment) FIG. 2 is a block diagram showing an example of an audio signal processing device of an AV system. This audio signal processing device includes an input unit 101, an audio DS
P102, output unit 103 and microcomputer 10
4. The DSP 102 has a RAM
(Random Access Memory) 105 and ROM (Read Onl)
y Memory) 106 and an attenuator, a mixer and a digital filter for constituting a signal delay device (see FIG. 1).

The input unit 101 extracts control data from the input signal and outputs the control data to the microcomputer 104. The microcomputer 104 analyzes the control signal input from the input unit 101, and instructs the DPS 102 to perform predetermined signal processing according to the result.
For example, when the input signal is AC-3, the microcomputer 104 instructs the DSP 102 to perform a decoding process of the AC-3 signal and a predetermined sound field process. When the input signal is DTS, the microcomputer 104
02 instructs decoding processing of the DTS signal and predetermined sound field processing. The DSP 102 is a microcomputer 1
A predetermined program is stored in the ROM 10 according to an instruction from the
6 is loaded into the RAM 105, and processing of the input signal is started according to the program. The signal delay device shown in FIG. 1 is also realized by the DSP 102 and a program.

The signal output from the DSP 102 is D / A-converted by an output unit 103 and supplied to a speaker via an amplifier (not shown). Also, the microcomputer 104 may output the output unit 1 as necessary, for example, when switching signals.
03, and temporarily stops the output from the output unit 103 (voice mute). FIG. 3 is a schematic diagram showing an address space of the RAM 105. In FIG. 3, a hatched portion indicates an area in which a program is loaded, and an outlined portion indicates a free area. As shown in this schematic diagram, the RAM 10
5 is loaded with a program for executing signal processing, and empty spaces are scattered. In the present embodiment, these empty areas are used as a signal delay buffer of a signal delay device. Hereinafter, each free area scattered in the memory space is referred to as a memory block.

FIG. 4 is a schematic diagram showing a method of using the memory of the signal delay device of the present embodiment. In the present embodiment, the configuration of the signal delay device is basically the same as that shown in FIG. 1, so that its illustration and detailed description are omitted. In the present embodiment, the reference register 110 and the start address table 120 are used. Reference register 110
Is one of the operation registers of the DSP 102 or RAM
105 is realized by using a part of the register 105. Here, it is assumed that the register is a 16-bit register. Further, the start address table 120 is realized using a free area of the RAM 105.

In this embodiment, the address of the memory space used as the signal delay buffer is stored in the reference register 110.
Specify by. For example, as shown in FIG. 4, it is assumed that each memory block is composed of a storage area for 256 words with consecutive addresses. In this case, the reference register 110 stores the upper 8 bits of the index section 111 and the lower 8 bits.
And a bit offset section 112. One (one word) storage area is selected from each memory block according to the value of the offset unit 112. Further, one index from the start address table 120 is referred to by the value of the index section 111. In the start address table 120, for example, consecutive index numbers from 00h to FFh are assigned, and the index (index 0) having the index number 00h is the start address of the memory block 0 (1200 in this example).
h) is stored, the start address (1800h in this example) of the memory block 1 is stored in an index (index 1) having an index number of 01h, and Start address (1E0 in this example)
0h) is stored in each of the indexes 0 to n so that the start addresses of the corresponding memory blocks 0 to n are stored.

By using the reference register 110 and the start address table 120, a plurality of memory blocks scattered in the memory space can be used as a continuous area. For example, while the value of the reference register 110 is between 0000h and 00FFh, the index 0
By adding a bit string (relative address) output from the offset unit 112 to the start address output from the memory unit as an address, any one of the storage areas belonging to the memory block 0 is selected. , Data is written to the selected storage area.

Next, the value of the reference register 110 is 0100h
, The index part 111 of the reference register 110
Is 01h, index 1 is selected. The value obtained by adding the bit string (relative address) output from the offset unit 112 to the start address output from the index 1 is used as the address,
One of the plurality of storage areas belonging to the memory block 1 is selected, and data is written to the selected storage area.

As described above, the value of the reference register 110 is sequentially incremented, and data is sequentially stored in each storage area of each of the memory blocks 0 to n. Then, the last storage area of the last memory block n (F0 in this example)
02h), the value of the reference register 110 is returned to 0000h, and the data is stored again from the storage area of the memory block 0.

Also, when reading data from the signal delay buffer, the value of the reference register 110 indicates the address of the storage area where the signal with the delay time of 0 msec is stored, so that the signal with the desired delay time is stored. The address of the storage area can be easily calculated. In the present embodiment, the start address of each memory block is stored in the start address table 120, and the reference register 11
By incrementing the value of 0, the address of the storage area where data is to be stored is specified. As a result, the use efficiency of the memory can be improved, and the memory capacity required for the AV device or the audio device can be reduced, and the product cost can be reduced.

In the above embodiment, the DSP 1
Although a case has been described where the free area of the RAM 105 built in the O. 02 is used as a signal delay buffer, the present invention can also be applied to a RAM external to the DSP 102. In addition, the present invention provides a part of a RAM built in the DSP 102 and a RAM externally attached to the DPS 102.
It is also possible to apply the case where a part or all of are used as a signal delay buffer.

(Second Embodiment) FIG. 5 shows a second embodiment of the present invention.
It is a schematic diagram which shows the memory use method of the signal delay device of 2nd Embodiment. Note that, also in the present embodiment, the configuration of the signal delay device is basically the same as that shown in FIG. 1, and therefore illustration and detailed description thereof are omitted. In the present embodiment, the reference register 110 and the start address table 1
21 is used.

In this embodiment, memory blocks 0 to n
Consists of a storage area for 256 words, and the lower 8 bits of the start address of each of the memory blocks 0 to n are all 0 (00h). Also, the reference register 110
Is divided into an upper 8-bit index section 111 and a lower 8-bit offset section 112. Offset part 1
According to the value of 12, one (one word) storage area is selected from each memory block. Also, the index unit 1
One index in the start address table 120 is referred to by the value of 11. In the start address table 120, for example, consecutive index numbers from 00h to FFh are assigned, and the index (index 0) having the index number 00h is the upper 8 bits of the start address of the memory block 0 (12h in this example). ) Is stored, and the memory block 1 is stored in the index (index 1) having the index number 01h.
Of the start address of the memory block 2 (1Eh in this example) is stored in an index (index 2) having an index number of 02h. Thus, the upper 8 bits (hereinafter also referred to as the upper address) of the corresponding memory blocks 0 to n are stored in the respective indexes 0 to n.

By using the reference register 110 and the start address table 121, a plurality of memory blocks scattered in the memory space can be used as a continuous area. For example, while the value of the reference register 110 is between 0000h and 00FFh, the index 0
And the lower address output from the offset unit 112, the memory block 0
, Any one of the plurality of storage areas is selected, and data is written to the selected storage area.

Next, the value of the reference register 110 is 0100h
, The index part 111 of the reference register 110
Is 01h, index 1 is selected. Then, one of a plurality of storage areas belonging to the memory block 1 is selected by the upper address output from the index 1 and the lower address output from the offset unit 112, and the selected storage area is assigned to the selected storage area. Data is written.

As described above, the value of the reference register 110 is sequentially incremented, and data is sequentially stored in the storage areas of the areas 0 to n. And the last area n
When the data is stored in the last storage area (EFFFh in this example), the value of the reference register 110 is returned to 0000h, and the data is stored again from the storage area of the memory block 0.

When data is read from the signal delay buffer, the address of the storage area where the signal with the delay time of 0 msec is stored can be known from the value of the reference register 110, so that the signal with the desired delay time is stored. The address of the storage area can be easily calculated. In the present embodiment, the upper address of the start address of each memory block is stored in the start address table 121, and the value of the reference register 110 is incremented to specify the address of the storage area where the data is to be stored. As a result, the use efficiency of the memory can be improved, and the memory capacity required for the AV device or the audio device can be reduced, and the product cost can be reduced.

(Third Embodiment) FIG. 6 shows a third embodiment of the present invention.
It is a schematic diagram which shows the memory use method of the signal delay device of 2nd Embodiment. This embodiment is an example applied to a case where the size of each memory block is not uniform. In FIG.
4 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the present embodiment, a size table 130 is prepared in addition to the start address table 120. This size table 130 stores the storage capacity of each memory block. In this example, as shown in FIG. 6, it is assumed that the capacity of the memory block 0 is 100h words, the capacity of the memory block 1 is B0h words, the capacity of the memory block 2 is 100h words, and so on. The size table 130 stores the capacity of each memory block corresponding to each memory block. The number of bits of the offset unit 112 needs to be set to a number of bits that can individually select each storage area of the memory block having the largest storage capacity among the memory blocks. In this example, the capacity value of the memory block having the largest capacity is 2
Since it is 56, the number of bits of the offset unit 112 is set to 8.

In this embodiment, the reference register 1
The upper 8 bits of 10 are the index section 111, and the lower 8 bits are the offset section 112. When the value of the offset unit 112 matches the value stored in the size table 130, the value of the offset unit 112 is set to 00.
h and resetting the index part 1
The value of 11 is incremented.

For example, if the value of the reference register 110 is 000
From 0h to 00FF, a value obtained by adding the bit string (relative address) output from the offset unit 112 to the start address output from the index 0 is set as an address, so that a plurality of storage areas belonging to the memory block 0 are stored. One storage area is selected from among them, and data is written to the selected storage area.

When the value of the offset unit 112 matches the value (FFh) of the capacity of the memory block 0 stored in the size table 130, the value of the offset unit 112 is set to 00h and the value of the index unit 111 is set. Is incremented. As a result, the start address of the memory block 1 is output from the index 1 of the start address table 120. This start address table 1
20 to the start address output from
From the address 18 of the memory block 1 by the value (address) obtained by adding the bit string (relative address) output from
Data is stored in the 00h storage area. After that, the value of the offset unit 112 is sequentially incremented, and data is sequentially stored in each storage area of the memory block 1.
Then, when the data is written to the storage area having the address of 18AFh, the value of the offset unit 112 and the capacity value of the memory block 1 stored in the size table 130 are the same. 00
h, the value of the index unit 111 is incremented.

Thus, the start address table 120
Is selected, and the start address (1E00h) of the memory block 2 is output from the index 2. The value obtained by adding the bit string (relative address) output from the offset unit 112 to the start address output from the start address table 120 is used as the address of the storage area, and data is sequentially stored in each storage area of the memory block 2. .

As described above, in the present embodiment, a signal delay buffer can be realized by using a plurality of memory blocks having different sizes. As a result, in the present embodiment, there is an effect that the use efficiency of the memory can be further improved as compared with the first embodiment. (Fourth Embodiment) FIG. 7 is a schematic diagram showing a method of using a memory of a signal delay device according to a fourth embodiment of the present invention.
This embodiment is also an example applied to a case where the size of each memory block is not uniform. 7, the same components as those in FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the present embodiment, a size table 130 is prepared in addition to the start address table 121. This size table 130 is similar to the third embodiment,
The storage capacity of each memory block is stored. It is also assumed that the lower 8 bits of the start address of each of the memory blocks 0 to n are 0 (00h). In this example, as shown in FIG.
Assume that 0h words, the capacity of the memory block 1 is B0h words, the capacity of the memory block 2 is 100h words,... The size table 130 stores the capacity of each memory block corresponding to each memory block.

In this embodiment, the reference register 1
The upper 8 bits of 10 are the index section 111, and the lower 8 bits are the offset section 112. When the value of the offset unit 112 matches the value stored in the size table 130, the value of the offset unit 112 is set to 00.
h and resetting the index part 1
The value of 11 is incremented.

For example, if the value of the reference register 110 is 000
From 0h to 00FF, the bit string output from index 0 is used as the upper address, and the offset unit 11
Using the bit string output from 2 as a lower address, one storage area is selected from a plurality of storage areas belonging to the memory block 0 based on the upper address and the lower address, and data is written to the selected storage area. .

When the value of the offset unit 112 matches the value (FFh) of the capacity of the memory block 0 stored in the size table 130, the value of the offset unit 112 is set to 00h, and the value of the index unit 111 is set. Is incremented. As a result, the upper address of the memory block 1 is output from the index 1 of the start address table 121. This start address table 1
20 and the offset unit 11
2, the data is stored in the storage area of the memory block 1 at the address 1800h. After that, the value of the offset unit 112 is sequentially incremented, and data is sequentially stored in each storage area of the memory block 1. Then, when the data is written to the storage area having the address of 18AFh, the value of the offset unit 112 and the capacity value of the memory block 1 stored in the size table 130 are the same. 00h, the value of the index unit 111 is incremented.

Thus, the start address table 121
Is selected, and the upper address (1Eh) of the memory block 2 is output from the index 2.
Data is sequentially stored in each storage area of the memory block 2 based on the upper address output from the start address table 121 and the lower address output from the offset unit 112.

As described above, also in the present embodiment, a signal delay buffer can be realized by using a plurality of memory blocks having different sizes. As a result, in the present embodiment, there is an effect that the use efficiency of the memory can be further improved as compared with the second embodiment. In each of the above-described first to fourth embodiments, the number of bits of the index portion and the offset portion is set to 8 bits. However, it is preferable that these values are appropriately set according to the capacity and number of free areas. .

[0052]

As described above, according to the present invention,
Using the upper bit string of the reference register as an index section and the lower bit string as an offset section, each start address of each memory block is stored in the start address table in association with the value of the index section. Then, by incrementing the value of the reference register, it becomes possible to configure a signal delay buffer of the signal delay device using a plurality of memory blocks whose addresses are not continuous. As a result, it is possible to reduce the capacity of the memory used for the AV device or the audio device, and to reduce the product cost.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram illustrating an example of a signal delay device used in an AV system.

FIG. 2 is a block diagram illustrating an example of an audio signal processing device.

FIG. 3 is a schematic diagram illustrating an address space of a RAM;

FIG. 4 is a schematic diagram illustrating a method of using a memory of the signal delay device according to the first embodiment;

FIG. 5 is a schematic diagram illustrating a method of using a memory of the signal delay device according to the second embodiment;

FIG. 6 is a schematic diagram illustrating a method of using a memory of a signal delay device according to a third embodiment;

FIG. 7 is a schematic diagram illustrating a method of using a memory of a signal delay device according to a fourth embodiment;

[Explanation of symbols]

 101 input unit, 102 audio DSP, 103 output unit, 104 microcomputer, 105 RAM, 106 ROM, 110 reference register, 111 index unit, 112 offset unit, 120, 121 start address table, 130 size table.

Claims (9)

[Claims] 1. A method of using a memory of a signal delay device using a plurality of memory blocks having discontinuous addresses as a signal delay buffer, wherein an upper bit sequence of a reference register is used as an index unit, and a lower bit sequence is used as an offset unit. Creating a start address table in which each start address of the memory block is stored in association with the value indicated by the index unit, incrementing the value of the reference register, and starting address output from the start address table; A method of using a memory of a signal delay device, wherein an address of a storage area for inputting / outputting data is specified by a bit string output from a unit. 2. The storage system according to claim 1, wherein a value obtained by adding a bit string output from said index section to a start address output from said address table is used as an address of a storage area for inputting / outputting said data. A method for using a memory of the signal delay device according to the above. 3. The address of a storage area for inputting / outputting the data is designated by using a start address output from the address table as upper bits and a bit string output from the index section as lower bits. A method of using a memory of the signal delay device according to claim 1. 4. The method according to claim 1, wherein the start address table is implemented using a free area of a memory space. 5. The storage capacity of each memory block is as follows:
2. The method according to claim 1, wherein each of them is 2 to the power of n (where n is an integer). 6. A method of using a memory of a signal delay device using a plurality of memory blocks having discontinuous addresses as a signal delay buffer, wherein an upper bit sequence of a reference register is used as an index unit, and a lower bit sequence is used as an offset unit. Create a start address table in which each start address of the memory block is stored in association with the value indicated by the index portion, and create a size table that stores the storage capacity of each memory block in association with each memory block. Incrementing the value of the reference register, and specifying the address of a storage area for inputting and outputting data by the start address output from the start address table and the bit string output from the offset unit, The memory block to which the storage area belongs; Resetting the value of the offset part of the reference register and incrementing the value of the index part when the capacitance value stored in the offset table matches the value of the offset part. How to use the device's memory. 7. The address of a storage area for inputting / outputting the data, wherein a value obtained by adding a bit string output from the index section to a start address output from the address table is used. A method for using a memory of the signal delay device according to the above. 8. An address of a storage area for inputting / outputting the data is designated by setting a start address output from the address table as upper bits and a bit string output from the index section as lower bits. A method of using a memory of the signal delay device according to claim 6. 9. The method according to claim 6, wherein the start address table and the size table are implemented using a free area of a memory space.