JP2001007667A - Variable gain amplifier and differential amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable gain amplifier whose gain can be varied over a wide range and a broadband, without the need for a multi-stage configuration. SOLUTION: This variable gain amplifier is provided with a signal amplifying transistor(TR) 7, gain control TRs 6, 10, a load resistor 14 connected between a collector of the gain control TR 10 and a power supply 1, a capacitor 15 connected between the collector and a ground 9 and also with a low-pass filter that reduces high frequency noise.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable gain amplifier comprising a signal amplifying transistor and output-side and non-output-side gain control transistors each having an emitter connected to the collector of the signal amplifying transistor. And a differential amplifier.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram of a conventional variable gain amplifier. In FIG.
Is connected at one end to an inductance L according to the wiring length.
Is a power supply pad (power supply terminal) having one end connected to the other end of the wiring 2, and the multi-end side is branched into an output side and a non-output side. Reference numeral 4 denotes one end connected to the output side of the power supply pad 3, a load resistor provided on the signal output (OUT) side, 5 denotes a signal output node (output terminal) connected to the other end of the load resistor 4, and 6 denotes the above. A collector is connected to the other end of the load resistor 4 and a gain control transistor provided on the signal output side, 7 is a signal amplification transistor whose collector is connected to the emitter of the gain control transistor 6, and 8 is a signal amplification transistor Reference numeral 7 denotes a bias constant current source whose input side is connected to the emitter, and reference numeral 9 denotes a ground to which the bias constant current source 8 is connected. Reference numeral 10 denotes a gain control transistor connected to the non-output side of the power supply pad 3 and provided on the non-output side. The emitter has the emitter of the gain control transistor 6 and the collector of the signal amplifying transistor 7. Connected to. 11 is a gain control voltage source for supplying a gain control voltage to a control terminal 10t connected to the base of the gain control transistor 10, and 12 is a control terminal 6t connected to the base of the gain control transistor 6.
Is a gain control voltage source for supplying a gain control voltage to the gain control voltage sources 11 and 12. 13
Is a signal input node (input terminal) connected to the base of the signal amplification transistor 7.

Next, the operation will be described. The high-frequency signal input to the signal input node 13 is supplied to the base of the transistor 7 for signal amplification, and the high-frequency signal is amplified as a collector current of the transistor 7 for signal amplification. This collector current flows so as to pull the emitters of the transistors 6 and 10, and flows into the bias constant current source 8. This collector current is equal to the sum of the respective collector currents of the transistors 6 and 10 and the transistors 6 and 1
0 are supplied to the respective collector currents. The control for distributing the collector current is performed by transistors 6,
The control voltages supplied from the respective bases of the transistors 10, 1
Assigned to 0. By allocating the collector current, the gain can be varied. For example, if it is desired to increase the gain, the control voltage on the gain control voltage source 12 side should be increased to increase the collector current on the gain control transistor 6 side. If the gain should be decreased, the gain control voltage source 11 should be increased. It is only necessary to increase the control voltage on the side of the transistor and make a large collector current flow on the transistor 10 for gain control. The gain is controlled by the control voltage. When an input signal is input to the input node 13, the collector current of the gain control transistor 6 flows through the load resistor 3 to be converted. The converted output signal is output from signal output node 5.

[0004]

Since the conventional variable gain amplifier is constructed as described above, the wiring 2 from the power supply 1 to the power supply pad 3 has an inductance L. When this flows, this current is converted to a voltage. This high frequency voltage fluctuates the potential of the power supply pad 3 and appears as a voltage amplitude at the signal output node 5 via the load resistor 4. When the gain is set to be high, the voltage amplitude is not a problem since the output signal is larger than the voltage amplitude due to the inductance L. But if the gain is low,
That is, when the collector current of the gain control transistor 6 is reduced, the voltage amplitude becomes larger than the output signal,
This is the lower limit of gain control, which is problematic. Therefore, in order to be able to operate over a wide band and to vary the gain in a sufficiently wide range, it is necessary to increase the number of stages of the amplifier. In this case, there are problems such as an increase in chip area and an increase in current consumption. there were.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a variable gain amplifier which can operate in a wide band without multi-stages and can vary the gain in a sufficiently wide range. I do.

[0006]

According to a first aspect of the present invention, there is provided a variable gain amplifier comprising: a load resistor connected between a collector of a non-output side gain control transistor and a power supply;
A capacitor connected between the collector of the non-output side gain control transistor and the ground is provided, and a low-pass filter for reducing a high frequency voltage is configured by the load resistor and the capacitor.

In the variable gain amplifier according to the present invention, two power supply terminals for supplying a power supply voltage are provided to each collector side of the output-side and non-output-side gain control transistors, and a power supply and each power supply terminal are provided. Are divided into two lines.

[0008] A differential amplifier according to a third aspect of the present invention comprises:
Two load resistors connected between the respective collectors of the two non-output-side gain control transistors and the power supply side, and connected between the respective collectors of the two non-output-side gain control transistors and the ground. A low-pass filter is constituted by the capacitors.

A differential amplifier according to a fourth aspect of the present invention comprises:
Two power supply terminals for supplying a power supply voltage are provided on each collector side of the output-side and non-output-side gain control transistors, and wiring for connecting the power supply and each power supply terminal is divided into two.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 is a circuit diagram showing a configuration of a variable gain amplifier according to Embodiment 1 of the present invention, and the same components as those in FIG. In the figure, 1 is a power supply for the entire circuit, 2 is a wiring from the power supply 1 to the circuit element, 3 is a power supply pad, 4 is a load resistance on the signal output (OUT) side, 5 is a signal output node, and 6 is a signal output side. A gain control transistor, 7 is a signal amplification transistor,
8 is a bias constant current source, 9 is a ground, 10 is a non-output side gain control transistor, 11 is a non-output side gain control voltage source, 12 is an output side gain control voltage source, and 13 is a signal input node. is there. A load resistor 14 has one end connected to the non-output side of the power supply pad 3 and the other end connected to the collector of the gain control transistor 10, and is provided on the non-output side. Reference numeral 15 denotes a capacitor having one end connected to the other end of the load resistor 14 and the collector of the gain control transistor 10 and the other end connected to the ground 9. It is formed by a capacitor that escapes to the ground 9. A low-pass filter is constituted by the load resistor 14 and the capacitor 15,
This low-pass filter determines the inductance L of the wiring 2
When a high-frequency current flows to generate a high-frequency voltage, the high-frequency voltage is released to the ground 9. The cut-off frequency of the low-pass filter is set in advance so as to cut off the high-frequency voltage.

Next, the operation will be described. Normal amplification operation is
Since it is the same as the conventional example, a case where the output gain is set to be particularly low will be described. First, the control voltage of the voltage source 11 is set to be gradually higher than the control voltage of the voltage source 12, and the output gain is narrowed down. Then, the collector current of the signal amplification transistor 7 becomes the signal output (OUT)
It is distributed so as to flow more to the non-output side gain control transistor 10 than to the side gain control transistor 6. In this state, even if a high-frequency voltage is generated in the inductance L of the wiring 2, the high-frequency current flowing through the inductance L of the wiring 2 is attenuated because the load resistor 14 and the capacitor 15 form a low-pass filter. The amplitude of the high-frequency voltage appearing on the pad 3 can be reduced to a low output level. The high-frequency current has a load resistance of 14, a capacity of 1
5 flows to the ground 9 via the signal output (OU).
It does not flow to the T) side and is not output to the output node 5.

A case will be described in which the output gain is further set low so as not to output an output signal. In this state, when an input signal is input to the input node 13, the input signal flows into the ground 9 via the signal amplification transistor 7, the gain control transistor 10, and the capacitor 15. In the prior art, this input signal leaked to the output node 5 via the load resistor 4, but in the present application,
Unnecessary input signals flow to the ground 9 through the capacitor 15, so that signal leakage can be prevented.

Thus, the high-frequency voltage is applied to the output node 5
When the high-frequency signal is amplified, signal leakage due to the inductance L from the power supply 1 is reduced and the gain control range (dynamic range) is widened as compared with the conventional example. In addition, it is possible to configure a variable gain amplifier that changes the gain in a sufficiently wide range.

Embodiment 2 In the first embodiment, the case where the low-pass filter is constituted by the load resistor 14 and the capacitor 15 has been described. In the second embodiment, as shown in FIG. Power supply pad (power supply terminal) 31 for supplying power supply voltage to
Two wires 32 may be provided, and the wires 21 and 22 connecting the power supply 1 and the power supply pads 31 and 32 may be divided.
In this case, the power supply pad 31 is connected to the gain control transistor 1
0, the power supply pad 32 is connected to the load resistance 4
Is connected to one end. In order to set the output gain low without dividing as in the conventional example, the collector current of the output-side gain control transistor 6 is squeezed, and a reduced amount of current is passed to the non-output-side gain control transistor 10. . At this time, since the potential of the power supply pad 3 fluctuates due to the inductance L of the wiring 2, the amplitude is output to the output node 5 and the output level does not decrease.

In the second embodiment, two power supply pads 3
By providing the wirings 1 and 32 and dividing the wirings 21 and 22 into two, the inductances L1 and L2 are divided into two. Therefore, when the output gain is set low, even if the collector current of the gain control transistor 10 on the non-output side fluctuates, the output node 5 side is not affected by the fluctuation of the collector current. This is because when the collector current of the gain control transistor 10 passes through the inductances L1 and L2, the currents flow in opposite directions with respect to the inductances L1 and L2, and the converted voltages cancel each other. Similarly, when the input signal is the gain control transistor 1
0, the inductances L1 and L2 also cancel each other when flowing to the output side via the inductances L1 and L2. Therefore, it is possible to prevent leakage of a signal output unnecessarily on the output node 5 side.

Embodiment 3 In the first embodiment, the case where only the positive phase signal is amplified has been described. However, in the third embodiment, as shown in FIG. A differential amplifier is constituted by a variable gain amplifier B for dynamic amplification. In this case, load resistors 4, 4a, output nodes 5, 5a, gain control transistors 6, 6a, signal amplification transistors 7,
7a, the gain control transistors 10 and 10a, the input nodes 13 and 13a, and the load resistors 14 and 14a are configured symmetrically with respect to each other.
The opposite phase signal is amplified by the variable gain amplifier B on the right side. One end of the load resistor 14a is connected to the power supply pad 3, and the other end is connected to the collector of the gain control transistor 10a and the capacitor 1
5 is connected. A low-pass filter is constituted by the load resistors 14 and 14a and the capacitor 15. The bases of the gain control transistors 6 and 6a are connected to a gain control voltage source 11, and the gain control transistors 10 and 10a
Are connected to a gain control voltage source 12. An opposite-phase input signal having an opposite phase to the input signal input to the signal amplification transistor 7 is input to the base of the signal amplification transistor 7a. According to this, signal leakage to the output nodes 5 and 5a can be more efficiently removed.
Further, since the differential amplifier is configured, the gain can be varied over a wider range.

Embodiment 4 In the third embodiment, the case where the high-frequency voltage is reduced by providing a low-pass filter in the configuration of the operational amplifier has been described. However, in the fourth embodiment,
As shown in FIG. 4, the configuration of the differential amplifier
Power supply 1 and power supply pads 33 and 34
Are separated from each other. According to this, the same effect as in the third embodiment can be obtained.

[0019]

As described above, according to the first aspect of the present invention, the load resistance connected between the collector of the non-output side gain control transistor and the power supply side and the output resistance of the non-output side are controlled. A capacitor connected between the collector of the gain control transistor and the ground is provided, and a low-pass filter that reduces leakage of high-frequency signals is configured by the load resistor and the capacitor. In addition, a desired gain variable characteristic can be obtained with a small number of stages, and there are effects of power saving and miniaturization.

According to the second aspect of the present invention, two power supply terminals for supplying a power supply voltage are provided to each collector side of the output-side and non-output-side gain control transistors. Is divided into two, so that the variable gain range can be widened, a desired variable gain characteristic can be obtained with a small number of stages, and there is an effect of power saving and miniaturization.

According to the third aspect of the present invention, two load resistors connected between the respective collectors of the two non-output-side gain control transistors and the power supply side, and two non-output-side two gain control transistors are connected. Since the low-pass filter is formed by the capacitors connected between the respective collectors of the two gain control transistors and the ground, the gain variable range can be further widened.

According to the fourth aspect of the present invention, two power supply terminals for supplying a power supply voltage are provided to each collector side of the output-side and non-output-side gain control transistors. Is divided into two, so that the gain variable range can be further widened.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a variable gain amplifier according to Embodiment 1 of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a variable gain amplifier according to a second embodiment.

FIG. 3 is a circuit diagram showing a configuration of a differential amplifier according to a third embodiment.

FIG. 4 is a circuit diagram showing a configuration of a differential amplifier according to a fourth embodiment.

FIG. 5 is a circuit diagram showing a configuration of a conventional variable gain amplifier.

[Explanation of symbols]

1 power supply, 2 wiring, 3 power supply pad, 4,14 load resistance, 5 output node, 6,10 gain control transistor, 11,12 gain control voltage source, 13 input node, 15 capacity, L inductance.

 ──────────────────────────────────────────────────の Continued from the front page F term (reference) 5J066 AA01 AA12 CA32 CA36 CA37 CA41 CA51 CA62 CA81 CA92 FA01 FA10 FA11 FA20 HA02 HA25 HA29 HA33 KA02 KA05 KA12 KA42 KA49 MA19 MA22 ND03 ND04 ND23 ND28 PD01 PD02 TA01 AJA AAA AAA AA23 BA05 BA06 BB01 BC02 CA05 CA09 CA31 DA09 EA02

Claims (4)

[Claims] 1. A variable gain amplifier comprising a signal amplifying transistor and output-side and non-output-side gain control transistors each having an emitter connected to the collector of the signal amplifying transistor. A load resistor connected between the collector of the gain control transistor and the power supply side, and a capacitor connected between the collector of the non-output side gain control transistor and ground. A variable gain amplifier comprising a low-pass filter configured to reduce a high-frequency voltage by using a capacitor. 2. A variable gain amplifier comprising: a signal amplification transistor; and an output-side and non-output-side gain control transistor each having an emitter connected to the collector of the signal amplification transistor. A variable gain amplifier, comprising: two power supply terminals for supplying a power supply voltage to each collector side of a non-output side gain control transistor; and a wiring connecting a power supply and each power supply terminal is divided into two. 3. A variable gain amplifier comprising: a signal amplification transistor; and output-side and non-output-side gain control transistors each having an emitter connected to the collector of the signal amplification transistor. Differential amplifier, two load resistors connected between the respective collectors of the two non-output-side gain control transistors and the power supply side, and the respective collectors of the two non-output-side gain control transistors. A low-pass filter is constituted by a capacitor connected between the ground and a ground. 4. A variable gain amplifier comprising a signal amplification transistor and output-side and non-output-side gain control transistors each having an emitter connected to the collector of the signal amplification transistor. In the differential amplifier described above, two power supply terminals for supplying a power supply voltage are provided on each collector side of the output-side and non-output-side gain control transistors, and a wiring connecting the power supply and each power supply terminal is divided into two. A differential amplifier characterized in that: