JP2001005928A - Ic card - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an IC card which prevents data damage owing to a short break in the middle of data writing and has high operation reliability. SOLUTION: A data storage device is provided with a data storing part 5 which is electrically writable and also stores data in a prescribed unit, and is accessed by a host device for data in the prescribed unit. In such a case, a 1st memory 6 capable of temporarily storing data even without feeding power to the data storage medium, a 2nd memory 7 capable of temporarily storing control information necessary to data transfer to the part 5 from the memory 6 even without feeding power to the data storage device and a controlling means 16 for rewriting data of the prescribed unit during the transfer after resuming power supply in the case power supply is interrupted when the data is transferred are included.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC card used for electronic money, credit cards, and the like.

[0002]

2. Description of the Related Art Instead of a magnetic card which is now widely used,
IC cards that are excellent in storage capacity and security are becoming widespread in various systems. With this, IC
The use environment of the card is also required to be used in a harsher environment as compared with the conventional environment. For example, in an automatic toll collection system (ETC: Electronic Collection System) for a toll expressway, which is currently scheduled to be put into operation, an IC card used for payment of usage fees is inserted into an on-board device installed on a dashboard or the like of an automobile. Then, data communication is performed between the IC card and the roadside antenna installed in the toll gate lane while the vehicle is running, whereby communication necessary for the toll calculation is executed. For this reason, IC cards are required to operate more stably and store stored data in a worse environment than conventional usage environments such as high temperature, vibration, and noise in a vehicle.

[0003]

SUMMARY OF THE INVENTION In particular, I
It has been found that C card access is greatly affected by vibration of the vehicle body. This is because the external terminals of the IC card in the normal contact state and the IC card contact portion of the vehicle-mounted device are momentarily separated due to the vibration of the vehicle body. If the contacts are momentarily separated when writing data in the IC card, the power supplied to the IC card is momentarily interrupted, and the writing operation is interrupted. At that time, the validity of the write data block cannot be guaranteed, and data may be destroyed.

[0004] This is especially true when the data storage unit has an EEPROM.
When using M or Rush EEPROM, the data writing speed of this memory is longer than that of volatile memory such as RAM, so that the trouble of data destruction due to the instantaneous power interruption as described above occurs. And it becomes more difficult to guarantee the validity of the data.

[0005] Further, when the area where data destruction occurs is the management area of the IC card, the IC card may not be used at the time of restart.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to provide an IC card which solves such a conventional problem.

In order to achieve the above object, the present invention provides a data storage unit which is electrically writable and stores data in a predetermined unit, for example, a nonvolatile memory such as a flash EEPROM. In the IC card data to which data is written in a predetermined unit from a higher-level device, there is provided an information storage means for storing that an instantaneous interruption of power supply has occurred during data writing.

Further, means for saving data in the write target area in the backup area, judgment means for judging that an instantaneous interruption has occurred based on information in the storage means when power supply is resumed, and the judgment means When the occurrence of an instantaneous interruption is confirmed, there is provided a means for writing the save data in the backup area to a write target area.

The present invention is configured as described above,
Since a predetermined unit of data that was being written when the power was cut off is written into the data storage unit after the power supply is restarted, the validity of the data is completely guaranteed, and the IC card with high operation reliability is provided. Can be provided.

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram for explaining a semiconductor memory device according to the first embodiment.

The semiconductor memory device 1 includes a microcomputer 2 for reading / writing to / from a flash memory and overall control, an I / F controller 3 for realizing an interface protocol with a host device, a work memory 4, a plurality of flash memories. It is mainly composed of a data storage section 5 composed of a type EEPROM (flash memory array), a first memory 6, a second memory 7, an address bus 8, a data bus 9, and a control signal bus 10 for connecting the respective sections. .

The address bus 11 and the data bus 1
2. It is connected to a host device (not shown) by a control signal bus 13. Here, address bus 8 and address bus 1
1, data bus 9 and data bus 12, control signal bus 10
And the control signal bus 13 do not always correspond to each other.

The microcomputer 2 includes a ROM 14 storing a control program, a RAM 15 having functions such as a counter register and a block number register, and a CPU 16 for executing each control operation.

The I / F controller 3 has a command register 17 for designating a process to be executed and an address register 1 for designating a logical block address for data access in order to realize access to a host device.
8, a length register 19 for designating the number of transfer blocks, a data register 20 for writing / reading data, and a status register 21 for notifying an execution result.

The work memory 4 has a first table 22 for converting a logical block address from a higher-level device into a real block address which is an actual address in a memory space in the flash memory group of the data storage unit 5, and the real block address. And a second table 23 that manages the data area of the flash memory corresponding to. In the semiconductor memory device 1, data access is performed in a certain fixed block unit, similarly to a normal hard disk, and an arbitrary data area is designated as a logical block address by a host device. At this time, the byte unit of one block is arbitrary, but 2n bytes is desirable. Here, a case where one block is composed of 512 bytes will be described.

In the present embodiment, the semiconductor memory device 1 will be described as an example. However, a so-called IC card in which a microcomputer and each memory are constituted by one chip and serially communicates with the outside may be used. In this case, the data storage unit is an EEPROM, and the writing unit is not fixed to 512 bytes per block, and writing is performed in an arbitrary number of bytes.

The structure of the first table 22 will be described with reference to FIG. As described above, the first table 22 stores the logical block address designated for data access from the host device as the actual address in the memory space of the data storage unit 5 composed of a plurality of flash memories. It is for converting to a block address.

In FIG. 1, it is assumed that the logical block address space is mapped to logical block addresses 0001h to FFFFh. Similarly, the real block address space also includes real block addresses 0001h to FFFF.
h. Here, for example, the logical block address 0 is set as the data read destination from the host device.
When 030h is specified, the first table 22 refers to the real block address 0088h corresponding to the logical block address 0030h, specifies the real block address 0088h in the real block address space, and reads the corresponding data A.

By passing through the first table 22 in this manner, the address values of the logical block address and the real block address do not need to always match, so that
The memory space of the data storage unit 5 can be used effectively.

For the logical block address where no data is written, for example, the logical block address FF
Like FFh, the value of the predetermined area of the first table 22 is 0000h, indicating that there is no corresponding data in the real block address space. For reading to such a logical block address, ALL0 may be transferred to a higher-level device.

The second table 23 is for storing flag information for managing the state of data in the real block address in the real block address space. As shown in FIG. 3, in the area of the second table 23 corresponding to the real block address 0088h, a "valid data" flag 01h indicating that the data in the real block address is valid is stored. Further, when the data in the real block address is invalid like the real block address 0043h, the "invalid data" flag 02h is stored. This indicates that the data in this block was valid before, but was rewritten and the data corresponding to a certain logical block address was set to another real block address. The "invalid data" flag also indicates the necessity of the erasing process in the flash memory.

As for the real block address where data can be written, an "empty block" flag 00h is stored like the real block address 0007h. For a real block address where data cannot be written, a "defective block" flag FFh is stored as in the real block address 0123h. By using these flag information, the state of the flash memory constituting the real block address space can be managed, and processing such as writing and erasing data to the flash memory can be performed effectively. The values of these flags are examples, and may be set arbitrarily as long as they are identified so that the state of the flash memory can be managed.

Since the first table 22 and the second table 23 are information necessary for accessing the flash memory in the data storage unit 5, they are stored in the nonvolatile memory. As the memory, an EEPROM or a flash memory may be used, but an FRAM, which has a higher access speed than the EEPROM or the flash memory and can rewrite data in byte units, is most suitable. Alternatively, a method of using an SRAM as a memory and storing table information in a nonvolatile memory when the power is turned off may be used. Alternatively, a method of backing up the SRAM with a battery or the like may be used.

FIG. 4 is a diagram showing a configuration of the first memory 6. The first memory 6 is a non-volatile memory, such as an FRAM or an SRAM backed up by a battery, which has a higher data writing speed than the data storage unit 5 (flash EEPROM) and is nonvolatile. As shown in the figure, a large number of memory blocks 24 are provided for each block number from “block 0” to “block 255”. The total number of the blocks may be arbitrary.

FIG. 5 is a diagram showing a configuration of the second memory 7. The second memory 7 is, for example, an FRAM or an SRAM or an EEPROM backed up by a battery.
And the like. And a flag information area 2 for storing flag information indicating a processing state of the data transfer.
5, a start address information area 26 for storing start address information, a transfer block number information area 27 for storing the number of transfer blocks, an operation target logical block address information area 28 for storing an operation target logical block address, and an operation target real block address. Operation target real block address information area 29 for storing, multiple target logical block address information areas 30 for storing target logical block addresses
And so on.

Data transfer is performed by using the flag information area 25, the head address information area 26, the transfer block number information area 27, the operation target logical block address information area 28, the operation target real block address information area 29, and the target logical block address information area 30. A control information area 31 for storing various types of control information required for the processing of FIG.

Next, the microcomputer 2 will be described with reference to FIGS.
Will be described.

As shown in FIG. 7, when power is supplied from a higher-level device, each unit is first initialized in step (hereinafter abbreviated as S) 1 and a process corresponding to power shutdown is performed in S2. The processing will be described later, and here, a case where power is supplied to the semiconductor memory device from the host device in a normal state will be described.
That is, if it is determined in S2 that the flag information in the second memory is not “11H” or “12H”,
Proceed to S5.

In S5, it is determined whether the command is waiting. If the command is waiting, the command is received. In S6, it is determined whether the command is data writing. If the command is data writing, a write processing subroutine described later is called. Further, it is determined whether or not the command received in S7 is data reading. If the command is data reading, a subroutine of a reading process described later is called.

If it is another command, the process corresponding to the command is executed in S8, and when the processing of the command is completed, an end signal is sent to the host device in S9, and the process waits for the next command.

Next, the writing process will be described with reference to FIG. In S10, the start address value of the logical block address and the number of transfer blocks input from the host device to the address register and the length register are set in the second memory.

Next, the first step is executed in S11.
In this first step, as shown in FIG. 9, first, in S20, flag information "10H", that is, flag information indicating that data is being written from the higher-level device to the first memory, is set in the second memory.

In step S21, the number of blocks to be transferred input to the length register is counted by a counter (RA) in the microcomputer.
M), and the value of the block number register designating the memory block in the first memory is set to "0" in S22.

Then, at S23, 1
The data for the block is transferred to the memory block indicated by the block number (see FIG. 4). When the transfer is completed, S24
In step S25, the value of the block number is incremented by +1. In step S25, the value of the counter is decremented by -1.

The operations of S23 to S25 are repeated until the value of the counter becomes "0", and the value of the counter becomes "0", that is, data writing (transfer) from the higher-level device to the first memory. Is completed in S26, the flag information "11H" indicating the end of the data writing to the first memory is set in the second memory, and the first step is ended.

When the first step is completed, the second step is executed in S12 as shown in FIG.
In this second step, as shown in FIGS. 10 and 11, first, in S30, the flag information "12H",
The flag information indicating that data is being written from the memory to the data storage unit is set in the second memory.

In step S31, the start address value and the number of transfer blocks are read from the second memory, and the logical block address to be written is calculated from them. For example, if the start address value is 0001h and the number of transfer blocks is 3,
The logical block address to be written is 0001h to 0
003h is calculated.

The logical block address value to be written calculated in S32 is stored in the second memory, and the number of blocks to be transferred is set in a counter (RAM).
At step 33, the value of the block number register designating the memory block in the first memory is set to "0".

Next, in S34, the logical block address to be written is read from the second memory based on the number of transfer blocks and the value of the counter. In step S35, the first table is searched to determine whether a real block address corresponding to the logical block address to be written exists.
If it is determined at 36 that a real block address exists,
In S37, an "invalid data" flag is set in the area of the second table corresponding to the real block address.

Next, in step S38, an "empty block" flag is searched from the second table, and the real block address of the "empty block" is set as a write destination block address (S39). In step S40, a logical block address to be written is set. The value and the real block address value of the write destination are stored in the area of the operation target logical block address and the operation target real block address in the second memory, respectively.

Then, in S41, one block of data from the memory block of the first memory indicated by the block number is written to the area of the data storage unit specified by the real block address.

Next, in step S42, the "valid data" flag is set in the area of the second table corresponding to the real block address of the write destination, and in step S43, the area of the first table corresponding to the logical block address of the write target is set. Is set to the real block address value of the write destination.

Thereafter, the value of the block number is incremented in S44, the value of the counter is decremented in S45, and it is determined whether or not the value of the counter has become 0 in S46. S34 to S4 until the counter value becomes 0
6 is repeated to transfer the data of the predetermined block from the first memory to the data storage unit.

When the data transfer is completed, the control information set in the second memory is cleared in S47, the flag information of the second memory is set to "00H" in S48, and the second step is ended. The execution of the second step is similarly performed in S4 of FIG. 7 described above.

Returning to FIG. 8, when the second step is executed in S12, it is determined in S13 whether or not there is an erase block. If there is no erase block, the write processing is terminated.

Next, the reading process will be described with reference to FIG. First, in S50, the values of the address register and the length register are read, the logical block address value and the number of blocks to be transferred are read, and in S51, the number of transfer blocks is set in a counter.

Next, the logical block address to be read is calculated from the head address value of the read logical block address, the number of transfer blocks, and the value of the counter. Next, it is converted into a real block address from the first table (S53), and the data in the real block address is read out in S54 and transferred to the host device via the I / F controller. Then, the value of the counter is decremented in S55, and it is determined whether or not the value of the counter has become 0 in S56. Data processing is repeated by repeating the processing operations from S52 to S56 until the counter value becomes 0, and the data is read out. When the value becomes 0, the reading process ends.

Next, the erasing process will be described with reference to FIG. First, in step S60, the second table is searched for an "invalid data" flag. In step S61, a "valid data" flag in an erase block unit including an "invalid data" flag is searched. It is determined whether or not there is. If there is no "valid data" flag, an erasing operation is performed in erase block units in S63.

If it is determined in S62 that the "valid data" flag is present, the data in the real block address, which is the "valid data" flag, is saved in the work memory in S64, and erased from the second table in S65. Search for "empty block" flags outside the block.

In step S66, the data saved in the work memory is written to the actual block address of the "empty block". Next, in step S67, the real block address of the save source is searched from the first table, and is changed to the real block address of the write destination, and the "valid flag" is set in the area of the second table corresponding to the written real block address. Is set (S68), and an erasing operation is performed in erase block units in S69.

Thereafter, in step S70, an "empty flag" is set in the area of the second table corresponding to the real block address in the erase block, and the erase processing ends.

The above description is of a normal processing operation in which power is supplied from the higher-level device to the semiconductor memory device. However, when a power failure occurs, the outlet of the higher-level device is unexpectedly pulled out, or the semiconductor memory device is pulled out. When the connection with the host device is unexpectedly cut off, that is, the power supply from the host device to the semiconductor memory device may be cut off.

Next, the response to this case will be described with reference to FIGS. FIG. 6 is a diagram for explaining the state flag. As shown in FIG.
"H" indicates a ready state, "10H" indicates that data is being written from the higher-level device to the first memory, "11H" indicates that data has been written from the higher-level device to the first memory, and "12H" indicates that data has been written to the first memory. The case indicates that data is being written from the first memory to the data storage unit.

At S2 in FIG. 7, the data writing from the host device to the first memory is completed ("11H") or the first
Writing data from the memory to the data storage unit (“1
2H ”) indicates that the data being transferred can be recovered even if the power supply to the semiconductor memory device is cut off from the host device at that time. On the other hand, if the power is turned off while data is being written from the higher-level device to the first memory ("10H"), the data of the block is only partially stored in the first memory. Indicates that recovery is not possible. Therefore, in this S2,
At that time, when the power to the semiconductor memory device is cut off, it is determined whether the data can be restored.

When the flag information indicates "11H" or "12H" and it is determined that the data being transferred can be restored, the actual block address value to be operated is read from the second memory in S3, and the actual block is read. An "invalid data" flag is set in the area of the second table corresponding to the address, and during recovery processing, writing of data to the actual block address is prohibited. Next, in step S4, the above-described second step is executed, and after the power supply is restarted, the data being transferred during the power-off is written to the data storage unit from the beginning.

FIGS. 14 to 16 are diagrams for explaining a modification of the processing operation. FIG. 14 differs from FIG. 7 in that, after S8, the end of the command process is returned to the host device in S9 regardless of the write process or the read process.

FIG. 15 differs from FIG. 8 in that there is an S100 between S11 and S12 for returning the end of the command processing to the host device.

Further, FIG. 16 differs from FIG. 12 in that the end of the command processing is returned to the host device after S56 (S101), and the read processing is ended.

When the predetermined command processing is completed as described above, the fact is notified to the higher-level device sequentially, so that the waiting time of the higher-level device can be shortened as much as possible, and other processing in the higher-level device becomes possible. The processing efficiency of the host device is improved.

Next, data writing in the case of a so-called IC card in which a microcomputer and each memory are formed of one chip and serial communication with the outside is performed will be described with reference to a flowchart of FIG. A write command block is transferred to the IC card from a higher-level external device such as a reader / writer by serial communication, and written into a communication buffer set in a volatile memory such as an SRAM inside the IC card. This command block includes write data and a write address in addition to command information indicating a write command.

In S201, a block (physical address) corresponding to the write area indicated by the write address (logical address) is calculated. In step S202, a writing flag is set to determine that the power supply has been interrupted while the rewrite block number obtained in step S201 is stored in the nonvolatile memory and written. Next, in S203, the data written in the rewrite block is written to the save area to save the data, and it is confirmed in S204 that the data save to the save area is successful.

At step S205, the write data actually transmitted in the communication buffer is written to the rewrite block obtained at step S201, and at step S206, it is confirmed that the data write has been normally executed. Finally, in S207, S20
The process of clearing the in-write flag set in step 3 is executed, and the write process ends.

An EEPROM or a rush E is stored in the data storage unit.
When an EPROM is used, since the data writing speed of this memory is longer than that of a volatile memory such as a RAM, the probability of an instantaneous power interruption occurring during the processing of S203 is high. In this case, the data in the write block includes data being written and data before the write process, resulting in data destruction.

In the initialization process when the power is turned on again, it is possible to know that the power supply during the rewriting process has been interrupted by checking the rewriting flag. The processing will be described with reference to FIG.

In the initialization processing after the power supply of the IC card is turned on, the state of the writing flag is confirmed, and if the flag is set (if the processing during data writing is interrupted in the previous processing), FIG. The processing is executed to reproduce the writing area. In S208, the writing flag is checked, and it is checked that the flag is set. In S209, the data saved in the save area is written to the block number destination saved in S202 in FIG. 17, and the destroyed block is written in S210. Is reproduced to the state before the writing process. S21
At 0, it is confirmed that the data write-back has been executed normally. At S211, the writing flag is cleared, and the data reproducing process is completed.

[0066]

According to the present invention, a predetermined unit of write data being written when the power is turned off is written into the data storage unit after the power supply is restarted. In addition, the guarantee of the validity of the data is completed, and an IC card with high operation reliability can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining a configuration and a function of a first table.

FIG. 3 is an explanatory diagram for explaining a configuration and a function of a second table.

FIG. 4 is a configuration diagram of a first memory;

FIG. 5 is a configuration diagram of a second memory.

FIG. 6 is an explanatory diagram showing the contents of a flag value stored in a second memory.

FIG. 7 is a flowchart showing a main routine of the semiconductor memory device.

FIG. 8 is a flowchart illustrating a data write process.

FIG. 9 is a flowchart showing a first step.

FIG. 10 is a flowchart showing a second step.

FIG. 11 is a flowchart showing a second step.

FIG. 12 is a flowchart illustrating a data read process.

FIG. 13 is a flowchart showing a data erasing process.

FIG. 14 is a flowchart illustrating a modification of the main routine.

FIG. 15 is a flowchart showing a data write process in the modification.

FIG. 16 is a flowchart showing a data read process in the modification.

FIG. 17 is a flowchart showing a data write process.

FIG. 18 is a flowchart showing a process of reproducing a destruction area.

[Explanation of symbols]

 Reference Signs List 1 semiconductor memory device 2 microcomputer 3 I / F controller 4 work memory 5 data storage unit 6 first memory 7 second memory 14 ROM 15 RAM 16 CPU 17 command register 18 address register 19 length register 20 data register 21 status register 22 First table 23 Second table 24 Memory block 25 Flag information area 26 First address information area 27 Transfer block number information area 28 Logical block address information area to be operated 29 Real block address information area to be operated 30 Control state area

Claims (2)

[Claims] 1. A non-volatile data storage unit which is electrically writable and stores data in a predetermined unit is provided, and writing to the data storage unit is performed in a predetermined unit from a host device. An IC card, comprising: an instantaneous interruption information storage means for storing that an instantaneous interruption of power supply has occurred while data is being written to a write target area. 2. The IC card according to claim 1, wherein a means for saving data in a write target area to a backup area and an instantaneous interruption based on information in said instantaneous interruption information storage means when power supply is resumed. And a means for writing the save data of the backup area to a write target area when the determination means confirms the occurrence of an instantaneous interruption.