JP2001005637A - Data circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make preventable a circuit with an FIFO function from being put into a data empty state by outputting a status signal obtained by comparing the value of a specific bit of a register indicating the number of pieces of stored data with the value of a previously set specific bit. SOLUTION: When data are already written to the circuit 5 with FIFO function, a write pointer 52 of the circuit 5 is increased by the number of the pieces of written data and when data are read out of the circuit 5, a read pointer 55 of the circuit 5 is increased by the number of the pieces of read data. At this time, the number of pieces of data stored in the circuit 5 is obtained by subtracting the read pointer 55 from the write pointer 53. The circuit 5 compares the number of the pieces of data stored in the circuit 5 with a previously set value to assert a status signal. The comparison is made by using the specific bit of the register. The status signal is connected to a DMA controller or interruption controller and serves as a DMA request or interruption request.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit, and
The present invention relates to an integrated circuit using an IFO (first in first out) control method.

[0002]

2. Description of the Related Art In an integrated circuit incorporating a conventional circuit having a FIFO function, when used for voice processing, continuous transfer is often performed. However, data is transmitted without interruption by a data transmission circuit. For this purpose, it is necessary that transmission data always exist inside a circuit having a FIFO function. Also, in order for the data receiving circuit to receive data without interruption, there must always be an empty space for storing data inside a circuit having a FIFO function.

For example, FIG. 24 is a diagram showing a transition of the number of data stored in a circuit having a conventional FIFO function. When the number of stored data is going to fall below a preset value, FIG. (FIG. 24 (b)) is for outputting a status signal. Referring to FIG.
In the case where A data (A> B) is output from the circuit having the FIFO function faster than the B data is written to the circuit having the FIFO function (FIG. 24E,
In (f)), it becomes difficult for the number of data in the circuit having the FIFO function to exceed a preset value thereafter (FIGS. 24 (c) and (d)).

Therefore, there is a problem that a status signal is not output until data in a circuit having a FIFO function is lost.

FIG. 25 is a diagram showing a transition of the number of data stored in a circuit having a conventional FIFO function. When the number of stored data is going to exceed a preset value, FIG. (FIG. 25B) is for outputting a status signal. Referring to FIG.
A case where A data (A> B) is output from a circuit having an FIFO function faster than writing B data into a circuit having an FIFO function (FIGS. 25 (e) and (f))
Is that the number of data in the circuit having the FIFO function thereafter becomes less than a preset value (FIG. 25).
(C) and (d)) become difficult.

Therefore, there is a problem that a status signal is not output until data in a circuit having a FIFO function overflows.

[0007]

In the conventional integrated circuit as described above, when data transmission / reception is performed, when a series of data transmission / reception is completed and the operation is stopped, residual data exists in a circuit having a FIFO function. However, there is a problem that the status signal is not output despite the operation.

[0008]

An integrated circuit according to the present invention compares a specific bit of a register indicating the number of data to be stored with a preset specific bit value in a data circuit provided with a circuit having a FIFO function. By doing so, a circuit having a FIFO function for outputting a status signal is provided.

Further, in the data circuit according to the first aspect, the data circuit is a transmission circuit or a reception circuit.

In a data circuit provided with a circuit having a FIFO function, a register indicating the number of data to be stored, a first set value set by a user to negate a status signal, and a second set value asserting a status signal are provided. A circuit having a FIFO function of outputting a status signal by comparing the setting value with the setting value.

Further, in the data circuit according to the third aspect, the data circuit is a transmission circuit or a reception circuit.

In a data circuit provided with a circuit having a FIFO function, a plurality of status signals can be generated by comparing a specific bit of a register indicating the number of data to be stored with a value of a plurality of predetermined specific bits. It has a circuit having a FIFO function for outputting.

In a data circuit provided with a circuit having a FIFO function, a plurality of comparison circuits for comparing the number of data to be stored with a plurality of set values set by a user are provided, and the number of data is compared with the plurality of set values. By doing so, a circuit having a FIFO function for outputting a plurality of status signals is provided.

In a data circuit provided with a circuit having a FIFO function, a memory for storing data, a write pointer and a read pointer for storing an address of the memory, and a remaining amount circuit for receiving the write pointer and the read pointer are provided. , A comparison circuit for comparing a circuit with a set value of 0, a difference between the write pointer and the read pointer, and a circuit with a set value of 0, and recognition for recognizing whether a series of data is being transmitted / received or stopped from a peripheral circuit or a CPU. And a status signal generation circuit that generates a status signal based on input signals from the recognition circuit and the comparison circuit.
And a circuit having an FO function.

Further, in the data circuit according to any one of claims 5 to 7, at least one of the plurality of status signals is provided with a circuit having a FIFO function connected to a DMA controller.

The data circuit according to any one of claims 5 to 7, further comprising a circuit having a FIFO function in which at least one of the plurality of status signals is connected to an interrupt controller.

Further, in any one of claims 5 to 7,
The data circuit according to the item, further comprising a circuit having a FIFO function in which at least one of the plurality of status signals is connected to each of the DMA controller and the interrupt controller.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a data transmission circuit with a circuit having a FIFO function according to the first embodiment. Referring to FIG. 1, transmission circuit 1 includes an IO bus 3 for data transfer, a circuit 5 having a FIFO function for transferring data from IO bus 3, and a FIFO.
A status signal is transmitted from the shift register 7 to which the output data of the circuit 5 having the function is input, and the DM which outputs the data to the IO bus 3 from the circuit 5 having the FIFO function.
It comprises an A controller 8 and an interrupt controller 11. In addition, a peripheral circuit and a CPU are connected to the IO bus 3.

FIG. 2 is a block diagram of the circuit 5 having a FIFO function. Referring to FIG. 2, a circuit 5 having a FIFO function transfers data from IO bus 3 and stores the memory 51, a write pointer 53 storing an address of memory 51, a read pointer 55, and a write pointer 53. The remaining amount circuit 57 to which the pointer 53 and the read pointer 55 are input, and a difference between the write pointer 53 and the read pointer 55 and a preset value (first, a comparison is made to compare the difference between the write pointer 53 and the read pointer 55) And a comparison circuit 58 that compares the value with the comparison value.

The operation of the transmission circuit 1 will be described.
First, transmission data is written from the IO bus 3 to the circuit 5 having the FIFO function, and the transmission data in the circuit 5 having the FIFO function is sent to the shift register 7. The transmission data sent to the shift register 7 is transmitted as a serial output. When data is written to the circuit 5 having the FIFO function, the write pointer 53 of the circuit 5 having the FIFO function is incremented by the number of write data. When data is read from the circuit 5 having the FIFO function, the read pointer 55 of the circuit 5 having the FIFO function is incremented by the number of read data.

At this time, the number of data stored in the circuit 5 having the FIFO function is prepared by subtracting the read pointer 55 from the write pointer 53. The status signal is connected to the DMA controller 8 or the interrupt controller 11, and serves as a DMA request or an interrupt request.

FIG. 3 is a diagram showing the transition of the number of data stored in the circuit 5 having the FIFO function (not an actual circuit configuration). Circuit 5 with FIFO function
Is a comparison between the number of stored data and a preset value (a value initially created for comparing the difference between the write pointer 53 and the read pointer 55, and is referred to as setting 1 here). , Assert the status signal. The comparison is performed by a specific bit of a register indicating the number of stored data.

For example, assuming that the number of data stored in the circuit 5 having the FIFO function is represented by 16 bits, if it is set that the status signal is output when the upper 4 bits are "0000", the circuit 5 having the FIFO function is set. The status signal is asserted when the number of data stored in the memory is equal to or less than 16′h0fff (setting 1 = 16 ′).
h0fff). That is, the state shown in FIG.
When the status signal shifts to the state, the status signal is asserted. Thereafter, when the state shifts to the state of FIG. 3D, the status signal is negated, and when the state shifts to the state of FIG. 3C, the status signal continues to be asserted regardless of CPU access.

According to the first embodiment, it is possible to cope with the case where the data reading speed from the circuit having the FIFO function is faster than the data writing speed to the circuit having the FIFO function, and it is possible to prevent the data empty of the circuit having the FIFO function. It is possible. Further, it is possible to reduce the number of transistors or the circuit area in manufacturing a circuit.

Embodiment 2 FIG. 4 is a block diagram of a data receiving circuit with a circuit having a FIFO function according to the second embodiment. Referring to FIG. 4, receiving circuit 101 includes an IO bus 103 for data transfer, a circuit 105 having a FIFO function for transferring data to IO bus 103,
A status signal is transmitted from a shift register 107 for inputting output data to a circuit 105 having a FIFO function and a circuit 105 having a FIFO function.
And an interrupt controller 111 for outputting data to the CPU. In addition, a peripheral circuit and a CPU are connected to the IO bus 103.

FIG. 5 is a block diagram of the circuit 105 having the FIFO function. Referring to FIG. 5, the circuit 105 having the FIFO function includes a memory 151 in which data is transferred and stored from the shift register 107, a write pointer 153 storing an address of the memory 151,
The read pointer 155, the remaining amount circuit 157 to which the write pointer 153 and the read pointer 155 are input, the difference between the write pointer 153 and the read pointer 155 and a preset value (first, the write pointer 153
And a value created for comparing the difference between the read pointer 155 and the read pointer 155. ) Is compared with a comparison circuit 158.

The operation of the receiving circuit 101 will be described. First, the received data is stored in the shift register 107 and then written to the circuit 105 having a FIFO function. Data stored in the circuit 105 having the FIFO function is read out from the IO bus 103 to another module. When data is written to the circuit 105 having the FIFO function, the write pointer 153 of the circuit 105 having the FIFO function is incremented by the number of write data. When data is read from the circuit 105 having the FIFO function, the circuit 1 having the FIFO function
The read pointer 155 of 05 is incremented by the number of read data.

At this time, the circuit 105 having the FIFO function
Are prepared by subtracting the read pointer 155 from the write pointer 153. The status signal is connected to the DMA controller 108 or the interrupt controller 111, and serves as a DMA request or an interrupt request.

FIG. 6 is a diagram showing a transition of the number of data stored in the circuit 105 having the FIFO function (not an actual circuit configuration). The circuit 105 having the FIFO function stores the number of stored data and a preset value (a value created first for comparing the difference between the write pointer 153 and the read pointer 155, and is referred to as setting 1 here). To assert the status signal. The comparison is performed by a specific bit of a register indicating the number of stored data.

For example, a circuit 105 having a FIFO function
Is assumed to be represented by 16 bits, when it is set to output a status signal when the upper 4 bits are “1111”, the circuit 105 having the FIFO function is set.
The status signal is asserted when the number of data stored in the memory is 16'hf000 or more (setting 1
= 16'h0fff). That is, when the number of status signals shifts from the state of FIG. 6A to the state of FIG. 6B, the status signal is asserted. Thereafter, if the state shifts to the state shown in FIG. 6D, the status signal is negated.
If the state shifts to the state (c), the status signal continues to be asserted regardless of the access of the CPU.

According to the second embodiment, it is possible to cope with the case where the data reading speed from the circuit having the FIFO function is slower than the data writing speed to the circuit having the FIFO function, and it is possible to prevent data full in the circuit having the FIFO function. It is possible. Further, it is possible to reduce the number of transistors or the circuit area in manufacturing a circuit.

Embodiment 3 FIG. FIG. 7 shows Embodiment 3
1 is a block diagram of a data transmission circuit with a circuit having a FIFO function according to FIG. Referring to FIG.
Reference numeral 1 denotes an IO bus 303 for data transfer and an IO bus 3
03, a circuit 305 having a FIFO function to which data is transferred, a shift register 307 to which output data of the circuit 305 having a FIFO function is input, and a status signal transmitted from the circuit 305 having a FIFO function.
DMA controller 3 that outputs data to O bus 303
08 and an interrupt controller 311.
In addition, a peripheral circuit and a CPU are connected to the IO bus 303.

FIG. 8 is a block diagram of a circuit 305 having a FIFO function. Referring to FIG. 8, a circuit 305 having a FIFO function transfers data from IO bus 303 and stores the memory 351, a write pointer 353 for storing an address of memory 351, a read pointer 355, and a user A setting circuit 333a that can set the number of data, a setting circuit 333b, and a write pointer 3
53 and the remaining circuit 3 to which the read pointer 355 is input
57, the write pointer 353 and the read pointer 35
5, a comparison circuit 358a for comparing the difference between the data of No. 5 and the number of data of the setting circuit 333a, a comparison circuit 358b for comparing the difference between the write pointer 353 and the read pointer 355 and the number of data of the setting circuit 333b, And a data generation circuit 370 that generates data based on the input data of 358b.

The operation of the transmitting circuit 301 will be described. First, the transmission data is written from the IO bus 303 to the circuit 305 having the FIFO function, and the transmission data in the circuit 305 having the FIFO function is stored in the shift register 307.
Sent to The transmission data sent to the shift register 307 is transmitted as a serial output.

When data is written to the circuit 305 having the FIFO function, the circuit 305 having the FIFO function
Is incremented by the number of write data. When data is read from the circuit 305 having the FIFO function, the read pointer 355 of the circuit 305 having the FIFO function is incremented by the number of read data.

At this time, a circuit 305 having a FIFO function
Is prepared by subtracting the read pointer 355 from the write pointer 353. The status signal is connected to the DMA controller 308 or the interrupt controller 311 and serves as a DMA request or an interrupt request.

FIG. 9 is a diagram showing a transition of the number of data stored in the circuit 305 having the FIFO function (not an actual circuit configuration). The circuit 305 having the FIFO function asserts the status signal by comparing the number of stored data with the value (setting 1, setting 2) for which the user has set the number of data. One of the setting values (setting 2) has a role of asserting the status signal. The other set value (setting 1) has a role of negating the status signal. The set value that plays the role of negating the status signal is set to a larger value than the set value that plays the role of asserting the status signal.

When the number of data stored in the circuit 305 having the FIFO function matches the set value for asserting the status signal, the status signal is asserted.
When the number of data stored in the circuit 305 having the FIFO function matches the set value for negating the status signal, the status signal is negated. That is, FIG.
When the number of data transitions from the state of FIG. 9A to the state of FIG. 9C, the status signal is asserted. Then, FIG.
If the state shifts to the state (f), the status signal is negated. The status signal continues to be asserted irrespective of CPU access until it is negated by comparison with the set value.

According to the third embodiment, it is possible to cope with the case where the data reading speed from the circuit having the FIFO function is faster than the data writing speed to the circuit having the FIFO function, and it is possible to prevent the data empty of the circuit having the FIFO function. It is possible.

Further, since the status signal can be continuously asserted until the number of data stored in the circuit having the FIFO function becomes almost empty and becomes almost full, necessary data can be concentrated. It is possible to perform data processing efficiently.

Embodiment 4 FIG. FIG. 10 is a block diagram of a data receiving circuit with a circuit having a FIFO function according to the fourth embodiment. Referring to FIG. 10, receiving circuit 401 inputs output data to IO bus 403 for data transfer, circuit 405 having a FIFO function for transferring data to IO bus 403, and circuit 405 having a FIFO function. Status signals are transmitted from the shift register 407 and the circuit 405 having a FIFO function,
DMA controller 40 that outputs data to bus 403
8 and an interrupt controller 411. In addition, a peripheral circuit and a CPU are connected to the IO bus 403.

FIG. 11 shows a circuit 405 having a FIFO function.
It is a block diagram of. Referring to FIG.
The circuit 405 having a function is provided with a memory 451 to which data is transferred and stored from the shift register 407, and a write pointer 453 for storing an address of the memory 451.
, A read pointer 455, a setting circuit 433a that allows the user to set the number of data, and a setting circuit 433b.

A remaining circuit 457 to which the write pointer 453 and the read pointer 455 are input, and a comparison circuit 458a for comparing the difference between the write pointer 453 and the read pointer 455 with the number of data in the setting circuit 433a.
A comparison circuit 458b for comparing the difference between the write pointer 453 and the read pointer 455 with the number of data of the setting circuit 433b, and a data generation circuit 470 for generating data from the input data of the comparison circuits 458a and 458b.

The operation of the receiving circuit 401 will be described. The received data is stored in the shift register 407 and then written to the circuit 405 having a FIFO function. The data stored in the circuit 405 having the FIFO function is read out from the IO bus 403 to another module.

When data is written to the circuit 405 having the FIFO function, the circuit 405 having the FIFO function
Is incremented by the number of write data. When data is read from the circuit 405 having the FIFO function, the read pointer 455 of the circuit 405 having the FIFO function is incremented by the number of read data.

At this time, a circuit 405 having a FIFO function
Is prepared by subtracting the read pointer 455 from the write pointer 453. The status signal is connected to the DMA controller 8 or the interrupt controller 11, and serves as a DMA request or an interrupt request.

FIG. 12 shows a circuit 405 having a FIFO function.
Is a graphic representation of the transition of the number of data stored in the data (not an actual circuit configuration). The circuit 405 having the FIFO function asserts the status signal by comparing the stored data number with a value (setting 1, setting 2) for which the user has set the data number. One of the setting values (Setting 2)
Is responsible for asserting the status signal. The other set value (setting 1) has a role of negating the status signal. The set value that plays the role of negating the status signal is set to a larger value than the set value that plays the role of asserting the status signal.

When the number of data stored in the circuit 405 having the FIFO function matches the set value for negating the status signal, the status signal is negated.
That is, when the number of data shifts from the state of FIG. 12A to the state of FIG. 12C, the status signal is asserted.
Thereafter, when the state shifts to the state shown in FIG. 12 (f), the status signal is negated. The status signal continues to be asserted irrespective of CPU access until it is negated by comparison with the set value.

According to the fourth embodiment, it is possible to cope with the case where the speed of reading data from the circuit having the FIFO function is lower than the speed of writing data to the circuit having the FIFO function, and it is possible to prevent data full in the circuit having the FIFO function. It is possible.

Further, since the status signal can be continuously asserted from a state where the number of data stored in the circuit having the FIFO function is close to data full to a state close to empty, necessary data can be stored. The transmission can be performed in a concentrated manner, and data processing can be performed efficiently.

Embodiment 5 FIG. FIG. 13 is a block diagram of a data transmission circuit with a circuit having a FIFO function according to the fifth embodiment. Referring to FIG. 13, transmission circuit 501 receives an input of an IO bus 503 for data transfer, a circuit 505 having a FIFO function for transferring data from IO bus 503, and an output data of circuit 505 having a FIFO function. Shift register 507 and FIFO
A status signal is transmitted from the circuit 505 having a function, and the DMA controller 508 and the interrupt controller 511 output data to the IO bus 503. In addition, a peripheral circuit and a CPU are connected to the IO bus 503.

FIG. 14 shows a circuit 505 having a FIFO function.
It is a block diagram of. Referring to FIG.
The circuit 505 having a function includes a memory 551 in which data is transferred and stored from the IO bus 503,
1, a write pointer 553 for storing an address of “1”, a read pointer 555, a remaining amount circuit 557 to which the write pointer 553 and the read pointer 555 are input, and a difference between the write pointer 553 and the read pointer 555 and a preset value (first And a comparison circuit 558 for comparing the difference between the write pointer 553 and the read pointer 555.

The operation of the transmission circuit 501 will be described. Transmission data is written from an IO bus 503 to a circuit 505 having a FIFO function, and transmission data in the circuit 505 having a FIFO function is sent to a shift register 507. The transmission data sent to the shift register 507 is transmitted as a serial output. When data is written to the circuit 505 having the FIFO function, the write pointer 553 of the circuit 505 having the FIFO function is incremented by the number of write data. When data is read from the circuit 505 having the FIFO function,
The read pointer 555 of the circuit 505 having the O function is incremented by the number of read data.

At this time, a circuit 505 having a FIFO function
Is prepared by subtracting the read pointer 555 from the write pointer 553. The status signal is connected to the DMA controller 508 or the interrupt controller 511, and serves as a DMA request or an interrupt request.

FIG. 15 shows a circuit 505 having a FIFO function.
Is a graphic representation of the transition of the number of data stored in the data (not an actual circuit configuration). The circuit 505 having the FIFO function is a value created in order to compare the number of stored data with a preset value (first, a difference between the write pointer 553 and the read pointer 555. Here, setting 1, setting 2 By comparing with
Assert the status signal. The comparison is performed by a specific bit of a register indicating the number of stored data.

For example, a circuit 505 having a FIFO function
Is assumed to be represented by 16 bits, if the status signal is set to be asserted when the upper 4 bits are “0000” and when all the upper 16 bits are not “0”, the FIFO is set. The number of data stored in the circuit 505 having a function is 16'h001
The status signal is asserted when the value is 0 or more and 16'h0fff or less (setting 1 = 16'h0fff,
Setting 1 = 16'h0010).

That is, the state shown in FIG.
When the number of data shifts to the state of (b), the status signal is asserted. Thereafter, when the state shifts to the state of FIG. 15D or the state of FIG. 15E, the status signal is negated. In the state shown in FIG. 15C, the status signal continues to be asserted regardless of the access of the CPU.

According to the fifth embodiment, it is possible to cope with the case where the speed of reading data from the circuit having the FIFO function is faster than the speed of writing data to the circuit having the FIFO function, and to prevent data emptying of the circuit having the FIFO function. It is possible. In addition, using data
When data is written to the circuit having the O function by DMA transfer or the like, the number of data stored in the circuit having the FIFO function decreases to just before the data empty, and
When it is determined that the processing cannot be completed in the transfer, the status signal can be negated and the DMA transfer can be stopped.

If a setting is made to generate a CPU interrupt when the number of data stored in the circuit having the FIFO function has decreased to just before data empty, the DMA request often has a higher priority than the interrupt request.
Since the bus right may be held during the request, DMA
It is effective to stop the transfer.

When a circuit having a FIFO function is incorporated in a data receiving circuit and used, it is possible to cope with a case where the data reading speed from the circuit having the FIFO function is lower than the data writing speed to the circuit having the FIFO function. It is possible to prevent data full of a circuit having a FIFO function.

When data is read from a circuit having a FIFO function using data by DMA transfer or the like, the number of data stored in the circuit having a FIFO function increases until immediately before data full, and DMA transfer is performed. When it is determined that the processing cannot be performed in time, the status signal can be negated and the DMA transfer can be stopped.

When a setting is made such that a CPU interrupt is generated when the number of data stored in a circuit having a FIFO function has increased to just before data full, a DMA request often has a higher priority than an interrupt request. It is effective to stop the DMA transfer because the bus right may be held during the request.

Embodiment 6 FIG. FIG. 16 is a block diagram of a data transmission circuit with a circuit having a FIFO function according to the sixth embodiment. Referring to FIG. 16, transmission circuit 601 receives an IO bus 603 for data transfer, a circuit 605 having a FIFO function for transferring data from IO bus 603, and an output data of circuit 605 having a FIFO function. Shift register 607 and FIFO
A status signal is transmitted from the circuit 605 having a function, and the DMA controller 608 includes a DMA controller 608 that outputs data to the IO bus 603 and an interrupt controller 611. In addition, a peripheral circuit and a CPU are connected to the IO bus 603.

FIG. 17 shows a circuit 605 having a FIFO function.
It is a block diagram of. Referring to FIG.
The circuit 605 having a function includes a memory 651 in which data is transferred and stored from the IO bus 603,
A write pointer 653 for storing an address of 1, a read pointer 655, a setting circuit 633a that allows the user to set the number of data, and a setting circuit 633b are provided.

A remaining circuit 657 to which the write pointer 653 and the read pointer 655 are input, and a comparator 658a for comparing the difference between the write pointer 653 and the read pointer 655 with the number of data in the setting circuit 633a.
A comparison circuit 658b for comparing the difference between the data of the write pointer 653 and the read pointer 655 with the number of data of the setting circuit 633b, and a status signal generation circuit 670 for generating a status signal based on the input data of the comparison circuits 658a and 658b. Be composed.

The operation of the transmission circuit 601 will be described. Transmission data is written from an IO bus 603 to a circuit 605 having a FIFO function, and transmission data in the circuit 605 having a FIFO function is sent to a shift register 607. The transmission data sent to the shift register 607 is transmitted as a serial output.

When data is written to the circuit 605 having the FIFO function, the write pointer 653 of the circuit 605 having the FIFO function is incremented by the number of write data. Circuit 6 with FIFO function
When data is read from the data buffer 05, the read pointer 655 of the circuit 605 having the FIFO function is incremented by the number of read data.

At this time, a circuit 605 having a FIFO function
Is prepared by subtracting the read pointer 655 from the write pointer 653. The status signal is connected to the DMA controller 608 or the interrupt controller 611, and serves as a DMA request or an interrupt request.

FIG. 18 shows a circuit 605 having a FIFO function.
Is a graphic representation of the transition of the number of data stored in the data (not an actual circuit configuration). The circuit 605 having the FIFO function asserts the status signal by comparing the stored data number with a value (setting 1, setting 2) for which the user has set the data number. The comparison is performed using two types of set values and a magnitude comparison circuit. The number of stored data is equal to or less than one set value (setting 1) and the other set value (setting 2)
In this case, the status signal is kept asserted.

That is, the state shown in FIG.
When the number of data shifts to the state of (b), the status signal is asserted. Thereafter, if the state shifts to the state of FIG. 18D or the state of FIG. 18E, the status signal is negated. In the state of FIG. 18C, the status signal continues to be asserted regardless of the access of the CPU.

According to the sixth embodiment, it is possible to cope with the case where the data reading speed from the circuit having the FIFO function is faster than the data writing speed to the circuit having the FIFO function, and it is possible to prevent the data empty of the circuit having the FIFO function. It is possible.

When data is written to a circuit having a FIFO function using data by DMA transfer or the like, the number of data stored in the circuit having a FIFO function is reduced to just before data empty, and DMA transfer is performed. When it is determined that the processing cannot be performed in time, the status signal can be negated and the DMA transfer can be stopped.

If a setting is made such that a CPU interrupt is generated when the number of data stored in the circuit having the FIFO function has decreased to just before data empty, the DMA request often has a higher priority than the interrupt request.
Since the bus right may be held during the request, DMA
It is effective to stop the transfer.

Further, when a circuit having a FIFO function is incorporated in a data receiving circuit and used, it is possible to cope with a case where the data reading speed from the circuit having the FIFO function is lower than the data writing speed to the circuit having the FIFO function. It is possible to prevent data full of a circuit having a FIFO function.

When data is read from a circuit having a FIFO function using data by DMA transfer or the like, the number of data stored in the circuit having a FIFO function increases until immediately before data full, and DMA transfer is performed. When it is determined that the processing cannot be performed in time, the status signal can be negated and the DMA transfer can be stopped.

If a setting is made to generate a CPU interrupt when the number of data stored in the circuit having the FIFO function has increased to just before data full, the DMA request often has a higher priority than the interrupt request. It is effective to stop the DMA transfer because the bus right may be held during the request.

Embodiment 7 FIG. 19 is a block diagram of a data transmission circuit with a circuit having a FIFO function according to the seventh embodiment. Referring to FIG. 19, transmission circuit 701 receives an input of an IO bus 703 for data transfer, a circuit 705 having a FIFO function to which data is transferred from IO bus 703, and an output data of circuit 705 having a FIFO function. Shift register 707 and FIFO
A status signal is transmitted from the circuit 705 having a function, and the DMA controller 708 and the interrupt controller 711 output data to the IO bus 703. In addition, a peripheral circuit and a CPU are connected to the IO bus 703.

FIG. 20 shows a circuit 705 having a FIFO function.
It is a block diagram of. Referring to FIG. 20, this FIFO
A circuit 705 having a function includes a memory 751 in which data is transferred and stored from the IO bus 703,
A write pointer 753 for storing the address of No. 1, a read pointer 755, a setting circuit 733 a by which the user can set the number of data, a setting circuit 733 b, a remaining amount circuit 757 to which the write pointer 753 and the read pointer 755 are inputted, The comparison circuit 758a compares the difference between the write pointer 753 and the read pointer 755 with the number of data of the setting circuit 733a, and the comparison circuit 758b compares the difference between the write pointer 753 and the read pointer 755 with the number of data of the setting circuit 733b. Be composed.

The operation of the transmitting circuit 701 will be described. Transmission data is written from an IO bus 703 to a circuit 705 having a FIFO function, and transmission data in the circuit 705 having a FIFO function is sent to a shift register 707. The transmission data sent to the shift register 707 is transmitted as a serial output.

When data is written to the circuit 705 having the FIFO function, the circuit 705 having the FIFO function
Is incremented by the number of write data. When data is read from the circuit 705 having the FIFO function, the read pointer 755 of the circuit 705 having the FIFO function is incremented by the number of read data.

At this time, a circuit 705 having a FIFO function
Is prepared by subtracting the read pointer 755 from the write pointer 753. The status signal is connected to the DMA controller 708 or the interrupt controller 711, and serves as a DMA request or an interrupt request.

FIG. 21 shows a circuit 705 having a FIFO function.
Is a graphic representation of the transition of the number of data stored in the data (not an actual circuit configuration). The circuit 705 having the FIFO function asserts the status signal by comparing the stored data number with the value (setting 1, setting 2) for which the user has set the data number. The comparison is performed using a plurality of types of setting values (for example, setting 1 and setting 2).

When writing to the circuit 705 having the FIFO function is performed by DMA transfer, a DMA request is output if the number of stored data is equal to or smaller than one set value (setting 1) (may match the setting 1). (The output may be performed only once). That is, the state shown in FIG.
When the number of data shifts to the state of (b), a DMA request is output. Thereafter, if the state shifts to the state of FIG. 21A, the DMA request is cleared. FIG.
Under the condition (c), the status signal continues to be asserted regardless of the access of the CPU.

When the value is equal to or less than the other set value (set 2) (it may be the same as set 2), that is, when the state shifts to the state shown in FIG. 21C, the DMA request signal having a higher priority is set. Is output accordingly. Further, in addition to the switching of the priority, the output may be switched to an interrupt signal or the like.

According to the seventh embodiment, it is possible to change the priority or type of the request signal according to the number of data stored in the circuit having the FIFO function.

Embodiment 8 FIG. FIG. 22 is a block diagram of a data receiving circuit with a circuit having a FIFO function according to the eighth embodiment. Referring to FIG. 22, this receiving circuit 801
Are IO bus 803 for data transfer and IO bus 80
3 having a FIFO function for transferring data to
, A shift register 807 for inputting received data to a circuit 805 having a FIFO function, and a status signal transmitted from the circuit 805 having a FIFO function.
The DMA controller 808 includes a DMA controller 808 that outputs data to the H.03 and an interrupt controller 811. Other I
A peripheral circuit and a CPU are connected to the O bus 803.

FIG. 23 shows a circuit 805 having a FIFO function.
It is a block diagram of. Referring to FIG.
The circuit 805 having a function includes a memory 851 to which data is transferred and stored from the shift register 807, and a write pointer 853 for storing an address of the memory 851.
, A read pointer 855, a remaining amount circuit 857 to which the write pointer 853 and the read pointer 855 are input.
And a circuit 877 whose set value is “0” and a write pointer 8
53 and the difference between the read pointer 855 and the set value are “0”
A comparison circuit 858 for comparing with the circuit 877, a recognition circuit 888 for recognizing that a series of data is being received / stopped from a peripheral circuit or a CPU, and a status signal is generated by input data of the recognition circuit 888 and the comparison circuit 858 And a status signal generation circuit 870.

The operation of the receiving circuit 801 will be described. First, the received data is stored in the shift register 807, and then written into the circuit 805 having a FIFO function. Data stored in the circuit 805 having the FIFO function is read out from the IO bus 803 to another module.

When data is written to the circuit 805 having the FIFO function, the circuit 805 having the FIFO function
Is incremented by the number of write data. When data is read from the circuit 805 having the FIFO function, the read pointer 855 of the circuit 805 having the FIFO function is incremented by the number of read data.

At this time, a circuit 805 having a FIFO function
Is prepared by subtracting the read pointer 855 from the write pointer 853. The status signal is connected to the DMA controller 808 or the interrupt controller 811 and serves as a DMA request or an interrupt request.

When the end of the reception is detected by the recognition circuit 888, if the data stored in the circuit 805 having the FIFO function remains (the number of data is not 0), the remaining data is transferred. Assert the status signal to get it.

According to the eighth embodiment, the load of the CPU processing can be reduced by the circuit having the FIFO function independently determining the situation.

Embodiment 9 FIG. In the eighth embodiment, F
Although a data receiving circuit with a circuit having an IFO function is described as an embodiment, it may be a data transmitting circuit. For example, by changing the shift register shown in FIG. 22 to a shift register to which output data of a circuit having a FIFO function is input, a data transmission circuit with a circuit having a FIFO function can be configured (not shown).

In the operation, if data stored in the circuit having the FIFO function remains (the number of data is not 0), a status signal is asserted to process the remaining data.

According to the ninth embodiment, similarly to the eighth embodiment, the load of the CPU processing can be reduced by the circuit having the FIFO function independently judging the situation.

Embodiment 10 FIG. As described above, Embodiments 1 to 9
Although the data transmitted / received to / from the shift register is described as serial data, nothing is limited to serial data and parallel data may be used. For example, a circuit having a FIFO function capable of dealing with parallel data can be configured by removing the shift register shown in FIG. 1 (not shown). Hereinafter, FIGS. 4, 7, 10, 13, 16, 1
The same applies to 9, 22 and the like.

The operation and effects are the same as in the first to ninth embodiments.

[0098]

According to the integrated circuit of the present invention, in a data circuit provided with a circuit having a FIFO function, a specific bit of a register indicating the number of data to be stored is compared with a value of a predetermined specific bit. By providing a circuit having a FIFO function for outputting a status signal, it is possible to cope with a case where the data reading speed from the circuit having the FIFO function is faster than the data writing speed to the circuit having the FIFO function. It is possible to prevent emptying.

Further, it is possible to reduce the number of transistors or the circuit area in manufacturing the circuit.

Further, in the data circuit according to the first aspect, the data circuit is a transmission circuit or a reception circuit, so that the data read speed from the circuit having the FIFO function is lower than the data write speed to the circuit having the FIFO function. It is possible to cope with a slow case, and it is possible to prevent data full of a circuit having a FIFO function.

Further, it is possible to reduce the number of transistors or the circuit area in manufacturing a circuit.

In a data circuit provided with a circuit having a FIFO function, a register indicating the number of data to be stored, a first set value set by a user to negate a status signal, and a second set value asserting a status signal are provided. By providing a circuit having a FIFO function of outputting a status signal by comparing with a set value,
FIF from the data writing speed to the circuit having O function
It is possible to cope with a case where the data reading speed from the circuit having the O function is high, and it is possible to prevent data empty in the circuit having the FIFO function.

Further, since the status signal can be continuously asserted from the state where the number of data stored in the circuit having the FIFO function is almost empty to the state where it is almost full, necessary data can be concentrated. It is possible to perform data processing efficiently.

In the data circuit according to the third aspect, the data circuit is a transmission circuit or a reception circuit, so that the data read speed from the circuit having the FIFO function is lower than the data write speed to the circuit having the FIFO function. It is possible to cope with a slow case, and it is possible to prevent data full of a circuit having a FIFO function.

Further, since the status signal can be continuously asserted until the number of data stored in the circuit having the FIFO function becomes a state close to data full and becomes a state close to empty, necessary data can be stored. The transmission can be performed in a concentrated manner, and data processing can be performed efficiently.

In a data circuit provided with a circuit having a FIFO function, a plurality of status signals can be generated by comparing a specific bit of a register indicating the number of data to be stored with a plurality of predetermined bits. By providing a circuit having a FIFO function for outputting,
It is possible to cope with a case where the data reading speed from the circuit having the FIFO function is faster than the data writing speed to the circuit having the FIFO function, and it is possible to prevent data emptying of the circuit having the FIFO function.

In a data circuit provided with a circuit having a FIFO function, a plurality of comparison circuits for comparing the number of data to be stored with a plurality of set values set by a user are provided, and the number of data is compared with the plurality of set values. By providing a circuit having a FIFO function for outputting a plurality of status signals, it is possible to further cope with a case where the speed of reading data from the circuit having the FIFO function is faster than the speed of writing data to the circuit having the FIFO function. , FI
It is possible to prevent data empty of a circuit having the FO function.

When data is written to a circuit having a FIFO function using data by DMA transfer or the like, the number of data stored in the circuit having a FIFO function is reduced to just before data empty, and DMA transfer is performed. When it is determined that the processing cannot be performed in time, the status signal can be negated and the DMA transfer can be stopped.

In a data circuit provided with a circuit having a FIFO function, a memory for storing data, a write pointer and a read pointer for storing an address of the memory, and a remaining amount circuit for receiving the write pointer and the read pointer are provided. , A comparison circuit for comparing a circuit with a set value of 0, a difference between the write pointer and the read pointer, and a circuit with a set value of 0, and recognition for recognizing whether a series of data is being transmitted / received or stopped from a peripheral circuit or a CPU. And a status signal generation circuit that generates a status signal based on input signals from the recognition circuit and the comparison circuit.
And a circuit having an FO function.
The circuit with the function determines the situation independently,
It is possible to reduce the load of U processing.

The data circuit according to any one of claims 5 to 7, further comprising a circuit having a FIFO function in which at least one of the plurality of status signals is connected to a DMA controller. In the case where data is written to a circuit having a FIFO function by DMA transfer or the like using the above, the number of data stored in the circuit having the FIFO function decreases until immediately before data empty, and if the processing cannot be completed in the DMA transfer, When it is determined, the status signal can be negated and the DMA transfer can be stopped.

The data circuit according to any one of claims 5 to 7, further comprising a circuit having a FIFO function in which at least one of the plurality of status signals is connected to an interrupt controller.
If the CPU interrupt is set to occur when the number of data stored in the circuit having the FO function has decreased to just before data empty, the DMA request often has a higher priority than the interrupt request. Since there are cases where the bus right is held, the DMA transfer can be stopped.

Further, in any one of claims 5 to 7,
3. The data circuit according to claim 1, wherein at least one of the plurality of status signals includes a circuit having a FIFO function connected to each of the DMA controller and the interrupt controller, so that the data stored in the circuit having the FIFO function is provided. It is possible to change the priority or type of the request signal according to the number.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data transmission circuit with a circuit having a FIFO function according to a first embodiment of the present invention;

FIG. 2 is a block diagram of a circuit having a FIFO function according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a transition of the number of data stored in a circuit having a FIFO function according to the first embodiment of the present invention;

FIG. 4 is a block diagram of a data receiving circuit with a circuit having a FIFO function according to a second embodiment of the present invention;

FIG. 5 is a block diagram of a circuit having a FIFO function according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a transition of the number of data stored in a circuit having a FIFO function according to a second embodiment of the present invention.

FIG. 7 is a block diagram of a data transmission circuit with a circuit having a FIFO function according to a third embodiment of the present invention.

FIG. 8 is a block diagram of a circuit having a FIFO function according to a third embodiment of the present invention.

FIG. 9 is a diagram showing a transition of the number of data stored in a circuit having a FIFO function according to a third embodiment of the present invention.

FIG. 10 is a block diagram of a data receiving circuit with a circuit having a FIFO function according to a fourth embodiment of the present invention.

FIG. 11 is a block diagram of a circuit having a FIFO function according to a fourth embodiment of the present invention.

FIG. 12 is a diagram illustrating a transition of the number of data stored in a circuit having a FIFO function according to a fourth embodiment of the present invention.

FIG. 13 is a block diagram of a data transmission circuit with a circuit having a FIFO function according to a fifth embodiment of the present invention.

FIG. 14 is a block diagram of a circuit having a FIFO function according to a fifth embodiment of the present invention.

FIG. 15 is a diagram illustrating a transition of the number of data stored in a circuit having a FIFO function according to a fifth embodiment of the present invention.

FIG. 16 is a block diagram of a data transmission circuit with a circuit having a FIFO function according to a sixth embodiment of the present invention.

FIG. 17 is a block diagram of a circuit having a FIFO function according to a sixth embodiment of the present invention.

FIG. 18 is a diagram illustrating a transition of the number of data stored in a circuit having a FIFO function according to a sixth embodiment of the present invention.

FIG. 19 is a block diagram of a data transmission circuit with a circuit having a FIFO function according to a seventh embodiment of the present invention.

FIG. 20 is a block diagram of a circuit having a FIFO function according to a seventh embodiment of the present invention.

FIG. 21 is a diagram illustrating a transition of the number of data stored in a circuit having a FIFO function according to a seventh embodiment of the present invention.

FIG. 22 is a block diagram of a data receiving circuit with a circuit having a FIFO function according to an eighth embodiment of the present invention.

FIG. 23 is a block diagram of a circuit having a FIFO function according to an eighth embodiment of the present invention.

FIG. 24 is a diagram showing a transition of the number of data stored in a circuit having a conventional FIFO function.

FIG. 25 is a diagram showing a transition of the number of data stored in a circuit having a conventional FIFO function.

[Explanation of symbols]

Reference Signs List 1 transmission circuit 5 circuit with FIFO function 101 reception circuit 105 circuit with FIFO function 301 transmission circuit 305 circuit with FIFO function 401 reception circuit 405 circuit with FIFO function 505 circuit with FIFO function 508 DMA controller 511 interrupt controller 605 FIFO Circuit having a function 608 DMA controller 611 Interrupt controller 705 Circuit having a FIFO function 708 DMA controller 711 Interrupt controller 805 Circuit having a FIFO function 808 DMA controller 811 Interrupt controller 807 Shift register 851 Memory 853 Write pointer 855 Read pointer 857 Remaining circuit 858 Comparison circuit 870 Data generation circuit 877 Setting value is 0 bit Circuit 888 Recognition circuit

Claims (10)

[Claims] In a data circuit provided with a circuit having a FIFO function, a specific bit of a register indicating the number of data to be stored is compared with a value of a predetermined specific bit.
A data circuit comprising a circuit having a FIFO function for outputting a status signal. 2. The data circuit according to claim 1, wherein said data circuit is a transmission circuit or a reception circuit. 3. A data circuit provided with a circuit having a FIFO function, comprising: a register indicating the number of data to be stored; a first set value set by a user to negate a status signal; and a second set value asserting a status signal. A FIFO that outputs a status signal by comparing with a set value
A data circuit comprising: a circuit having an O function. 4. The data circuit according to claim 3, wherein said data circuit is a transmission circuit or a reception circuit. 5. A data circuit provided with a circuit having a FIFO function, wherein a plurality of status signals are generated by comparing a specific bit of a register indicating the number of data to be stored with a value of a plurality of predetermined specific bits. A data circuit comprising a circuit having a FIFO function for outputting. 6. A data circuit provided with a circuit having a FIFO function, comprising: a plurality of comparison circuits for comparing the number of stored data with a plurality of set values set by a user; A data circuit, comprising: a circuit having a FIFO function for outputting a plurality of status signals by comparing with the above. 7. A data circuit provided with a circuit having a FIFO function, comprising: a memory for storing data; a write pointer and a read pointer for storing an address of the memory; and a remaining amount to which the write pointer and the read pointer are input. A circuit having a set value of 0; a comparing circuit for comparing the difference between the write pointer and the read pointer and a circuit having the set value of 0; and transmitting / receiving a series of data from a peripheral circuit or a CPU A data circuit, comprising: a recognition circuit for recognizing a signal; and a circuit having a FIFO function including a status signal generation circuit for generating a status signal based on input signals from the recognition circuit and the comparison circuit. 8. The data circuit according to claim 5, wherein at least one of the plurality of status signals is connected to a DMA controller.
A data circuit comprising a circuit having an FO function. 9. The data circuit according to claim 5, wherein at least one of the plurality of status signals is connected to an interrupt controller.
A data circuit comprising a circuit having an IFO function. 10. The data circuit according to claim 5, wherein at least one of the plurality of status signals has a FIFO function connected to each of a DMA controller and an interrupt controller. A data circuit, comprising: