JP2001005422A - Plasma display device and driving method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce reactive power consumption by bringing a common electrode potential of non-display lines into a floating condition, and alternately switching the lines for display operation and those for making the common electrode potential floating. SOLUTION: A sustained discharge pulse is applied to Y-electrodes of odd- numbered lines in a 1st field, and those of even-numbered lines in a 2nd field. Wall changes are still stored on X- and Y-electrodes in a cell which has generated wall charges and discharged them just before, and the cell is initiated to discharge again by being applied with the sustained discharge pulse. On the other hand, in a cell which has not discharged just before, wall charges are not stored on X- and Y-electrodes, therefore, discharge is not generated even though the sustained discharge pulse is applied to the cell. Light emission is continued for the sustained discharge period by repeating this operation. Reactive power consumption due to the charge/discharge to/from a capacitive load between the X- and Y-electrodes in the non-display lines can be reduced by making the Y-electrode potential of the non-display lines to be in a floating state for this sustained discharge period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a plasma display device and a driving method thereof, and more particularly to a driving method for suppressing power consumption.

[0002]

2. Description of the Related Art FIG. 12 is a vertical sectional view showing a part of a panel structure of a three-electrode AC type plasma display panel (PDP). This PDP has address electrodes W1, W2,...
Wm,..., Wm, scan electrodes X1, X2,..., Xn extending in a direction perpendicular to the paper surface, and common electrodes Y1, Y2,. , Yn, dielectric 7, M
A gO layer 8, a phosphor 9, a front glass substrate 10a, and a rear glass substrate 10b are provided (FIG. 12 shows a cross section including the address electrode Wj). Further, a partition (not shown) is formed between the front glass substrate 10a and the rear glass substrate 10b with each address electrode interposed therebetween, thereby securing a discharge space DP. The discharge space DP is filled with an inert gas (for example, a mixed gas of neon and xenon). Hereinafter, the common electrodes Y1, Y2,..., Yn are collectively referred to as Y electrodes, and the scan electrodes X1, X2,.
.., Xn are collectively called an X electrode.

Each of the X electrode and the Y electrode is composed of a transparent electrode 34 formed on the front glass substrate 10a and a bus electrode 33 formed on the transparent electrode 34, respectively. The reason for using the transparent electrode 34 is that the front glass substrate 1
This is because the visible light is efficiently extracted through Oa. The reason for forming the bus electrode 33 on the transparent electrode 34 is as follows.
This is for reducing the value of the line resistance of the transparent electrode 34. The X electrode and the Y electrode are covered with a dielectric 7, and an MgO layer 8 is formed on the surface of the dielectric 7 as a protective film.

Further, address electrodes W1, W2,..., W
m is formed orthogonally to the X electrode and the Y electrode on the rear glass substrate 10b, and the phosphor 9 is formed on the surface of each address electrode and the surface of the partition.

[0005] The light emission principle of the PDP utilizes a phenomenon that vacuum ultraviolet rays (VUV) generated from an inert gas by discharge excite a phosphor. In the structure of the PDP shown in FIG. 12, a sustain discharge is caused between the X electrode and the Y electrode, and the phosphor 9 is excited using VUV generated at that time. Then, the reflected light of the light emitted from the phosphor 9 is taken out from the front glass substrate 10 and used as a display image. It is to be noted that a structure for extracting the transmitted light of the phosphor from the rear glass substrate 10b side is also considered.

FIG. 13 shows a structure of a conventional PDP device PD4 including peripheral circuits other than the panel. FIG.
In FIG. 13, panel 5 is shown as a set of cells 6 including one intersection of an address electrode and an X and Y electrode (in FIG. 13, only 4 × 5 cells are shown for simplicity, but nx Assume that there are m cells). Also,
Around the panel 5, a control circuit 1, a first memory 11, a second memory 12, an X electrode maintaining circuit 31, a scan driving circuit 3
2, the address drive circuit 21 and the Y electrode sustaining circuit 41 are shown. The control circuit 1 converts display data supplied from the outside into data suitable for display on the panel 5 and supplies the data to the address driving circuit 21. Further, the control circuit 1 includes an X electrode maintaining circuit 31,
It also controls the scan drive circuit 32 and the Y electrode maintenance circuit 41.

Next, the operation of the PDP device PD4 will be described. FIG. 14 is a diagram showing a state of a drive waveform of each electrode when performing interlaced display in the PDP device PD4.
For example, in the case of an NTSC signal, one frame is composed of a first field for displaying even lines and a second field for displaying odd lines. However, since each cell of the PDP can take only binary values of light emission and non-light emission, in order to display a plurality of gradations, the above one field is temporally divided into subfields. In each subfield, the discharge between the address electrode and the X electrode
The address period in which wall charges are stored on the surface of the layer and the wall charges are X
A sustain discharge period for sustain discharge between the electrode and the Y electrode. The sustain discharge period of each subfield is temporally weighted, and halftone display is performed by a combination of display and non-display of the subfield. For example, in the case of using the luminance display 256 = 2 ⁸ gradations divides the field into eight sub-fields,
The sustain discharge period of each divided subfield is weighted in eight stages. By selecting lighting or non-lighting of each of the weighted subfields, an arbitrary gray scale out of 256 gray scales can be displayed. The order of lighting of the subfields at this time may be any order regardless of the length of the sustain discharge period.

Now, the operation in the subfield of the first field in FIG. 14 will be described. As a premise,
It is assumed that data of all even-numbered lines is input to the control circuit 1 together with the synchronization signal in the field immediately before the first field, and is stored in the second memory 12.

First, at the beginning of the address period, writing and erasing are performed on the X electrodes and the Y electrodes of all the cells 6 on the even line in order to equalize the state of the cells 6 on the even line. Next, the control circuit 1 reads the data of the second line from the data of all even lines stored in the second memory 12 from the second memory 12 and sends the data to the address drive circuit 21. The address driving circuit 21 applies an address pulse L ₂ to the address electrodes W1 to Wm based on the data.
To activate the address electrodes selectively. At this time, the scan driving circuit 32 while under the control of the control circuit 1, and outputs the scan pulse X ₂ to the scan electrode X2 of the second line active. As a result, a discharge occurs in the cell 6 of the second line in which both the X electrode and the address electrode are active, and the space charges generated by the discharge move to the electrodes of opposite polarities and are accumulated as wall charges. . After the generation of the wall charges, the discharge stops because the substantial potential difference between the X electrode and the address electrode is smaller than the potential difference that can maintain the discharge. That wall charges in the cell 6 is generated based on the address pulse L _2, data is written to the second line.

Thereafter, the control circuit 1 reads the data of the even lines from the second memory 12 in the order of the fourth line, the sixth line,... And sends the data to the address drive circuit 21. The address drive circuit 21 outputs address pulses L ₄ , L ₆ ,..., L _n in the same manner as in the case of the second line. At this time, the scan driving circuit 32 outputs the address pulses L ₄ , L ₆ ,
· · · ·, L scanning the even lines corresponding to each of the _n pulse X _4, X _6, · · · ·, outputs X _n, cell X electrodes of each line, the address electrodes are both made active 6 generates wall charges.

When the data is written to all the even lines, the address period ends. Since the scan pulses X ₁ , X ₃ ,..., X _n−1 for the odd lines are not output during the address period of the first field, the scan drive circuit 32 for the odd lines is not used.

In the subsequent sustain discharge period, the X electrode sustain circuit 3
1 and the Y-electrode sustaining circuit 41 alternately generate pulses having different phases under the control of the control circuit 1 to perform a light-emitting operation by sustain discharge between the two electrodes.

The above operation of one subfield is repeated by the number of subfields, and the operation of the first field is completed. During the period of the first field, data of all odd lines displayed in the next field is input to the control circuit 1 together with a synchronization signal. Then, the input data of all the odd-numbered lines is written to the first memory 11.

Next, the second field is entered and the same operation as in the first field is performed. That is, at the beginning of the address period, the control circuit 1 performs writing and erasing on all the cells 6 on the odd line in order to equalize the state of the cells 6 on the odd line. Next, the control circuit 1
The data of the first line is read from the memory 11 and sent to the address drive circuit 21. Address driving circuit 21 gives the address pulse L ₁ to the address electrodes W1~Wm on the basis of the data, selectively activate the address electrodes. At this time, the scan drive circuit 32 activates the scan pulse X ₁ that activates the scan electrode X1 of the first line.
Is output. As a result, among the cells 6 on the first line, those in which the X electrode and the address electrode are both activated generate wall charges, and data is written on the first line.
Thereafter, the control circuit 1 reads the data of the odd-numbered lines from the first memory 11 in the order of the third line, the fifth line,... And sends the data to the address drive circuit 21. Then, the address driving circuit 21 outputs address pulses L ₃ , L ₅ ,..., L _n−1 in the same manner as in the case of the first line. At this time, the scan driving circuit 32 outputs the address pulses L ₃ , L ₅ ,.
_n-1 of the odd lines of the scan pulse X ₃ corresponding to the respective, X _5, · · · ·, and outputs the X _n-1, X electrodes of each line, the cell 6 address electrodes becomes both active Generates wall charges. Then, the light emission operation is performed in the subsequent sustain discharge period, the operation of one subfield is repeated by the number of subfields, and the operation of the second field is completed.
During the period of the second field, data of all even lines displayed in the next field is input to the control circuit 1 together with a synchronization signal. Then, the input data of all even lines is written to the second memory 12.

[0015]

A conventional PDP device PD
In No. 4, one scanning drive circuit was provided for one X electrode. However, when performing interlaced display, only half of the scan drive circuits are used during the address period. Therefore, since the scanning drive circuit has redundancy, the circuit cost increases, which is one of the factors that hinder the cost reduction of the PDP device.

To solve such a problem, see, for example,
In the PDP device disclosed in JP-A-133621, the number of scan driving circuits is reduced by half to reduce the cost of the PDP device. FIG. 15 shows a PDP device disclosed in Japanese Patent Laid-Open No. 10-133621 as a PDP device PD5. In FIG. 15, the PDP device PD5 is PD
Similarly to the P device PD4, the control circuit 1, the first memory 11, the second memory 12, the X electrode maintaining circuit 31, the scan driving circuit 3
2, an address driving circuit 21, and a panel 5 including a plurality of cells 6. However, unlike the PDP device PD4, the Y electrode maintaining circuit includes an odd Y electrode maintaining circuit 42 and an even Y electrode maintaining circuit 43. Also X
As for the electrodes, adjacent even-odd electrodes are connected to a common scanning drive circuit 32 as a set. As for the Y electrodes, the Y electrodes on the odd lines are connected to the odd Y electrode maintaining circuit 4.
2, the even-numbered line Y electrode is
Are connected in common.

The operation of the PDP device PD5 will be described. FIG. 16 is a diagram showing a state of a drive waveform of each electrode of the PDP device PD5. The difference from the PDP device PD4 is that the same scan pulse is output to the commonly connected adjacent X electrodes during the address period in both the first field and the second field, and the sustain discharge period in the first field. In the above case, the sustain discharge pulse is applied only to the Y electrodes of the even lines, and the Y electrodes of the odd lines are kept at a constant potential. During the sustain discharge period of the second field, the sustain discharge pulse is applied only to the Y electrodes of the odd lines, and The only difference is that the electrodes are kept at a constant potential. In this way, although the same scan pulse is applied to the adjacent X electrodes, only the Y electrodes of the even lines are discharged in the first field for displaying the even lines, and the odd lines are discharged in the second field for displaying the odd lines. Of the PDP device PD4
In this case, the interlaced display can be performed with half the number of scan drive circuits.

However, according to the above publication, the potential of the Y electrode of the non-display line is controlled to be kept constant in order to prevent the discharge of the cell of the non-display line during the sustain discharge period. Therefore, under the influence of the sustain discharge pulse applied to the X electrode during the sustain discharge period, charge and discharge are repeated by the capacitance between the X electrode and the Y electrode of the non-display line adjacent thereto. .

That is, it is considered that a capacitance exists between the electrodes, and between the address electrodes and the X electrodes, between the address electrodes and the Y electrodes, and between the X electrodes and the Y electrodes belonging to different display lines. (For example, the scan electrode X2 and the common electrode Y
1) and between the X electrode and the Y electrode belonging to the same display line (for example, the scan electrode X1 and the common electrode Y1). Among them, the values of the capacitances of the former three are sufficiently smaller than the values of the capacitance of the latter, so that they can be ignored here. However, the value of the capacitance between the X electrode and the Y electrode belonging to the same display line is large, and by repeatedly applying the above-described sustain discharge pulse during the sustain discharge period, the charge and discharge of this capacitive load is performed. Is repeated. This charging / discharging operation is unavoidable in a row for performing display, but is completely unnecessary in a non-display line.

For example, in the second field of FIG. 16, odd lines are displayed. In this case, between the scan electrode X2 and the common electrode Y2, between the scan electrode X4 and the common electrode Y4,... .. the scan electrode Xn and the common electrode Yn
Between the electrodes, charging and discharging of the capacitance between the electrodes occurs, and unnecessary power that does not contribute to light emission is consumed.

In addition, there is a problem that flicker is easily generated in interlaced display, and a problem that flicker is easily conspicuous when non-interlaced input signals (for example, video output of a personal computer) are displayed. There is also.

In view of the above problems, it is an object of the present invention to realize a driving method with low power consumption and less flicker in a PDP device in which the number of scanning driving circuits is reduced by half.

[0023]

Means for Solving the Problems Claim 1 of the present invention
The scan electrode includes a scan electrode and a common electrode arranged in parallel, and an address electrode orthogonal to the scan electrode and the common electrode. The scan electrodes of adjacent odd-numbered lines and even-numbered lines are commonly connected one by one, Using a plasma display device that can divide the common electrode into even lines and odd lines and control each independently, in at least one of a reset period and a sustain discharge period, an even line or an odd line Controlling the common electrode and the scan electrode on one line to perform an image data display operation, setting the potential of the common electrode on the other line to a floating state, and performing the display operation on the common line and the common line; The line that causes the electrode potential to be in a floating state can be alternately switched for each odd and even field. In performs interlaced display of the image data, a plasma display device driving method.

According to a second aspect of the present invention,
2. The method according to claim 1, wherein the image data is a non-interlaced input signal, and the non-interlaced input signal is converted into an interlaced signal including the odd and even fields. Perform race display.

According to a third aspect of the present invention,
2. The method according to claim 1, wherein the image data is an interlaced input signal, and the frame period of the interlaced display is displayed shorter than a frame period of the interlaced input signal. .

According to a fourth aspect of the present invention,
4. The method according to claim 3, wherein one frame of the interlace input signal corresponds to a plurality of frames of the interlace display, and the plurality of frames of the interlace display. Are the same image as the one frame of the interlaced input signal.

According to a fifth aspect of the present invention,
4. The method according to claim 3, wherein one frame of the interlace input signal corresponds to a plurality of frames of the interlace display, and the plurality of frames of the interlace display. Performs image processing using a first frame that is the same image as the one frame of the interlace input signal, the one frame of the interlace input signal, and another frame of the interlace input signal. The image includes at least one of the second frames that are images.

According to a sixth aspect of the present invention,
A scan electrode and a common electrode arranged in parallel, and an address electrode orthogonal to the scan electrode and the common electrode, wherein the scan electrode and the common electrode are alternately arranged, and the scan of adjacent odd-numbered lines and even-numbered lines is performed. The electrodes are commonly connected one by one, and the common electrode is divided into an even line and an odd line so that they can be independently controlled. In at least one of the reset period and the sustain discharge period, the even line or the odd line A line that controls the common electrode and the scan electrode of one of the lines to perform an image data display operation, causes the potential of the common electrode of the other line to float, and performs the display operation. And the line for setting the potential of the common electrode to a floating state is alternately switched for each of the odd and even fields. The image data to interlaced display between a plasma display device.

According to a seventh aspect of the present invention,
Scan electrodes and common electrodes arranged in parallel, and address electrodes orthogonal to the scan electrodes and common electrodes,
A switching circuit for controlling transmission of a signal to the common electrode, wherein the scan electrodes of adjacent odd-numbered lines and even-numbered lines are commonly connected one by one, and the switching circuit connects the common electrode to an even-numbered line and an odd-numbered line. And at least one of a reset period and a sustain discharge period to control the common electrode and the scan electrode of one of the even lines or the odd lines. The display operation of image data is performed, the potential of the common electrode of the other line is set to a floating state, and the line for performing the display operation and the line for setting the potential of the common electrode to a floating state are odd and even numbers. In the plasma display device, the image data is displayed in an interlaced manner by alternately switching every field. That.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 shows a PDP device PD1 used in the plasma display device driving method according to the first embodiment of the present invention. PDP
The device PD1 has the same structure as the PDP device PD5 shown in FIG. That is, the PDP device PD1 includes the control circuit 1,
Address drive circuit 21, X electrode sustain circuit 31, scan drive circuit 32, odd Y electrode sustain circuit 42, even Y electrode sustain circuit 43, panel 5, cell 6, address electrodes W1 to W1
0, X electrodes X1 to X8 and Y electrodes Y1 to Y8. For more specific description, the number of cells 6 is 8 × 10 here.

Next, a method of driving the PDP device PD1 will be described with reference to FIGS. 2 and 3
FIG. 3 is a diagram showing a state of a drive waveform of each electrode when performing interlaced display in the PDP device PD1 shown in FIG.
FIG. 2 shows one subfield of the first field for displaying even lines, and FIG. 3 shows one subfield of the second field for displaying odd lines. Here, one subfield is divided into three periods, a reset period, an address period, and a sustain discharge period. The reset period is a period in which the lighting cells are initialized. During the reset period in the first field, the address electrodes W1 to W10 and the X electrode X1
X8 and Y electrodes Y2, Y4,...
8 during the reset period in the second field, and to the address electrodes W1 to W10, the X electrodes X1 to X8, and the Y electrodes Y1, Y3,. Then, a discharge is caused between the electrodes, and thereafter, the discharge is stopped by the erase pulse, and the state of the cell 6 is made uniform.

The address period is a period for selecting a cell to be displayed. In the address period in the first field, the address drive circuit 21 generates the address electrode W based on the data.
Address pulses L ₂ , L ₄ ,...
· Gives L _8, selectively activate the address electrodes. At this time, the scan driving circuit 32 outputs the address pulse L
_{2, ····,} X electrode X2 corresponding to each of L _8, ····,
X8 is line-sequentially scanned, and scan pulses X ₂ ,..., X ₈ are applied in order from the scan electrode X2. However, X electrodes X1,..., X7 are also X electrodes X2,.
And the same pulse is applied. In the address period in the second field, the address drive circuit 21 generates the address electrode W1 based on the data.
Sequential address pulse to the _{~W10 L 1, L 3, ····} ,
Give L _7, selectively activate the address electrodes. At this time, the scan driving circuit 32 outputs the address pulse L
_{1, ····,} X electrodes X1 corresponding to each of L _7, ····,
Performs line sequential scanning to X7, the scan pulse X ₁ from the scan electrode X1 in this order, ..., and applies the X _7. However, X electrodes X2,..., X8 are also X electrodes X1,.
And the same pulse is applied. Then, in the cell 6 in which the X electrode and the address electrode are both active in each line, a discharge occurs, and the space charges generated by the discharge move to the electrodes of opposite polarities and are accumulated as wall charges. After the generation of the wall charges, the discharge stops because the substantial potential difference between the X electrode and the address electrode is smaller than the potential difference that can maintain the discharge. At this time, in order to generate wall charges in the cell 6 that performs display, it is necessary to make the value of the potential difference between the X electrode and the address electrode sufficiently large to cause discharge.
In a cell that does not perform display, the potential difference between the X electrode and the address electrode needs to be a small value that does not cause discharge. As described above, when applying the scan pulse and the address pulse, it is necessary to pay attention to the above relationship.

The sustain discharge period is a period in which display is performed using wall charges accumulated in the address period. In the first field, the X electrodes X1 to X8 and the Y electrodes Y2,
.., And a sustain discharge pulse is applied with a phase shift of 180 degrees to Y8. In the second field, the X electrodes X1 to X1
A sustain discharge pulse whose phase is shifted by 180 degrees is applied to X8 and the Y electrodes Y1,..., Y7 of the odd lines.

For example, first, a sustain discharge pulse is applied to each of the X electrodes X1 to X8. Wall charges are accumulated on the X electrode of the cell 6 selected to display during the address period, and a discharge is generated by applying a voltage having the same polarity as the voltage due to the wall charges. The value of the voltage of the sustain discharge pulse at this time needs to be a value such that a discharge does not occur by itself, but a discharge occurs when the voltage is superimposed on the potential generated by the wall charges. Note that since no cell 6 has a wall charge on the X electrode in the cell 6 where no display is performed, no discharge occurs even when the sustain discharge pulse is applied. When a discharge occurs in the cell 6, a space charge is generated, wall charges having a polarity opposite to the applied voltage are accumulated on each electrode, and a substantial potential difference between the X electrode and the Y electrode is obtained. The potential difference becomes smaller than the voltage required to maintain the discharge, and the discharge stops.

Next, in the first field, the even lines
In the second field, a sustain discharge pulse is applied to each of the odd-numbered line Y electrodes. In the cell 6 in which discharge has been performed until immediately before to generate wall charges, the wall charges are accumulated on the X electrode and the Y electrode, and the discharge is started again by application of the sustain discharge pulse. On the other hand, in the cell 6 in which the discharge has not been performed immediately before, no wall charge is accumulated between the X electrode and the Y electrode, so that even if a sustain discharge pulse is applied to the Y electrode, a sufficient potential difference is not obtained. No discharge occurs.

Light emission continues during the sustain discharge period by repeating this operation. In the first field, no sustain discharge pulse is applied to the odd-numbered line Y electrodes. In the second field, no sustain discharge pulse is applied to the even-numbered line Y electrodes. However, in the second field, the emission of the even-numbered lines does not continue. Therefore, the odd lines in the first field and the even lines in the second field are lines on which no display is performed.

In the present embodiment, during the sustain discharge period, the potential of the Y electrode of the non-display line is made to be in a floating state, thereby invalidating the capacitive load between the Y electrode and the X electrode in the same line by charging and discharging. The power can be reduced. In this case, the potential of the Y electrode follows the change in the potential of the X electrode belonging to the same display line, and almost no charge / discharge of the capacitance between the electrodes occurs. As a result, consumption of the reactive power can be suppressed low. .

FIG. 4 shows, by way of example, how voltage pulses are applied to each electrode during the sustain discharge period of the second field. A common sustain discharge pulse is supplied to all X electrodes, but odd Y electrodes Y1, Y3,
.., Y7 are supplied with a sustain discharge pulse having a polarity opposite to that of the X electrode.

On the other hand, the potential of the Y electrode on the non-display line is in a floating state. The potential of the floating Y electrode is
Under the influence of the closest X electrode, a value close to the potential of the X electrode is obtained. Since FIG. 4 shows the state of the second field, even Y electrodes Y2, Y4,.
.., Y8 becomes the floating potential (the hatched portion is the floating potential).

Similarly, in the case of the first field, the odd Y electrodes Y1, Y3,..., Y7 are set to the floating potential state.

When the X electrodes and the Y electrodes are alternately arranged as in the PDP device PD1 shown in FIG. 1, the Y electrodes of the non-display line are such that two X electrodes are close to each other. , And takes a value closer to the potential of the X electrode under the influence of the X electrode. Therefore, consumption of the reactive power can be suppressed more reliably.

The control for setting the floating potential can be easily realized by providing an appropriate switching mechanism in the odd-numbered Y electrode holding circuit 42 and the even-numbered Y electrode holding circuit 43.

The non-display line Y during the sustain discharge period
Although the method of reducing the reactive power by making the electrodes floating has been described, it is desirable that the Y electrode of the non-display line be floated by applying this method even during the reset period. By doing so, the reactive power can be reduced even during the reset period, and unnecessary light emission can be prevented from occurring in the row where no display is performed. Also in the driving waveforms of FIGS. 2 and 3,
During the periods other than the address period, the Y electrodes of the non-display lines are in a floating state. During the address period, it is necessary to apply a constant voltage to both the odd-numbered Y electrode and the even-numbered Y electrode in order to prevent erroneous discharge.

When the driving method of the plasma display apparatus according to the present embodiment is used, the consumption of the reactive power can be reduced by setting the Y electrode of the non-display line in a floating state during the reset period or the sustain discharge period.

In the PDP device PD1 shown in FIG.
The odd-numbered Y electrode maintaining circuit 42 and the even-numbered Y electrode maintaining circuit 43 have independent configurations. Instead of these, one Y-electrode maintaining circuit 41 is used, and if necessary, an odd-numbered or even-numbered Y-electrode maintaining circuit is used. Of a circuit configuration having a switching circuit 44 capable of selecting an output to
The DP device PD2 may be used. By doing so, the number of circuits can be reduced, and miniaturization and cost reduction can be achieved.

The arrangement of the electrodes may be changed as shown in FIG. In the configuration of FIG. 6, an even-odd X electrode commonly connected is arranged so as to sandwich an adjacent even-odd Y electrode. With such an electrode arrangement, erroneous discharge between adjacent rows (for example, scan electrode X
It is unlikely that an erroneous discharge occurs between the second electrode 2 and the common electrode Y1).

In FIG. 6, the Y-electrode holding circuit is used on both the odd and even sides, and has the same configuration as that of FIG. 1, but of course, as shown in FIG. A configuration including a circuit and a switching circuit may be employed.

Embodiment 2 In the present embodiment, interlaced display is performed on a non-interlaced input signal by using the plasma display device driving method according to the first embodiment. FIG. 7 shows a time chart when converting a non-interlaced input signal into an interlaced signal.

For example, one field cycle is 1/60
For a non-interlaced input signal of [s] = 16.7 [ms], the control circuit 1 stores signal information in an internal memory and performs signal processing when the input of the first field is completed. , The data of the first field is separated into the data of the odd field and the data of the even field. Then, the PDP device displays the odd field and the even field at a field period of 1/120 [s], and a total of 1 field is displayed.
One frame of interlaced display corresponding to one field of the input signal is performed at a frame period of / 60 [s].

It is assumed that a PDP apparatus having 480 scanning lines has two scan lines.
56 = ²⁸ gradations VGA input to 1/60 of [s] = 16.
In the case of non-interlaced display with a field cycle of 7 [ms], assuming that the address data write time per line is 2.5 [μs], 2.5 [μs] × 480 = 1.2 per subfield. [Ms], and 1.2 [ms] × 8 = 9.6 [ms] in 8 subfields.
Also.

In this embodiment, considering that the address pulse is written only on the display line and that the VGA input is displayed in an interlaced manner, the address period per field is half that in the non-interlaced display. ,
2.5 [μs] × 240 = 0.
6 [ms], 0.6 [ms] × 8 in 8 subfields
8 = 4.8 [ms]. Then, it is possible to display one field at 1/120 [s] = 8.3 [ms], and even with VGA input, one frame image can be interlaced and displayed at a frame period of 1/60 [s]. is there.

FIG. 8 shows an example of the frame structure of the interlaced signal after the conversion shown in FIG. In FIG.
The odd field is composed of first to third odd subfields and idle periods, and the even field is composed of first to third even subfields and idle periods.
³ = 8 gradations can be output. Of course, the number of gradations is not limited to this, and the number of subfields may be arbitrarily increased or decreased.

Further, the frame configuration example shown in FIG. 8 may be modified as shown in FIG. In FIG. 9, the first odd-numbered subfield is followed by the first even-numbered subfield, and thereafter, even and odd are alternately arranged. Since the difference in the arrangement of the subfields does not affect the light emission intensity, the order of the subfields may be arbitrarily changed.

In this embodiment, as in the first embodiment, during interlace display, the Y electrode of the non-display line is operated in a floating state during the reset period or the sustain discharge period, and the X electrode and the Y electrode are operated. Reduction of the consumption of the reactive power between the electrode and the electrode is intended.

The use of the plasma display device driving method according to the present embodiment enables interlaced display with less flickering even for non-interlaced input signals.

Embodiment 3 In the present embodiment, interlaced display is performed by using the plasma display device driving method according to the first embodiment with respect to an interlaced input signal, with a frame period shorter than that of the input signal. FIG. 10 shows a time chart when converting into an interlaced signal in which the frame period is half (double speed operation) of the input signal.

For example, in the NTSC signal, one frame is displayed at a frame period of 1/30 [s] using an odd field and an even field whose field period is 1/60 [s]. For such an interlaced input signal such as an NTSC signal, the control circuit 1 displays the odd field and the even field at a field cycle of 1/120 [s], and displays 1 at a frame cycle of 1/60 [s]. Display the frame. Specifically, the frame period is converted by shortening the sustain discharge period in each subfield.

In FIG. 10, in the output signal, 1/60
The image of the first frame having the frame period of [s] is
Steps 1 and 2 are repeated twice. That is, one frame of the interlace input signal corresponds to a plurality of frames of the interlace display of the PDP output, and all of the plurality of frames are the same as one frame of the above-described interlace input signal. Image.
FIG. 11 shows a frame configuration example of the interlaced signal after the conversion shown in FIG. In FIG. 11, first frames 1 and 2 respectively include a first odd field including first to third odd subfields, and first to third frames.
And a first even field composed of even subfields. Although FIG. 11 shows an example in which 2 ³ = 8 gray levels can be output, the number of subfields may be arbitrarily increased or decreased. Also, the first frames 1 and 2 are
A frame configuration in which even and odd are mixed as shown in FIG. 9 may be adopted.

In this embodiment, as in the first embodiment, during interlace display, the Y electrode of the non-display line is operated in a floating state during the reset period or the sustain discharge period, and the X electrode and the Y electrode are operated. Reduction of the consumption of the reactive power between the electrode and the electrode is intended.

When the method of driving the plasma display device according to the present embodiment is used, the frame period is shortened, so that an image display with less flicker can be performed. Further, since the same one frame image is repeated a plurality of times, the brightness of the image can be prevented from being lowered.

In FIGS. 10 and 11, the same frame is repeatedly output twice. For example, in the first frame of the output signal, the first frame of the input signal is displayed as it is, and the output is performed. 1st frame of signal 2
In, a frame that has been subjected to image processing (for example, interpolation processing) using the first frame and the second frame of the input signal may be changed to be displayed. That is, one frame of the interlaced input signal corresponds to a plurality of frames of the interlaced display of the PDP output, and the plurality of frames correspond to one frame of the above-described interlaced input signal. In addition to the frame, the frame may include a frame obtained by performing image processing using one frame of the above-described interlace input signal and another frame of the interlace input signal. Then, a smoother moving image can be obtained.

In this case, however, the display start position of the output signal in FIG. 10 must be delayed by at least 1/60 [s]. To display a frame that has been subjected to image processing using the first frame and the second frame of the input signal in the first frame part 2 of the output signal, the first
This is because the second even field of the second frame of the input signal must be completed at the time when the first even field of the second frame starts.

Further, not only the first frame 2 but also the first frame
In the first frame, a frame that has been subjected to image processing using the first frame and the second frame of the input signal may be displayed. In that case, the display start position of the output signal in FIG. 10 needs to be after the end point of the second frame of the input signal.

[0064]

According to the plasma display apparatus driving method of the present invention, since the potential of the common electrode of the non-display line is in a floating state, the consumption of reactive power can be reduced.

According to the plasma display apparatus driving method of the present invention, an interlaced display with less flicker can be made even for a non-interlaced input signal.

According to the plasma display device driving method of the present invention, it is possible to display an image with less flicker.

According to the plasma display apparatus driving method of the present invention, it is possible to prevent the brightness of an image from being lowered.

According to the plasma display apparatus driving method of the present invention, a smoother moving image can be obtained.

According to the plasma display device of the present invention, the scan electrodes and the common electrodes are alternately arranged, so that the common electrode of the non-display line has two scan electrodes around it. Are closer to each other, and are more strongly influenced by the scan electrode, and take a value closer to the potential of the scan electrode. Therefore, consumption of the reactive power can be suppressed more reliably.

According to the plasma display apparatus of the present invention, since the switching circuit is provided, the number of circuits required for controlling the common electrode can be reduced, and the size and cost can be reduced. I can do it.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a plasma display device used in a plasma display device driving method according to a first embodiment;

FIG. 2 is a diagram showing driving waveforms of respective electrodes when displaying an even-numbered line using the driving method of the plasma display device according to the first exemplary embodiment;

FIG. 3 is a diagram showing a driving waveform of each electrode when displaying an odd-numbered line by using the driving method of the plasma display device according to the first exemplary embodiment;

FIG. 4 is a diagram showing waveforms of voltages applied to respective electrodes when displaying an odd-numbered line using the plasma display device driving method according to the first embodiment;

FIG. 5 is a diagram showing another configuration of the plasma display device used in the plasma display device driving method according to the first embodiment;

FIG. 6 is a diagram showing another configuration of the plasma display device used for the plasma display device driving method according to the first embodiment;

FIG. 7 is a diagram showing a time chart of an output of a PDP device when a non-interlaced input signal is interlaced and displayed using the plasma display device driving method according to the second embodiment.

FIG. 8 is a diagram showing a frame configuration when performing interlaced display using the plasma display device driving method according to the second exemplary embodiment;

FIG. 9 is a diagram illustrating another frame configuration when performing interlaced display using the plasma display device driving method according to the second embodiment;

FIG. 10 is a diagram showing a time chart of an output of a PDP device when an interlace input signal is displayed at a double speed operation by using the plasma display device driving method according to the third embodiment.

FIG. 11 is a diagram illustrating a frame configuration when performing interlaced display using the plasma display device driving method according to the third embodiment;

FIG. 12 is a diagram showing a vertical cross section of the plasma display device.

FIG. 13 is a diagram showing a configuration of a conventional plasma display device.

FIG. 14 is a diagram showing a driving waveform of each electrode of a conventional plasma display device.

FIG. 15 is a diagram showing a configuration of a conventional plasma display device with a reduced number of scan driving circuits.

FIG. 16 is a diagram showing a drive waveform of each electrode of a conventional plasma display device in which a scan drive circuit is eliminated.

[Explanation of symbols]

1 control circuit, 11 first memory, 12 second memory,
21 address drive circuit, 31 X electrode sustaining circuit, 32
Scanning drive circuit, 33 bus electrode, 34 transparent electrode, 4
1 Y electrode maintaining circuit, 42 Odd Y electrode maintaining circuit, 43
Even Y electrode sustaining circuit, 44 switching circuit, 5
Panel, 6 cells, 7 dielectric, 8 MgO layer, 9 phosphor, 10a front glass substrate, 10b rear glass substrate, X1 to Xn X electrode, Y1 to Yn Y electrode, W1 to
Wm Address electrode.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 650 G09G 3/20 650E 3/28 H04N 5/66 101B H04N 5/66 101 G09G 3/28 EF term (reference) 5C058 AA11 BA09 BA26 BB03 BB15 BB16 BB22 5C080 AA05 BB05 DD06 DD26 DD27 EE19 EE29 FF07 FF12 HH02 HH04 JJ02 JJ04 JJ06

Claims (7)

[Claims] A scan electrode and a common electrode arranged in parallel, and an address electrode orthogonal to the scan electrode and the common electrode, wherein the adjacent odd-numbered and even-numbered scan electrodes are commonly connected one by one; By using a plasma display device capable of dividing the common electrode into even lines and odd lines and independently controlling each of the lines, at least one of a reset period and a sustain discharge period includes an even line or an odd line. Controlling the common electrode and the scan electrode on one line to perform an image data display operation, setting the potential of the common electrode on the other line to a floating state, and performing the display operation on the common line and the common line. To alternately switch the line that brings the electrode potential to a floating state every odd and even field Performs interlaced display of the image data, a plasma display device driving method. 2. The interlaced display according to claim 1, wherein the image data is a non-interlaced input signal, and the non-interlaced input signal is converted into an interlaced signal including the odd and even fields to perform the interlaced display. Method for driving a plasma display device. 3. The plasma display device according to claim 1, wherein said image data is an interlace input signal, and said frame display of said interlace display is displayed with a shorter frame period than a frame period of said interlace input signal. Drive method. 4. One of the frames of the interlaced input signal corresponds to a plurality of frames of the interlaced display, and all of the plurality of frames of the interlaced display are:
4. The method according to claim 3, wherein the image is the same as the one frame of the interlaced input signal. 5. The method of claim 1, wherein one frame of the interlaced input signal corresponds to a plurality of frames of the interlaced display, and the plurality of frames of the interlaced display is Of a first frame that is the same image as one frame and a second frame that is an image processed using the one frame of the interlace input signal and another frame of the interlace input signal The method for driving a plasma display device according to claim 3, comprising at least one of them. 6. A scan electrode and a common electrode arranged in parallel, and an address electrode orthogonal to the scan electrode and the common electrode, wherein the scan electrode and the common electrode are alternately arranged, and adjacent odd lines and The scan electrodes of the even lines are commonly connected one by one, and the common electrodes are divided into even lines and odd lines, and can be independently controlled. In at least one of a reset period and a sustain discharge period, Controlling the common electrode and the scan electrode of one of the even lines or the odd lines to perform an image data display operation, bringing the potential of the common electrode of the other line into a floating state, and performing the display operation. And a line for causing the potential of the common electrode to be in a floating state for each of the odd and even fields. The image data to interlaced display by switching each other, the plasma display device. 7. An adjacent odd-numbered line, comprising: a scan electrode and a common electrode arranged in parallel; an address electrode orthogonal to the scan electrode and the common electrode; and a switching circuit for controlling transmission of a signal to the common electrode. And the scan electrodes of even lines are commonly connected one by one, and the switching circuit can divide the common electrode into even lines and odd lines and independently control each of them. In at least one of the periods, the common electrode and the scan electrode in one of the even lines or the odd lines are controlled to perform an image data display operation, and the potential of the common electrode in the other line is floated. A line for performing the display operation and a line for floating the potential of the common electrode. The image data to interlaced display by switching alternately odd and each even field, the plasma display device.