JP2000353656A - Pattern forming method and manufacture of semiconductor device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pattern forming method, together with a manufacturing method for a semiconductor device, wherein a pattern of high accuracy, with reduced edge roughness, is formed easily and in general purpose manner. SOLUTION: (1) A pattern formation method, comprises a process where a photoresist formed on a base body is exposed in a pattern, a background exposure process I where the entire surface of a forming region of the photoresist or a range comprising at least the region exposed in a pattern is exposed. In the background exposure process I, the condition for reducing the edge roughness of the photoresist pattern to be formed is selected and (2) the pattern formation of (1) is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of forming a pattern and a method of manufacturing a semiconductor device using the same. In particular, the present invention provides a pattern forming method suitable for forming a fine pattern and a manufacturing method suitable for manufacturing a semiconductor device including a step of forming a fine pattern.

[0002]

2. Description of the Related Art In the field of pattern forming technology, miniaturization has been increasingly advanced, and various problems have been caused by this. As one of them, there is a problem of edge roughness of a pattern. In particular, in recent years, as the design line width in semiconductor lithography becomes smaller, the edge roughness occupies, for example, 10% or more of the pattern line width, and reducing the edge roughness of the pattern has become an important issue.

For example, as a conventional technique for reducing edge roughness in electron beam lithography, as shown in “Applied Physics”, Vol. 63, No. 11, p.
Reduction of the average molecular weight and polydispersity of the resist, the technique of using a base resin having a large degree of freedom of the main chain, and the 16a-B- of the 59th Annual Meeting of the Japan Society of Applied Physics, p606
As shown in FIG. 11, there is a technique of performing a correction for increasing an exposure amount at a pattern edge in order to decompose a molecular aggregate exposed on a resist pattern side wall.

In addition, Japanese Patent Application Laid-Open No. 8-195339 describes an electron beam drawing technique for reducing edge roughness by reducing the shot pitch of a contour portion of a pattern.
A pattern formation technique for improving edge roughness by using a resist material having a specific molecular structure is described.
However, these conventional technologies are not always easy to implement, or lack general versatility because commonly used resists cannot be used,
Alternatively, there is a problem that it is difficult to apply a fine pattern.

[0005]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems and can effectively reduce the edge roughness of a pattern, thereby realizing high-precision pattern formation, and can be implemented easily. It is an object of the present invention to provide a pattern forming method which is versatile with respect to a resist material or the like and can be suitably applied even to a fine pattern, and a method of manufacturing a semiconductor device which forms a circuit pattern by forming such a highly accurate pattern. The purpose is to provide.

[0006]

According to the present invention, there is provided a pattern forming method comprising the steps of: exposing a photoresist formed on a substrate to a pattern;
A step of exposing the entire surface of the photoresist formation region or at least a range including a region to be exposed in the pattern is provided (this step is referred to as a background exposure step in the present specification). The method is characterized in that conditions for reducing the edge roughness of a photoresist pattern to be formed are selected and performed.

In a method of manufacturing a semiconductor device according to the present invention, a photoresist formed on a substrate is exposed in a pattern to obtain a photoresist pattern, and the photoresist pattern is used to form a semiconductor circuit pattern. Not only a pattern of a conductor such as a semiconductor or a wiring, but also a pattern of an insulator or other patterns formed on a semiconductor device as needed). And a background exposure step of exposing the entire surface of a photoresist formation region or at least a range including a region where pattern exposure is performed, and the background exposure step reduces edge roughness of a photoresist pattern to be formed. It is characterized by selecting and performing conditions.

In the present invention, in the background exposure step, the relationship between the conditions of the background exposure and the edge roughness of the photoresist pattern to be formed is obtained (for example, it can be obtained from an experimental value obtained by actual measurement, or obtained by simulation). Can be performed using conditions (preferably optimal conditions) for reducing the edge roughness obtained therefrom. The background exposure step may be performed before or after the pattern exposure step, and the order of the steps is arbitrary.

According to the present invention, by performing the above-described background exposure step, a resist pattern with reduced edge roughness can be obtained, the edge roughness of the formed pattern can be improved, and a highly accurate pattern can be formed. Obtainable. Although many techniques for performing double exposure including overall exposure have been proposed, there is no proposal that focuses on employing such an exposure technique for improving edge roughness. For example, electron beam irradiation and whole surface ion beam,
Japanese Patent Application Laid-Open No. 56-164531 discloses a technique for combining irradiation with the entire surface of an electron beam, ultraviolet rays, X-rays, or the like, but this technique is for improving the photosensitivity of a resist. Does not mention edge roughness. Japanese Patent Application Laid-Open No. Sho 63-78 discloses a technique for combining irradiation of the entire surface of the resist with an energy beam.
No. 523, this is a technique for achieving high contrast. Japanese Patent Application Laid-Open No. Sho 6 (1994) discloses a technique for pre-exposing a resist on a film with UV light or visible light.
It is described in Japanese Patent Application Laid-Open No. 2-78550, which is a technique for increasing the sensitivity at the time of high contrast processing of a resist.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be further described below, and preferred specific examples will be described with reference to the drawings. Needless to say, the present invention is not limited to the illustrated embodiment.

In the following description, the present invention will be described with respect to the case where the present invention is embodied with respect to the exposure of a semiconductor circuit pattern, and in particular, the case where a pattern is formed by electron beam lithography. The present invention is not limited to application to lithography, but can be applied to optical lithography, X-ray lithography, various charged beam lithography, and the like.

Embodiment 1 In this embodiment, the present invention is applied to perform double exposure of a resist to increase the slope of the stored energy of the resist pattern and reduce the edge roughness of the resist pattern. It is an example. In the present embodiment, the present invention is applied to the manufacture of a semiconductor device having a miniaturized and integrated semiconductor circuit pattern, which requires high-precision pattern formation.

Please refer to FIG. 1 to FIG. FIG. 1 is a view for explaining an exposure method for forming a resist pattern in this example, FIG. 2 is a view showing a profile of stored energy of the pattern, and FIG. 3 is an exposure amount and an edge of background exposure (background exposure). It is a figure showing the relation with roughness. FIG. 4 is a diagram showing a schematic configuration of an electron beam lithography machine that can be used in the embodiment.

In this embodiment, as schematically shown in FIG. 1, when pattern exposure II is performed, the entire surface of a material to be exposed (for example, a semiconductor wafer) or the pattern exposure II is exposed.
A background exposure (background exposure) I is performed to expose a range including a region where is performed. The background exposure I only needs to include at least a portion for performing the pattern exposure II. The background exposure I and the pattern exposure II may be performed in any order,
That is, the order of the exposures I and II is arbitrary.

In this embodiment, the present invention is embodied in a form in which electron beam exposure is performed using an electron beam lithography machine as illustrated in FIG. The illustrated and illustrated electron beam direct exposure apparatus includes an electron gun 1
An electron beam (here, made of LaB ₆ ) is radiated to the entire surface of the forming opening of the mask of the first shaping aperture 21, and an electron beam image from the opening is formed on the mask of the second shaping aperture 22. An electron beam image having a different size and shape is formed by projecting the variable shape opening and the collective figure forming opening at different positions by the shaping deflector 4, and an arbitrary size and shape are formed using the electron beam image. This is an exposure machine that transfers a desired pattern to a resist on a material 9 to be exposed (semiconductor wafer or the like).

In FIG. 4, reference numeral 3 denotes a converging lens, 5 denotes a projection lens, 6 denotes an objective lens, 7 denotes a high-speed sub deflector, and 8 denotes a high precision deflector. Reference numerals 10A and 10B denote continuous stage movement and stage step movement, respectively, of a wafer stage or the like forming a support.

In the present embodiment, for example, double exposure is performed by using the above-described exposure apparatus as shown in FIG. That is, the above-described background exposure I and pattern exposure II are performed on the pattern.

FIG. 2 shows pattern positions (A and A 'in FIG. 2).
Represents the pattern V of the stored energy of the pattern by graphing the relationship between the stored energy of the pattern with respect to A and A 'in FIG. 1. In this embodiment, the background V Since the exposure I is performed, the exposure amount of the pattern exposure is added to the exposure amount of the background exposure I. By appropriately performing the background exposure I, the energy amount can be changed while maintaining the shape of the stored energy profile V, as shown in FIG.

As the profile V of the stored energy is steeper, that is, as the inclination of the profile V of the stored energy is larger, the edge roughness can be reduced.
In particular, the edge roughness can be effectively reduced by making the slope of the stored energy near the threshold value of the resist used for pattern formation maximum. Note that FIG.
In the case of, if there is no background exposure I, the profile V
Will not reach the threshold.

In the present invention, the desired effect can be obtained by selecting the conditions for reducing the edge roughness of the photoresist pattern to be formed in the background exposure step. And a condition for reducing the edge roughness obtained from the relationship between the edge roughness of the photoresist pattern to be formed,
It is particularly preferable to use the optimal conditions that minimize the edge roughness. The relationship between the background exposure condition and the edge roughness of the pattern to be formed may be obtained by actually performing an experiment or by simulation. In the case of obtaining by simulation, parameters of the Gaussian distribution of the pattern profile V shown in FIG.

FIG. 3 shows an NEB22 (manufactured by Sumitomo Chemical Co., Ltd.) which is a 250 nm-thick negative resist for electron beam lithography applied on an 8-inch silicon substrate, and has an isolated pattern as shown in FIG. This is an example in which the above-described background exposure I and pattern exposure II have been performed. At this time, the exposure amount of the background (background) exposure I was changed variously, and the edge roughness in each case was measured. Edge roughness (nm) was determined as a 3Σ value.
The relationship between the exposure amount of the background exposure I and the edge roughness is shown in a graph III.

By measuring the relationship between the exposure amount of the background (background) exposure I and the edge roughness as shown in FIG. 3, optimum background exposure conditions can be obtained.
In this case, for the pattern exposure II, 4.4 μC / cm ² was set as an exposure value suitable for the resist to be used. From FIG. 4, the exposure amount of the background exposure I was set to about 1.6 μC / cm ² (see FIG. 4 indicates that the edge roughness is at a minimum. From this, it can be seen that the optimum conditions are that the exposure amount of the pattern exposure II is 4.4 μC / cm ² and the exposure amount of the background exposure I is about 1.6 μC / cm ² .

By forming the resist pattern on the basis of the above, a resist pattern with improved edge roughness is obtained. When a semiconductor circuit pattern is formed by this, a high-precision circuit pattern with improved edge roughness is obtained. Could be obtained.

The above method can be applied to any resist. Although a negative resist is used in the above example, a positive resist is similarly effective. In addition, the above method can be carried out using a conventionally used apparatus as it is, and can be carried out relatively easily. It is extremely effective for pattern formation, for example, line width control in EB drawing or the like as described above, and can be said to be a practical technique.

Although the above description has been made by taking electron beam lithography as an example, as described above, the present invention can be applied to various other pattern formation exposure techniques. In addition to the case of forming an isolated pattern as shown in FIG. 1, various other patterns such as a gate pattern, a line pattern,
An AND space pattern is also effective in reducing the edge roughness.

Further, the present invention is not limited to a specific substrate or resist, but is very versatile. For example, polysilicon, an oxide film (such as SiO ₂ ), a nitride film (Si
N, SiTi, etc.), silicide (WSi ₂ , TiSi)
₂ , CoSi ₂ , NiSi, etc.), organic films, etc., and can be used to form patterns of various materials. Effective in reducing edge roughness of various patterns formed using organic and inorganic resists applied and formed on these materials. It is.

[0027]

According to the method of forming a pattern and the method of manufacturing a semiconductor device of the present invention, the edge roughness of a pattern can be effectively reduced, and a highly accurate pattern can be formed. In addition, the present invention can be easily implemented, has an effect that it is versatile for a resist material to be used, and can be suitably applied to a fine pattern.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining exposure according to an embodiment of the present invention.

FIG. 2 is a diagram for describing a profile of a pattern stored energy in the embodiment of the present invention.

FIG. 3 is a diagram for explaining a relationship between an exposure amount of background exposure and edge roughness.

FIG. 4 is a schematic view of an electron beam lithography exposure apparatus that can be used.

[Explanation of symbols]

I: background exposure, II: pattern exposure, III.
..Relationship between exposure amount of background exposure and edge roughness, IV
... Optimal conditions (of exposure amount of background exposure), V... Profile of stored energy of pattern.

Claims (4)

[Claims] 1. A pattern forming method comprising a step of exposing a photoresist formed on a substrate in a pattern, wherein the background exposing the entire surface of a photoresist formation region or at least a region including the region to be exposed in the pattern is exposed. A pattern forming method comprising: an exposure step; and performing the background exposure step by selecting a condition for reducing edge roughness of a photoresist pattern to be formed. 2. The method according to claim 1, wherein the background exposure step is performed using a condition for reducing edge roughness obtained from a relationship between a background exposure condition and an edge roughness of a photoresist pattern to be formed. 4. The pattern forming method according to 1. 3. A method for manufacturing a semiconductor device comprising the steps of: exposing a photoresist formed on a substrate to a pattern to obtain a photoresist pattern; and forming a semiconductor circuit pattern using the photoresist pattern. A background exposure step of exposing the entire surface or at least a range including a region to be exposed in the pattern, and the background exposure step is performed by selecting conditions for reducing edge roughness of a photoresist pattern to be formed. A method for manufacturing a semiconductor device, comprising: 4. The method according to claim 3, wherein the background exposure step is performed using a condition for reducing edge roughness obtained from a relationship between a background exposure condition and an edge roughness of a photoresist pattern to be formed. 13. The method for manufacturing a semiconductor device according to item 5.