JP2000353400A - Circuit for detecting mrom leak defect, and mrom mixed chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily detect a defective MROM in a short time without missing a defective MROM by controlling a group of transistors constituting an MROM to the prescribed state in accordance with kinds of test, and taking out a signal detecting that leak is caused in one part of the group of transistors. SOLUTION: During a period of performing a NOP instruction of a CPU, DC leakage defect detecting measurement is performed. After a MROM mixed chip is turned into a test mode and a pre-charge transistor 3a, a column select- transistor 3b, a cell selector transistor 3c, and a ROM cell transistor 3d are fixed in the prescribed state, leakage is detected by a leak detecting circuit provided in a MROM circuit 3, and this is outputted to the outside from a flag output circuit. Therefore, off-leakage measurement of various transistors in the MROM circuit 3 can be performed by DC voltage, it can be discriminated by one monitor terminal of a port circuit sharing a monitor whether leakage defect of MROM 16 bits exists or not.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an M (mask) RO
MROM used for M embedded chip, especially for reliability evaluation of various transistors and reject test at shipping
The present invention relates to a leak failure detection circuit.

[0002]

2. Description of the Related Art Conventionally, there is no MROM-embedded chip provided with an MROM leak defect detection circuit. Therefore, when a sample is shipped to the market and a low-frequency operation is performed, a defective MROM-embedded chip due to MROM leak occurs (charge). Data corruption due to omissions) occurred frequently.

[0003]

Therefore, a low-speed frequency operation test (hereinafter referred to as fmi
n test), and the evaluation may be performed.
The fmin test time for a Kbyte MROM mixed chip is the test time of one sample t = (system clock *
4) * (Memory size / 2) = (1 / 32KHz *)
4) * (128K / 2) = 125usec 65536 = 8.
Since it takes two seconds, when the number of samples is 10,000, it takes about 23 hours and is not practical.

Further, since many MROM leak failures depend on frequency, there is a great possibility that a failure having a frequency of 32 kHz or less is overlooked, and it is difficult to reject an MROM leak failure sample.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide an MROM leak defect that can be detected easily and in a short time without overlooking an MROM defect in an MROM mixed chip. Detection circuit and MR equipped with this MROM leak failure detection circuit
An object is to provide an OM mixed chip.

[0006]

In order to achieve the above object, the present invention is characterized in that an MROM and an MRO
Control means for controlling a group of transistors constituting M to a predetermined state according to the type of test; leak detection means for detecting that a leak has occurred in a part of the transistor group; Output means for extracting the detection signal when detected.

According to a second aspect of the present invention, the output means outputs the detection signal as serial data sequentially from one output terminal.

According to a third aspect of the present invention, the transistor group includes:
A column selector transistor, a cell selector transistor, a ROM cell transistor, and a disable transistor are used to detect leaks of the column selector transistor, the cell selector transistor, and the disable transistor in each of the three types of tests, and the ROM is used in the subsequent one type of test. The cell transistor leak is detected and this ROM
To detect the leak of the cell transistor, a leak failure detection test is performed a plurality of times after selecting an address for setting all the ROM data to "1".

According to a fourth aspect of the present invention, the leak detecting means has a sense amplifier for detecting a potential of a precharge output line of the MROM, and the reference voltage of the sense amplifier is set to the M level.
It is changed between when the ROM is used in the normal use mode and when it is used in the mode for detecting the MROM leak failure.

[0010] The features of the invention of claim 5 are as follows.
An MROM leak failure detection circuit according to any one of the above aspects is provided.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of an MROM mixed chip on which an MROM leak failure detection circuit of the present invention is mounted. MROM mixed chip 10
0 is port circuit 1, RAM2, MROM circuit 3, MRO
A flag output circuit 4 for outputting a flag that stands when the M circuit 3 has a leak, a monitor / port circuit 5 for outputting a flag from the terminal PTOUT, a system reset generation circuit 6,
It has a CPU 7, a mode setting circuit 8 for setting a leak test mode and the like, an address area decoding circuit 9, and an oscillation / clock generation circuit 10.

In FIG. 1, an MROM leak detection circuit (leak detection means) is composed of an MROM circuit 3, a flag output circuit 4, a monitor / port circuit 5, and a mode setting circuit 8. Also, in order to operate the MROM leak detection circuit, an oscillation / clock generation circuit 10, a CPU 7, a system reset generation circuit 6, a RAM (program start on RAM) 2, and a port for loading a test program from the outside to the RAM 2 Circuit 1 is also required.

FIG. 2 is a block diagram showing a detailed configuration example of the MROM circuit 3 described above. The MROM circuit 3 includes a control circuit 31, a VREF generation circuit 32, a precharge control signal generation circuit 33, an A01 generation circuit 34, a B0x generation circuit 35, a C07 generation circuit 36, a D01 generation circuit 37, a precharge transistor 3a, and a column selector transistor. 3b, a cell selector transistor 3c, a ROM cell transistor 3d, a disable transistor 3e, a sense amplifier circuit 3f, a data latch circuit 3g, a data output circuit 3h, and an R / S flip-flop (FF) circuit 3i. .

The sense amplifier 3f, the latch circuit 3g,
The RS flip-flop circuit 3i forms a leak detection circuit.

FIG. 3 is a block diagram showing a detailed configuration example of the flag output circuit 4 and the monitor / port circuit 5 described above. The flag output circuit 4 mainly includes a 16-bit buffer register circuit 4a, a 16-bit shift register circuit 4b, a 4-bit up counter 4c, and an ALL "1" detection circuit 4d.

The monitor / port circuit 5 includes a selector 5
1, an output buffer 52, and a NOR circuit 53.

FIG. 5 is a timing chart showing the operation of test 1 in the chip of FIG. FIG. 6 is a circuit diagram showing a detailed example of a control circuit of the MROM circuit shown in FIG. FIG. 7 is a circuit diagram showing a detailed example of the reference voltage generation circuit of the MROM circuit shown in FIG. FIG. 8 is a circuit diagram showing another detailed example of the reference voltage generation circuit of the MROM circuit shown in FIG. FIG. 9 shows the P of the MROM circuit shown in FIG.
FIG. 3 is a circuit diagram showing a detailed example of a RECNT generation circuit. FIG. 10 is a circuit diagram showing a detailed example of the A01 generating circuit of the MROM circuit shown in FIG. FIG. 11 shows the MR shown in FIG.
FIG. 3 is a circuit diagram showing a detailed example of a B0x generation circuit of the OM circuit. FIG. 12 is a circuit diagram showing a detailed example of the C07 generating circuit of the MROM circuit shown in FIG. FIG. 13 is a circuit diagram showing a detailed example of the D01 generation circuit of the MROM circuit shown in FIG. FIG. 14 is a circuit diagram showing a detailed example of the sense amplifier of the MROM circuit shown in FIG. FIG. 15 is a circuit diagram showing a detailed example of the 16-bit shift register circuit of the flag output circuit shown in FIG. FIG. 16 shows the 4-bit up counter and the ALL of the flag output circuit shown in FIG.
FIG. 3 is a circuit diagram showing a detailed example of a “1” detection circuit. FIG.
FIG. 2 is a circuit diagram showing a detailed example of a mode setting circuit shown in FIG.

Next, the operation of this embodiment will be described. The circuit shown in FIG. 1 is a system example having a 16-bit bus width and a ROM capacity of 128 Kbytes. Also, MROM
Leak tests can be classified into four types of test modes, including a column selector leak test, a cell selector leak test, a ROM cell leak test, and a disable transistor leak test.

The precharge control signal generation circuit 33, the A01 generation circuit 34, and the B0x generation circuit 3 of the MROM circuit 3
5, each control signal generated from the C07 generating circuit 36 and the D01 generating circuit 37 is set to the following logic based on the mode table shown in FIG.

A) Column selector input signal A01 = ((decoding of AL5 to AL1) * TESTI
V) + (TEST4 to 2) b) Cell selector input signal B0x = ((decoding of AL16 to AL10) * ROM
CS * TEST2V) + (TEST4-3 + TEST
1) c) ROM cell selector input signal C07 = ((decoding of AL9 to AL7) V + ROMC
SV * TEST3V) + (TEST4 + TEST2-
1) d) Disable TR gate input signal D01 = ((AL6 or AL6V) * PREV * ROM
CS * TEST4V) + (TEST3 + TEST1) e) PRECNT gate input signal PRECNT = (PRE * ROMCS) + (TEST4
1), PRE = (BT0V, PH2), PH1 Except for the ROM cell leak test, only the test mode is set by the mode setting circuit 8, and the off-leak defect detection test for each of the column selector, the cell selector, and the disable transistor is performed. It can be carried out.

The ROM cell leak test is basically for performing an off-leakage defect detection test of the ROM cells connected to C0 to C7 with respect to a random address on the physical MAP using all "1" data.

Next, an embodiment relating to test 1 will be described.
In order to perform a column selector leak failure detection test, in a multi-mode, a program of a NOP instruction (a plurality of times), a flag data write instruction, and a flag data read instruction are loaded into the RAM 2 for leak measurement. Thereafter, reset is performed, and the MROM leak failure detection circuit is set to the column selector leak test mode by inputting a mode setting signal from the mode setting terminal of LINO.

With this setting, the control circuit 31 sets VREF
The set value transitions from normal VDD / 2 to 3 * VDD / 4. At the same time, PRECNT = "1" generated from the precharge control signal generation circuit 33, and the A01 generation circuit 3
4, A0 to Al = all “0”, B0x generated from the B0x generation circuit 35 = all “1”, C0
C0 to C7 generated from the D7 generation circuit 36 = “1”, D0 to D1 generated from the D01 generation circuit 37
= All are set to "1".

When each control signal becomes as described above, the precharge transistor 3a is turned on, the column selector transistor 3b is turned off, the cell selector transistor 3c is turned on, the ROM cell transistor 3d is turned on, and the disable transistor 3f is turned on. , COLOUT
To the VDD level, the VDD power supply, the precharge transistor 3a, the column selector transistor 3b, the cell selector transistor 3c, the ROM cell transistor 3f, the disable transistor 3g, and the D of the GND power supply.
A C path is formed.

Here, when COLOUT is precharged and becomes "1", the output PR of the sense amplifier circuit 3f is output.
OUT becomes "0", so that the output of the latch circuit 3g becomes "1", and the output of the R / S flip-flop 3i becomes "0" (state in which no flag is set).

When a leak failure occurs in the column selector transistor portion, the leaks of all the column selector transistors 3b are summed, the COLOUT level drops to 3 * VDD / 4 or less of the VREF potential, and the sense amplifier circuit 3f
Is inverted to “1”.

As a result, the output of the latch circuit 3g becomes "0", the output of the R / S flip-flop circuit 3i is inverted to "1", and the leak failure detection flag is set. When there is no leak failure in the column selector transistor portion, COLOUT level = VDD,
The output PROUT of the sense amplifier circuit 3f holds the state of "1".

During the execution of the NOP instruction of the CPU 7, the DC
A leak failure detection measurement (about luS) is performed.

During the write command execution period of the CPU 7, the output (leakage information) of the sense amplifier circuit 3f is
At the same time as writing to g, the flag output is determined by the R / S flip-flop 3i. 1 of the flag output circuit 4 of FIG.
The flag data indicating the presence / absence of the column selector leak is written into the 6-bit buffer register circuit 4a, and the flag data is transferred to the 16-bit shift register circuit 4b at the fall timing of WR.

Next, during the read command execution period of the CPU 7, the column selector leak presence / absence flag data in the 16-bit buffer shift register 4a is supplied to the monitor terminal PTOUT via the monitor / port circuit 5 and the column of bits 0 to 15 is read. By sequentially reading the selector leak presence / absence flag information, the off-leak defect detection test (test 1) is completed.

In the above test, when there is a leak failure in the MROM, data "1" is output to the monitor terminal PTOUT, and when there is no leak failure in the MROM, data "0" is output to the monitor terminal PTOUT. Output.

After reading bit 0 to bit 15, the 4-bit up counter 4c, the ALL "1" detection circuit 4d and the latch circuits PH1 / PH2 re-start 1 bit.
Since the data of the 6-bit buffer register circuit 4a can be transferred to the 16-bit shift register circuit 4b, it is possible to monitor the result of leak detection of the column selector a plurality of times.

FIG. 5 is a timing chart of the test 1 described above. Each signal displayed in the left column in the figure corresponds to each signal displayed in FIG. Test 1 is RAM program, reset mode setting, VREF after VREF change
F stabilization, leak detection result writing, and leak result monitoring are performed in this order.

The control signals at the time of the cell selector leak test of test 2 are: PRECNT = “1”, A0 to A1 = all “1”, B0 to Bx = all “0”, C0 to C7 = all “1”, D0 to D1 = All are set to “1” and test 1
As in the column selector leak test, the DC leak failure detection result is monitored from the monitor terminal PTOUT.

Each control signal at the time of the disable transistor test in the test 4 is represented by PRECNT = "1" and A0 to A
1 = all “1”, B0 to Bx = all “1”, C0 to C7
= All "1", D0-D1 = all "0", and the DC leak failure detection result is monitored from the monitor terminal PTOUT as in the test 1 column selector leak test.

At the time of the ROM cell leak test of test 3,
Before selecting an address in which all MROM data is "1" and setting the test 3 mode, it is necessary to write an address designation program in which all "1" s are written in the RAM 2. That is, PRECNT = "1", A0-Al = selection, B0-
Bx = selection, C0-C7 = all "0", D0, D1 = selection. Thus, if there is "0" in the read data, a ROM cell leak is detected. It is necessary to execute the test eight times in order to test the random address portion (all "1" data addresses) from C0 to C7.

If there is no "1" in the MROM data, an arbitrary one is used as the MROM data, and this is written in the ROM cell. When the leak failure is monitored, the write data is read out, and the MROM data is read out. The presence or absence of DC leak failure detection is determined by comparison with the inverted data. Other than the above, the test method is
This is the same method as 2, 4.

Here, in terms of the test time, fc = 20M
Hz, multi-mode setting time 1 uS + program loading time to RAM 10 us + various leak mode setting time 1 uS + VREF stabilization time 1 uS + DC leak failure measurement time 1 uS + data latch time 0.4 uS + monitor terminal read time 6.4 uS (0.4 uS * 16 times) =
About 20 uS is enough.

Even if all the leak tests were performed, test 1 = 20 uS, test 2 = 20 uS, test 3 = 1
60uS (20uS * 8 gates), test 4 = 20u
In S, the total test time is only 220 uS. Compared to the conventional fmin test time = 8200 ms (32 KHz), the total ROM leak test = 0.22 ms, which can significantly reduce the test time.

According to the present embodiment, the MROM mixed chip 100 is set to the test mode, and the precharge transistor 3a, the column selector transistor 3b, the cell selector transistor 3c, and the ROM cell transistor 3d are fixed in a predetermined state. When a leak is detected by a leak detection circuit provided in the circuit 3, this is output from the flag output circuit 4 to the outside.
It is possible to measure off-leak of various transistors in the MROM circuit 3 in a C-like manner, and it is possible to determine the presence or absence of a leak in 32 KHz or less in a short time without overlooking the failure. One monitor terminal PTO of port circuit 5
It can be determined by UT. Further, since the rejection of the MROM leak defective cell can be easily performed and the presence or absence of the defective product can be easily determined, it is possible to solve the problem of the market defect that low-frequency operation failure occurs frequently after the sample is shipped. .

[0041]

As described in detail above, the M of the present invention
According to the ROM leak failure detection circuit, the failure of the MROM in the MROM mixed chip can be detected easily and in a short time without being overlooked. Moreover, DC MRO
Since the M leak defect detection test can be performed, the fmin test becomes unnecessary, and the evaluation time can be significantly reduced, so that the chip cost can be reduced.

According to the MROM mixed chip of the present invention, M
The rejection of defective cells due to ROM leakage can be performed in a short time and easily, and the presence / absence of a defective product can be easily determined. it can. Further, it can be used as a reliability test of various transistors in the MROM, and the reliability of the chip can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an MROM mixed chip on which an MROM leak failure detection circuit of the present invention is mounted.

FIG. 2 is a block diagram showing a detailed example of the MROM circuit shown in FIG.

FIG. 3 is a block diagram illustrating a detailed example of a flag output circuit illustrated in FIG. 1;

FIG. 4 is a table showing the state of each control signal in each test in the chip of FIG. 1;

FIG. 5 is a timing chart showing an operation of test 1 in the chip of FIG.

6 is a circuit diagram showing a detailed example of a control circuit of the MROM circuit shown in FIG.

FIG. 7 is a circuit diagram showing a detailed example of a reference voltage generation circuit of the MROM circuit shown in FIG. 2;

FIG. 8 is a circuit diagram showing another detailed example of the reference voltage generation circuit of the MROM circuit shown in FIG. 2;

9 is a circuit diagram showing a detailed example of a precharge control signal generation circuit of the MROM circuit shown in FIG.

FIG. 10 is a circuit diagram showing a detailed example of an A01 generating circuit of the MROM circuit shown in FIG. 2;

11 is a circuit diagram showing a detailed example of a B0x generation circuit of the MROM circuit shown in FIG. 2;

FIG. 12 is a circuit diagram showing a detailed example of a C07 generating circuit of the MROM circuit shown in FIG. 2;

FIG. 13 is a circuit diagram showing a detailed example of a D01 generation circuit of the MROM circuit shown in FIG. 2;

FIG. 14 is a circuit diagram showing a detailed example of a sense amplifier of the MROM circuit shown in FIG. 2;

15 is a circuit diagram showing a detailed example of a 16-bit shift register circuit of the flag output circuit shown in FIG.

16 is a circuit diagram showing a detailed example of a 4-bit up counter and an ALL “1” detection circuit of the flag output circuit shown in FIG. 3;

FIG. 17 is a circuit diagram showing a detailed example of the mode setting circuit shown in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Port circuit 2 RAM 3 MROM circuit 4 Flag output circuit 5 Monitor / port circuit 6 System reset generation circuit 7 CPU 8 Mode setting circuit 9 Address area decode circuit 10 Oscillation / clock generation circuit 31 Control circuit 32 VREF generation circuit 33 Precharge control Signal generation circuit 34 A01 generation circuit 35 B0x generation circuit 36 C07 generation circuit 37 D01 generation circuit 51 selector circuit 52 output buffer 53 NOR circuit 100 MROM mixed chip 3a precharge transistor 3b column selector transistor 3c cell selector transistor 3d NAND-ROM cell transistor 3e Discharge transistor 3f Sense amplifier circuit 3g Latch circuit 3h Output circuit 3i RS flip-flop circuit 4a 16-bit battery F register circuit 4b 16-bit shift register circuit 4c 4-bit up counter 4d ALL "1" detection circuit PTOUT monitor terminal

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B003 AA05 AB02 AB06 AB08 AC07 AD02 AD05 AD07 AD08 AD09 AE04 5B018 GA03 HA31 JA22 KA02 MA35 NA05 PA03 QA13 5L106 AA07 AA15 AA16 DD08 DD12 GG05

Claims (5)

[Claims] 1. An MROM, a control unit for controlling a group of transistors constituting the MROM to a predetermined state corresponding to a type of a test, and a leak detection unit for detecting that a leak has occurred in a part of the transistor group And an output means for extracting a detection signal when the occurrence of the leak is detected, and an MROM leak failure detection circuit. 2. The MROM leak detection circuit according to claim 1, wherein said output means converts the detection signal into serial data and sequentially outputs the detection signal from one output terminal. 3. The transistor group includes a column selector transistor, a cell selector transistor, a ROM cell transistor, and a disable transistor. In each of three types of tests, leakage of the column selector transistor, the cell selector transistor, and the disable transistor is detected. Then, the leakage of the ROM cell transistor is detected by one type of test later. In the detection of the leakage of the ROM cell transistor, a plurality of leak failure detection tests are performed after selecting an address where all the ROM data is set to "1". 3. The MROM leak failure detection circuit according to claim 1, wherein: 4. The leak detecting means has a sense amplifier for detecting a potential of a precharge output line of the MROM, and a reference voltage of the sense amplifier is used when the MROM is used in a normal use mode and when an MROM leak failure occurs. 4. The MROM leak failure detection circuit according to claim 1, wherein the change is made when the device is used in a mode for detecting the MROM leak. 5. The MRO according to claim 1, wherein:
An MRO comprising an M leak defect detection circuit
M mixed chip.