JP2000352969A - Picture processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a picture processor, which is capable of compositing a main picture and auxiliary information without using an additional circuit especially provided for auxiliary information picture composition, by executing a picture compositing processing, in which auxiliary information recorded in an auxiliary information bank is superimposed on normal picture signals to be inputted and outputting the composited picture signals. SOLUTION: The picture processor processes a picture 201 having 240 lines in which each line is made up with 704 pixels, for example. Auxiliary information is displayed in a region 202 having a longitudinal direction from an OSD Start line to an (OSD Start +80) line and a full lateral direction (Hereafter, the region indicated by region 202 is called as an auxiliary information display region). Numbers 1 to 56, 320 are assigned to the pixels in the auxiliary information bank in the memory of the picture processing device, picture compositing of a main picture and auxiliary information is conducted without using an additional circuit especially provided for auxiliary information picture compositing such as a character generator.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for synthesizing auxiliary information such as characters and graphics with an image to be displayed or recorded (hereinafter referred to as a main image).

[0002]

2. Description of the Related Art In general, a dedicated electronic system for displaying and recording images on a television, a video tape recorder, an image communication terminal and the like, and displaying and recording images on a computer and the like are only one feature of the system. In an electronic system, etc., in order to display and record auxiliary information such as characters and figures such as tape counter, time, date, etc. on the main image together with the main image, an addition specialized for auxiliary information image synthesis such as a character generator The circuit performs a process of combining the auxiliary information with the main image.

FIG. 11 shows an example. FIG. 11 is a block diagram of an image processing apparatus for displaying auxiliary information on an image display unit using a conventional character generator. The auxiliary information is displayed on the image display unit together with a main image taken from a lens using the character generator. FIG.

The main image captured by the lens 101 is subjected to image processing such as synchronous separation and color signal processing in an image processing unit 102. The processed image signal is input to the character generator 103. The character generator 103 selects, under the control of the microcontroller 105, one to be used as auxiliary information from characters, graphics, and the like stored in the ROM 104 inside the character generator 103, and determines the color, background, display position, and the like of the auxiliary information. Then, the auxiliary information is synthesized with the main image. The image signal processed by the character generator 103 is transmitted to the image display unit 10
6 and displayed.

[0005]

However, when the auxiliary information is a simple character or graphic, using an additional circuit such as a character generator specialized for synthesizing the auxiliary information image makes it possible to compare the function with the function realized by the apparatus. Therefore, the device becomes expensive and large.

The present invention has been devised to solve the above-mentioned problems. The present invention does not use an additional circuit such as a character generator specialized in synthesizing auxiliary information images, and uses a main image and an auxiliary information image. It is an object of the present invention to provide an image processing device capable of combining images.

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides an electronic system in which an image processing unit and a memory are connected to each other, wherein auxiliary information such as characters and graphics is stored as an image in the memory. An image processing unit that has an auxiliary information bank, performs an image synthesis process of superimposing auxiliary information recorded in the auxiliary information bank on an input normal image signal, and outputs a synthesized image signal. is there.

According to the present invention, the main image and the auxiliary information can be synthesized without using an additional circuit such as a character generator specialized for synthesizing the auxiliary information image.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an electronic system in which an image processing unit and a memory are combined;
An image synthesizing process in which the memory has an auxiliary information bank for storing auxiliary information such as characters and figures as an image, and the image processing unit superimposes auxiliary information recorded in the auxiliary information bank on a normal image signal to be input; And outputs the synthesized image signal.

According to a second aspect of the present invention, only the auxiliary information to be synthesized by the image processing unit is provided when the memory has a plurality of the auxiliary information banks and the image processing unit selects an arbitrary auxiliary information bank. Was changed.

According to a third aspect of the present invention, a first device that needs access to the memory is coupled to the memory via an arbiter that arbitrates a plurality of accesses to the memory, and the first device allows a plurality of devices to access By rewriting the auxiliary information in the auxiliary information bank, a large amount of various types of auxiliary information can be combined with the main image with a small amount of memory.

According to a fourth aspect of the present invention, the image of the auxiliary information is recorded in the auxiliary information bank as a reduced image of the image to be actually synthesized, and when the image is synthesized, the reduced image stored in the auxiliary information bank is stored. Is expanded by the image processing unit, thereby reducing the amount of memory used for the auxiliary information bank.

According to a fifth aspect of the present invention, the amount of memory used for the auxiliary information bank is reduced by expressing the image of the auxiliary information in a color code and recording the image in the auxiliary information bank.

According to the above arrangement, the main image and the auxiliary information can be image-combined without using an additional circuit such as a character generator dedicated to the auxiliary information image synthesis.

(Embodiment 1) FIG. 1 is an explanatory diagram of an image processed by an image processing apparatus according to Embodiment 1 of the present invention. In FIG. 1, it is assumed that the image processing apparatus processes an image 201 having, for example, 240 lines constituting one line with 704 pixels. The vertical direction of the auxiliary information from the OSD_Start line is (OSD_Start +
80) Up to the line, the area 202 where the screen is full in the horizontal direction
Will be displayed. Hereinafter, the area indicated by 202 is referred to as an auxiliary information display area. Pixels in the auxiliary information display area are
Numbered from 1 to 56320 as shown in FIG. Pixels in the image 201 are represented in a YUV color space, and Y,
Each signal of U and V is represented by 8 bits.

FIG. 2 is a functional block diagram of the image processing apparatus according to the first embodiment of the present invention, and FIG. 3 is a view showing the same memory map. The portion indicated by 301 is an image processing unit. In the image processing unit, Y data Y_I is used as a main image signal.
[7: 0], U data U_I [7: 0], V data V_
I [7: 0], horizontal synchronization signal H_IN, vertical synchronization signal V
_IN and the dot clock D_CLK_IN are input. The processed image signal obtained by performing the image processing of the main image in the image processing unit 301 is Y data Y_O [7: 0], U data U_
O [7: 0], V data V_O [7: 0], horizontal synchronization signal H_OUT, vertical synchronization signal V_OUT, and dot clock D_CLK_O.

The portion indicated by 303 is a memory. The memory 303 is connected to the image processing unit 301 and is accessible from the image processing unit 301. An auxiliary information bank 401 that records auxiliary information as an image exists in an arbitrary memory space in the memory 303.

FIG. 3 shows a memory map of the memory 303. It is assumed that the auxiliary information bank 401 starts from the memory address OSD_Adr. The auxiliary information bank 401 stores Y, U, and V data of the auxiliary information image for each pixel from pixel 1 to pixel 56320 in order. However,
Any one of the (Y, U, V) sets in the auxiliary information image represents transparency, and is reserved as displaying the pixels of the main image without displaying the auxiliary information. In this case, the auxiliary information bank 401 occupies a memory area of 165 kbytes.

In FIG. 2, a portion indicated by 304 is an internal register. The operation of the image processing unit is determined by the value of the register in the internal register 304. The controller 302 controls the image processing unit 301 by accessing the internal register 304 and updating the value appropriately. The internal register 304 includes a register OSD_EN 309 for controlling display of auxiliary information and a register OSD for holding a value of OSD_Start which is a head line of the auxiliary information area.
_Start 308 exists. When the image processing unit combines the auxiliary information with the main image, the controller 302 sets the first line of the auxiliary information area in the register OSD_Start 308, and activates the register OSD_EN309.

The portion indicated by reference numeral 306 is a V counter. The V counter is based on V_IN and D_CLK_IN.
Image signals Y_I [7: 0], U_I [7: 0], V_I
The vertical position in the image 201 of FIG. 1 where the image data represented by [7: 0] is displayed is determined.

The portion indicated by 307 is an H counter. The H counter uses H_IN and D_CLK_IN
Image signals Y_I [7: 0], U_I [7: 0], V_I
The horizontal position in the image 201 of FIG. 1 where the image data represented by [7: 0] is displayed is determined.

The part indicated by 310 is a control unit. When the register OSD_EN 309 is active, the value V_value of the V counter 306 and the register OSD
_Start 308 value OSD_Start is OSD_
Start ≦ V_value ≦ (OSD_Stat
rt + 80), the output O of the control unit 310
Activate SD_Valid. The control unit 31
0 is an address signal for calculating the pixel number of the auxiliary information display area from the values of the OSD_Start, the V counter 306, and the H counter 307, and reading the Y data of the pixel number stored in the auxiliary information bank in the memory 303. Is generated, and reading of the Y data is executed. The Y data read from the memory 303 is stored in a Y buffer 311.
Is written to. After the Y data is written to the Y buffer 311, the U data and the V data are written to the U buffer 312 and the V buffer 313 in the same order as for the Y data.

The transparency judging unit 317 includes a Y buffer 311, a U buffer
If the set of (Y, U, V) of the image data of the auxiliary information written in the buffer 312 and the V buffer 313 indicates transparency, the output OSD_Trans is activated.

The Y output switching unit 314 operates as OSD_Valid.
Is active and OSD_Trans is not active, the Y data written in the Y buffer 311 is output to the image processing unit output Y_O [7: 0]. Otherwise, the image processing unit input Y_I [7: 0] is output. ] To Y
_O [7: 0]. The U output switching unit 315 and the V output switching unit 316 are also OSD_
U_O according to the value of Valid and OSD_Trans
The data to be output to [7: 0] or V_O [7: 0] is switched.

By performing the above operation each time V_IN and H_IN change, the auxiliary information can be synthesized with the main image without using an additional circuit specialized for synthesizing the auxiliary information image such as a character generator. Is possible.

(Embodiment 2) FIG. 4 is a functional block diagram of an image processing apparatus according to Embodiment 2 of the present invention, and FIG. 5 is a diagram showing the same memory map. It is assumed that the memory 503 has 256 auxiliary information banks described in the first embodiment as an example. Different auxiliary information images are stored in each auxiliary information bank. FIG. 5 shows a memory map of the memory 503. Each auxiliary information bank is continuously arranged in the memory space without any gap.
Numbered up to 56. The auxiliary information bank 1 indicated by 601 starts from the address OSD_Adr1, and
Occupies a 5 kbyte memory area. The auxiliary information bank 2 indicated by 602 starts from the address next to the memory address where the V data of the pixel 56320 of the auxiliary information bank 1 indicated by 601 is stored. This address is referred to as OSD_Adr2. Similarly, a start address is determined for each auxiliary information bank up to the auxiliary information bank 256 indicated by 603.

In the internal register 504, there is provided a register OSD_Bank 318 indicating the number of the auxiliary information bank in which the auxiliary information image to be synthesized with the main image is stored. When the image processing unit 501 combines the auxiliary information with the main image, the controller 302 uses the register OSD_EN 309 and the register OSD_S described in the first embodiment.
In addition to the setting of the start 308, the register OSD_Ban
The auxiliary information bank number is set in k318.

The control unit 510 activates the output OSD_Valid of the control unit 510 by the method described in the first embodiment, and sets the registers OSD_Start 308,
The pixel number of the auxiliary information display area is calculated from the values of the V counter 306 and the H counter 307, and the Y data of the pixel number stored in the auxiliary information bank of the number indicated by the register OSD_Bank 318 in the memory 503 is calculated. An address signal or the like for reading is generated, and the reading of the Y data is executed. The Y data read from the memory 503 is written to the Y buffer 311. After the Y data is written to the Y buffer 311, the U data,
U buffer 31 in the order of V data in the same procedure as Y data.
2. Write to the V buffer 313. As described above, a plurality of pieces of auxiliary information can be switched and combined with the main image.

(Embodiment 3) FIG. 6 is a functional block diagram of an image processing apparatus according to Embodiment 3 of the present invention.

The portion indicated by 700 is a CPU. The CPU 700 accesses the memory 503 via the bus DB, and uses the memory 503 as main storage. The bus DB is also connected to an internal register of the image processing unit 501, and the CPU 700 controls the image processing unit 501. The image processing unit 501 accesses the auxiliary information bank in the memory 503 via the bus DB_VIDEO.

The part indicated by 701 is an arbiter. The arbiter 701 includes a CPU 700 and an image processing unit 501.
CP to avoid simultaneous access to memory 503
The arbitration of memory access between the U700 and the image processing unit 501 is performed autonomously.

If the image processing unit 501 does not perform image synthesis for superimposing auxiliary information on the main image, or processes a main image signal other than the auxiliary information display area even when performing image synthesis for superimposing auxiliary information, The image processing unit 501 does not access the memory 503. CPU
Reference numeral 700 denotes an image processing unit 501 which appropriately creates an auxiliary information image to be used in the future, and the image processing unit 501 accesses the auxiliary information bank in which an auxiliary information image which is not used during the idle time of memory access is stored as needed. Write the auxiliary information image and update the contents.

As described above, the image processing unit 501 can handle more auxiliary information than the amount of memory as a physical bank, and the CPU 700 updates the auxiliary information image in the auxiliary information bank as needed, so that the auxiliary information bank is stored in the memory 503. Can reduce the amount of memory occupied.

(Embodiment 4) FIG. 7 is an explanatory diagram of an image processed by an image processing apparatus according to Embodiment 4 of the present invention. If the auxiliary information is a simple character or graphic, the image 80
Since it is not necessary to display the image of the auxiliary information at the resolution of one pixel unit, for example, one pixel of the auxiliary information
01 is enlarged twice in the vertical direction and twice in the horizontal direction.

FIG. 8 is a functional block diagram of the image processing apparatus according to the fourth embodiment of the present invention. The control unit 910 outputs the output OSD_V of the control unit 910 by the method described in the first embodiment.
Activate alid and register OSD
_Start 308, V counter 306, H counter 3
07, the pixel number of the auxiliary information display area is calculated, and the register OSD_Bank31 existing in the memory 503 is calculated.
An address signal or the like for reading the Y data of the pixel number stored in the auxiliary information bank of the number indicated by No. 8 is generated, and the reading of the Y data is executed.

The Y data read from the memory 503 is written to the Y buffer 311. After the Y data is written to the Y buffer 311, the U data and the V data are sequentially written to the U buffer 312 and the V buffer 313 in the same procedure as the Y data. However, when performing image synthesis of a pixel having the same pixel number as an adjacent pixel on the same line in the auxiliary information display area, access to the auxiliary information bank in the memory 503 is not performed. In this case, since the auxiliary information bank in the memory 503 only needs to prepare the Y, U, and V data of the pixels 1 to 14080, the memory amount occupied by one auxiliary information bank is 42240 by.
te. As described above, the amount of memory used for the auxiliary information bank can be reduced.

(Embodiment 5) An image processed by an image processing apparatus having means according to Embodiment 5 of the present invention is shown in FIG. When the number of colors used by the auxiliary information image is not large, it is not necessary to specify detailed colors for the auxiliary information. Therefore, the color of the auxiliary information is represented by a 4-bit color code as shown in Table 1 as an example. One of 16 colors that can be represented by a color code represents transparency.

[0038]

[Table 1]

FIG. 9 is a functional block diagram of an image processing apparatus according to the fifth embodiment of the present invention, and FIG. 10 is a view showing the same memory map. FIG. 10 shows a memory map of the memory represented by reference numeral 1003. Since one pixel is represented by a 4-bit color code, image data of two pixels of the auxiliary information image can be stored in one memory address. Therefore, one auxiliary information bank only occupies a memory amount of 7040 bytes.

The portion indicated by reference numeral 1010 is a control section. The register OSD_EN 309 is active and the value V_value of the V counter 306 is
_Start 308 value OSD_Start is OSD_
Start ≦ V_value ≦ (OSD_Stat
(rt + 80), the output OSD_Valid of the control unit 1010 becomes active. Control unit 1
010 is an address signal for calculating the pixel number of the auxiliary information display area from the values of the OSD_Start, the V counter 306, and the H counter 307, and reading the auxiliary information data of the pixel number stored in the auxiliary information bank in the memory 1003. And the like, and reads the auxiliary information data. The auxiliary information data read from the memory 1003 is written to the buffer 1013 by selecting either pixel information from the value of the H counter 307.

Y output switching section 1014, U output switching section 10
15. If the OSD_Valid is active and the pixel information is not transparent, the V output switching unit 1016 converts the Y data, U data, and V data corresponding to (Table 1) into Y_O.
[7: 0], U_O [7: 0], V_O [7: 0]. Otherwise, Y_I [7: 0], U_I
[7: 0], V_I [7: 0] is converted to Y_O [7: 0], U
_O [7: 0] and V_O [7: 0].

As described above, the amount of memory required for the auxiliary information bank can be reduced. Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications can be made without departing from the technical scope of the present invention. .

[0043]

According to the image processing apparatus of the first embodiment,
By providing the auxiliary information bank in the memory, the image of the main image and the auxiliary information can be synthesized without using an additional circuit such as a character generator specialized for synthesizing the auxiliary information image.

According to the image processing apparatus of the second embodiment, a plurality of auxiliary information banks are provided in the memory, and the image processing section selects an arbitrary auxiliary information bank, thereby switching the plurality of auxiliary information to the main image. It becomes possible to synthesize.

According to the image processing apparatus of the third embodiment, the number of auxiliary information banks in the memory is written by writing auxiliary information to be used by the first apparatus in the auxiliary information bank not accessed by the image processing unit. It is possible to switch more auxiliary information.

According to the image processing apparatus of the fourth embodiment, a reduced image of the auxiliary information is recorded in the auxiliary information bank, and is expanded when the image is synthesized by the image processing apparatus. Can be reduced. Further, since the number of times the image processing unit accesses the memory can be reduced, the operation speed of the entire image processing apparatus is improved.

According to the image processing apparatus of the fifth embodiment, the image of the auxiliary information in the auxiliary information bank is recorded by a 4-bit color code, thereby reducing the amount of memory used for the auxiliary information bank. Have. Further, since the number of times the image processing unit accesses the memory can be reduced, the operation speed of the entire image processing apparatus is improved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of an image processed by an image processing device according to a first embodiment of the present invention.

FIG. 2 is a functional block diagram of the image processing apparatus according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a memory map according to the first embodiment of the present invention;

FIG. 4 is a functional block diagram of an image processing apparatus according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a memory map according to the second embodiment of the present invention;

FIG. 6 is a functional block diagram of an image processing apparatus according to a third embodiment of the present invention.

FIG. 7 is an explanatory diagram of an image processed by an image processing device according to a fourth embodiment of the present invention.

FIG. 8 is a functional block diagram of an image processing apparatus according to a fourth embodiment of the present invention.

FIG. 9 is a functional block diagram of an image processing apparatus according to a fifth embodiment of the present invention.

FIG. 10 is a diagram showing a memory map according to a fifth embodiment of the present invention.

FIG. 11 is a block diagram of an image processing apparatus that displays auxiliary information on an image display unit using a conventional character generator.

[Explanation of symbols]

 101 lens 102 image processing unit 103 character generator 104 ROM 105 microcontroller 106 image processing unit 202 auxiliary information display area 301 image processing unit 303 memory 310 control unit 401 auxiliary information bank 501 image processing unit 503 memory 510 control unit 700 CPU 910 control unit 1001 Image processing unit 1003 Memory 1010 Control unit 1101 Auxiliary information bank 1 1102 Auxiliary information bank 2 1103 Auxiliary information bank 256

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 5/66 H04N 9/74 Z 5C076 9/74 G06F 15/66 450 5C082 F term (Reference) 5B057 BA02 CA01 CA08 CA12 CA16 CB01 CB08 CB12 CB16 CB19 CC01 CE08 CE17 5C023 AA18 BA15 CA01 CA05 DA04 5C025 BA27 BA28 CA09 5C058 BA24 BA35 BB11 5C066 AA03 AA06 AA11 CA01 CA23 ED04 GA02 GA05 GA13 GA14 AGA12 AGA12 KA02 KBA12A BA04 BB03 BB06 CA01 5C082 AA01 AA02 BA02 BA12 BA27 BB25 BB28 CA33 CA34 CA56 DA61 MM07

Claims (5)

[Claims] 1. An electronic system in which an image processing unit and a memory are combined, the memory having an auxiliary information bank for storing auxiliary information such as characters and graphics as an image in the memory, wherein the image processing unit is input. An image processing apparatus, comprising: performing image synthesis processing for superimposing auxiliary information recorded in the auxiliary information bank on a normal image signal; and outputting a synthesized image signal. 2. The image processing apparatus according to claim 1, wherein said memory includes a plurality of said auxiliary information banks, and said image processing section switches an auxiliary information bank to switch only auxiliary information to be synthesized by said image processing section. The image processing device according to claim 1. 3. A first device requiring access to said memory is coupled to said memory via an arbiter for arbitrating multiple accesses to said memory, said first device supporting a plurality of said auxiliary information banks. By rewriting information,
3. The image processing apparatus according to claim 2, wherein a large amount of various types of auxiliary information can be combined with the main image with a small memory amount. 4. An image of auxiliary information is recorded in the auxiliary information bank as a reduced image of an image to be actually synthesized, and when the images are combined, the reduced image stored in the auxiliary information bank is processed by the image processing unit. 2. The image processing apparatus according to claim 1, wherein the amount of memory used for the auxiliary information bank is reduced by enlarging. 5. The image processing apparatus according to claim 1, wherein an image of the auxiliary information is represented by a color code and recorded in the auxiliary information bank, thereby reducing a memory amount used for the auxiliary information bank. Image processing device.