JP2000349624A - Clock generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize the varied variables of phases of clocks which are distributed in a clock generator when the switching is carried out between an operating system and a standby system and to prevent a main signal error that occurs in the clock generator by setting the control voltage of a voltage control oscillator of a PLL circuit functioning as the standby system at a prescribed level. SOLUTION: A selection circuit is added to each of PLL circuits of a pair of clock packages and the control voltage of a voltage control oscillator of the PLL circuit functioning as a standby system is set at a prescribed level. This clock generator includes a clock supply device 1, a pair of clock packages 2a and 2b, selection circuits 16a and 16b, clock input terminals 17a and 17b and clock output terminals 18a and 18b. The terminals 17a, 17b, 18a and 18b are crossed and connected to each other between the packages 2a and 2b. The control signals 15a and 15b of the clock generator control the packages 2a and 2b to set them directly opposite to the operating and standby systems respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock generator,
The present invention relates to a clock generation device used for a communication device or the like which has a redundant configuration and generates stable clock pulses.

[0002]

2. Description of the Related Art In digital communication and the like, a clock pulse is used as an operation reference of all circuits, and this clock pulse is generated by a clock generator.

[0003] In current communication devices, it is common to make the main circuit portion in the device redundant in order to increase the reliability of the device or system. The same applies to the clock generator (or clock package). For example, as disclosed in Japanese Patent Application Laid-Open No. 1-309540, a redundant system is configured in a clock generator in the device, an active system and a standby system are provided, and when a failure occurs in the active system, the system is immediately switched to the standby system. And maintain communication continuity. In other words, the reliability of the clock system inside the device is improved.

FIG. 4 is a block diagram showing an example of such a conventional clock generator having a redundant configuration. 4 has a pair of clock packages 2a and 2b connected to a common clock supply device 1.
One clock package, for example, 2a, includes an external clock switching unit 4a, a conversion unit 5a, a phase comparison unit 6a, a loop filter 7a, a voltage controlled oscillator 8a, a frequency divider 9a, a selection circuit 10a, and an internal clock generation unit 11a. . Similarly, the other clock package 2b has the same configuration and includes components 4b to 11b. The external clock switching units 4a, 4b of these clock packages 2a, 2b
b, a clock is input as a reference clock from the clock supply device 1 via the external clock input terminals 3a and 3b, respectively. In addition, these clock packages 2a, 2
clock generator 11 in the device arranged at the output end of b
a, 11b, the clock distribution terminal 12 in the device, respectively.
An output clock is supplied to each unit in the apparatus via a and 12b.

Further, the clock packages 2a and 2b are provided with clock input terminals 13a and 13b and clock output terminals 14a and 14b, respectively, and are cross-connected to each other. In other words, the clock input terminal 13a and the clock output terminal 14b are connected, and the clock input terminal 13b
And the clock output terminal 14a. Also,
Each of the clock packages 2a and 2b has a control signal 15
a and 15b are input.

The operation will be described. The external clock switching units 4a and 4b pass the external clock from the clock supply device 1 through the external clock input terminals 3a and 3b to the clock packages 2a and 2b by the control signals 15a and 15b, or make the external clock open ( Switch). The conversion units 5a and 5b are connected to the external clock switching unit 4
The external clock switched at a and 4b is converted into a clock of a predetermined level and frequency. Phase comparators 6a, 6
b is the clock from the converters 5a, 5b and the frequency divider 9a,
The phase comparison with the clock from 9b is performed. The loop filters 7a and 7b remove unnecessary high frequency components from the phase comparison results compared by the phase comparison units 6a and 6b, and generate DC level control signals based on the phase comparison results. The voltage controlled oscillators (VCO) 8a, 8b
a, output an output frequency corresponding to the DC control signal from 7b. The frequency dividers 9a and 9b divide the frequency by an arbitrary frequency division ratio as needed so that the output frequency from the VCOs 8a and 8b matches the frequency of the reference clock from the converters 5a and 5b. The selection circuits 10a and 10b output the control signals 15a and 15
According to b, either the output clock from the VCO 8a, 8b or the clock from the internal clock generators 11b, 11a in the other clock packages 2b, 2a is selected. The in-device clock generators 11a and 11b generate a clock having a required frequency in the device based on the clocks from the selection circuits 10a and 10b and output the generated clock to the in-device clock distribution terminals 12a and 12b.

The in-device clock generators 11a and 11b
An oscillator having a frequency stability higher than that of the VCOs 8a and 8b having a normal holdover function is mounted, and a stable clock is distributed to each unit in the apparatus. The internal clock generators 11a and 11b are configured to be able to maintain a certain frequency for a short time even if the input of the external clock from the clock supply device 1 is interrupted due to a failure or the like. .

Next, a redundant configuration of the clock packages 2a and 2b will be described. Clock package 2a, 2
b is a redundant configuration, in which one (for example, 2a) is active and the other (for example, 2b) is standby (or non-active). The control signals 15a and 15b have the opposite relationship to each other so as to indicate the state of the active / standby system of the clock packages 2a and 2b. For example, the clock package 2a is an active system, and the clock package 2
The case where b is a standby system will be described below.

Control signal 15a for clock package 2a
Sets the external clock switching unit 4a and the selection circuit 10a to the operating system state. In this case, the external clock switching unit 4 selects the external clock from the clock supply device 1, and the selection circuit 10a selects the output clock from the VCO 8a. On the other hand, the control signal 1 of the clock package 2b
5b is the external clock switching unit 4b and the selection circuit 10
Let b be the standby system state. Therefore, clock package 2
The external clock switching unit 4b of b is in an open state, and the selection circuit 10b selects the output clock from the internal clock generation unit 11a of the clock package 2a via the clock output terminal 14a and the clock input terminal 13b.

The operation of the above-described conventional clock generator of FIG. 4 is summarized as follows. The clock package 2a (or 2b), which is the operating system,
Clock package 2b (or 2a) operating in synchronization with (following) an external clock from
Operate in synchronization with (following) the clock output of the clock package 2a (or 2b). In other words, the clock packages 2a and 2b do not operate independently in the device, but the operating clock package 2a operates as a master and the standby clock package 2b operates as a slave. As described above, the redundant configuration of the clock packages 2a and 2b has a master-slave relationship because the external clock from the clock supply device 1 is disconnected due to a failure or the like, and the internal clock generation units 11a and 11b 11b, the clock package 2 remains
The relationship between a and 2b becomes a master-slave relationship, and the in-device clock distribution terminals 12a, 1 distributed to various parts in the device.
This is to make the output phase relationship of 2b coincide as much as possible.

As a related prior art, Japanese Patent Laid-Open No.
No. 4,204,990 entitled "Clock Generation Circuit with Redundant Configuration" and Japanese Unexamined Patent Publication No. 4-267652 "Clock Phase Synchronization System".

[0012]

In the prior art described above, since the external clock switching unit of the standby clock package is in the open state, the phase including the phase comparison unit, the loop filter, the VCO, and the frequency divider is determined. Synchronous loop (PL
L) The circuit operates without a reference clock. Therefore, the control voltage of the VCO gradually shifts. In this state, if switching between the operating system and the standby system occurs between the clock packages, a large fluctuation occurs in the control voltage of the VCO, and it takes time until the pull-in of the frequency is completed and the PLL circuit is stabilized. The main signal error.

In recent years, clock system performance has been standardized by international standards such as ITU-T.
For example, the amount of phase fluctuation of the clock in the device at the time of switching between the active system and the standby system of the clock package is also specified. Therefore, a clock generator having a performance satisfying these standards is required.

An object of the present invention is to minimize the amount of phase fluctuation of the internal clock distributed to the inside of the communication device when switching between the active system and the standby system of the clock package constituting the redundant system inside the communication device, An object of the present invention is to provide a clock generation device that prevents occurrence of a main signal error inside the device and guarantees a higher performance phase fluctuation characteristic when switching an operating system clock package.

[0015]

Means for Solving the Problems In order to solve the above-mentioned problems, the clock generator according to the present invention employs the following characteristic configuration.

(1) It has a pair of clock packages in a redundant configuration for receiving an external clock from a reference clock source,
The pair of clock packages each include a phase-locked loop circuit, and operate based on a control signal, wherein one of the pair of clock packages operates as an operating system and the other as a standby system. A clock generator for setting a control voltage of a voltage-controlled oscillator of the phase-locked loop circuit operating as the standby system to a predetermined value.

(2) The clock generator according to (1), wherein the control voltage of the standby voltage controlled oscillator is supplied from the operating system phase locked loop circuit.

(3) The clock generator according to (1), wherein the control voltage of the standby voltage controlled oscillator is set to a fixed value at which the voltage controlled oscillator oscillates at a substantially center frequency.

(4) The pair of clock packages includes:
The clock generator according to the above (1), further comprising an internal clock generator for outputting a high-precision oscillation frequency to an output side of the phase locked loop circuit.

(5) The clock generator according to (4), wherein the internal clock generator has a phase locked loop including a digital signal processor and has a holdover function.

[0021]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a preferred embodiment of a clock generator according to the present invention; FIG.

FIG. 1 is a block diagram of a first embodiment of a clock generator according to the present invention. Since this clock generator uses many components corresponding to the conventional clock generator of FIG. 4, the same reference numerals are used for the corresponding components for convenience.

The clock generator of FIG. 1 has a clock supply device 1 and a pair of clock packages 2a and 2b. Each of the clock packages 2a and 2b includes external clock input terminals 3a and 3b, and clock input terminals 13a and 13b.
b, clock output terminals 14a and 14b, and these clock input terminals 13a and 13b and the clock output terminal 14
a and 14b are similar to the prior art of FIG. 4 in that they are cross-connected to each other between the clock packages 2a and 2b.

Each of the clock packages 2a, 2b includes an external clock switching unit 4a, 4b, a conversion unit 5a, 5b, a phase comparison unit 6a, 6b, a selection circuit 16a, 16b, a loop filter 7a, 7b, a VCO 8a, 8b, a frequency division. Part 9a,
9b, selection circuits 10a and 10b, and in-device clock generators 11a and 11b.

As is clear from comparison with the block diagram of FIG. 4, the first embodiment of the clock generator of the present invention shown in FIG.
7a, 17b and clock output terminals 18a, 18b, and these terminals 17a-17b, 18a-18b are cross-connected between the clock packages 2a, 2b. That is, the clock input terminals 17a and 17b are connected to the input sides of the selection circuits 16a and 16b, respectively, and the clock output terminals 18a and 18b are connected to the output sides of the phase comparison units 6a and 6b, respectively. Then, the clock input terminal 17a
Is connected to the clock output terminal 18b, and the clock input terminal 17b is connected to the clock output terminal 18a. In other words, two cross connection portions are formed between the clock packages 2a and 2b.

In the clock generator of FIG. 1, the phase comparators 6a and 6b, the selectors 16a and 16b, the loop filters 7a and 7b, the VCOs 8a and 8b, and the frequency dividers 9a and 9 are used.
b is the same as that of the clock generator shown in FIG. Here, the selection circuits 16a and 16b
Are PLLs of the clock packages 2b and 2a of the other party, respectively.
The phase comparison results from the phase comparison units 6b and 6a constituting the circuit are selected by the control signals 15a and 15b. For example,
The control signals 15a and 15a are controlled so that the clock package 2a operates as the active system and the clock package 2b operates as the standby system.
Explaining the case where b is selected, the external clock of the clock supply device 1 is input from the external clock input terminal 3a of the clock package 2a to the PLL circuit via the external clock switching unit 4a and the conversion unit 5a. At this time, the selection circuit 16a inputs the phase comparison output of the phase comparison unit 6a to the VCO 8a via the loop filter 7a. Therefore, the VCO 8a inputs an output synchronized with the external clock and determined by the frequency division ratio of the frequency divider 9a to the internal clock generator 11a via the selection circuit 10a.

In this state, the external clock switching section 4b of the clock package 2b is in an open state, and blocks input of an external clock to the PLL circuit of the clock package 2b via the external clock input terminal 3b. However, the selection circuit 16b of the PLL circuit selects the comparison output of the phase comparison unit 6a of the clock package 2a and inputs the comparison output to the VCO 8b via the loop filter 7b. Therefore, the PLL circuit of the clock package 2b also operates following the PLL circuit of the clock package 2a. However,
The selection circuit 10b does not select the output of the PLL circuit,
The output of the internal clock generator 11a is selected via the clock output terminal 14a and the clock input terminal 13b.

Next, FIG. 2 is a detailed block diagram of the internal clock generator 11a (11b) of the clock generator of FIG.
Shown in The internal clock generator 11 includes a clock input terminal 19, a phase comparator 20, a converter 21, a digital low-pass filter 22, a digital signal processor 23,
Conversion unit 24, analog low-pass filter unit 25, VCO
26, a frequency divider 27, and a clock output terminal 28.

The clock selected by the selection circuit 10a (10b) in FIG. 1 is input to the clock input terminal 19 as a reference. The phase comparison unit 20 has a clock input terminal 1
9 is compared with the clock from the frequency divider 27. The converter 21 samples the phase comparison result from the phase comparator 20 and converts it into a digital signal. Digital low-pass filter (D-LPF) 22
Removes unnecessary high-frequency components such as unnecessary jitter components from the output signal from the converter 21 and outputs serial data. After performing various controls on the serial data from the D-LPF 22, the digital signal processing unit 23 sends out the serial data. The converter 24 converts the serial data from the digital signal processor 23 into an analog signal. Analog low-pass filter (A-LPF) 2
5 removes unnecessary high frequency components from the signal from the converter 24 and generates a DC level control signal based on the phase comparison result. The VCO 26 outputs an output frequency corresponding to the DC control signal from the A-LPF 25, and the VCO 8
Higher frequency stability. The frequency divider 27 controls the VCO 2 as necessary so that the output frequency from the VCO 26 matches the frequency of the reference clock from the clock input terminal 19.
6 is divided by the output frequency.

Between the clock packages 2a and 2b,
As described above, the output clock of the phase comparator 6 of the PLL circuit and the output clock of the VCO 8 are cross-connected at two points. The output clock from another clock package 2a or 2b is selected by the control signals 15a and 15b.

Next, the operation of the clock generator shown in FIGS. 1 and 2 will be described. The clock packages 2a and 2b of this clock generation device have a redundant configuration, in which one is an active system and the other is a standby system. Therefore, the control signals 15a and 15b are output from the clock packages 2a and 2b.
b is controlled to be exactly opposite to the active / standby system. Hereinafter, a case where the clock package 2a is the active system and the clock package 2b is the standby system will be described.

In this case, the control signal 15a controls the external clock switching unit 4a and the selection circuits 16a and 10a as active systems. That is, the external clock switching unit 4a
Selects an external clock from the clock supply device 1 and inputs it from the external clock input terminal 3a to the converter 5a. The selection circuit 16a inputs the output clock (phase comparison output) of the phase comparison unit 6a to the loop filter 7a. Further, the selection circuit 10a selects an output clock from the VCO 8a and inputs it to one input terminal of the phase comparison unit 20 via the in-device clock generation unit 11a, specifically, the clock input terminal 19 of FIG. Operate.

On the other hand, the control signal 15b of the clock package 2b controls the clock package 2b to a standby system, that is, a non-operating system. That is, the external clock switching unit 4
b is in an open (off) state. The selection circuit 16b selects a phase comparison output of the phase comparison unit 6a of the PLL circuit of the clock package 2a. The selection circuit 10b operates to select an output clock from the in-device clock generation unit 11a of the clock package 2a. In other words, the clock package 2a is operating and the clock package 2
If b is a standby system, clock package 2 that is an active system
Although a operates in synchronization (following) with the external clock from the clock supply device 1, the clock package 2b serving as the standby system operates in synchronization (following) with the clock output of the clock package 2a. Clock package 2
The reason why a and 2b have the above relationship will be described below.

As shown in FIG. 2, various digital signal processing can be performed by the digital signal processing unit 23 by converting the phase comparison result of the phase comparison unit 20 into digital data inside the internal clock generation units 11a and 11b. become. For example, if the digital signal processing unit 23 has a holdover function, the input of the external clock from the clock supply device 1 is interrupted due to a failure or the like, and the clock from the selection circuit 10a or 10b is interrupted. , D-LPF
The serial data from 22 can be fixed (held) to the immediately preceding digital data. As a result, VCO 26
Is also fixed to the immediately preceding control voltage,
The accuracy of the clock output from the clock output terminal 28 is VC
It depends only on the error due to the change with time of O26, and a certain degree of frequency accuracy can be maintained in a short time. If the digital signal processing unit 23 has a large time constant,
The phase fluctuation of the clock input from the selection circuit 10 to the clock input terminal 19 during the normal operation or the phase fluctuation caused by the switching between the active system and the standby system of the clock packages 2a and 2b can be sufficiently absorbed. , A stable clock can be distributed to the clock package 2b.

Further, the selection circuit 16a of the clock package 2a is controlled by the control signal 15a so as to select the output clock of the phase comparison unit 6a, and the selection circuit 16b of the clock package 2b is also controlled by the control signal 15b. Since control is performed so as to select the output clock of the comparison unit 6b, the selection circuits 16a and 16b of the clock packages 2a and 2b output the same output clock (in this case, the output from the phase comparison unit 6a of the clock package 2a). Clock). Therefore, the output frequencies and phases of the VCOs 8a and 8b are substantially the same, although there are some differences due to variations in the components used. Therefore, when the clock package 2a is switched to the standby system and the clock package 2b is switched to the active system from this state, the inside of the clock package 2b is changed by the change of the control signal 15b to the external clock switching unit 4b, the selection circuits 16b and 10b. Is switched in the opposite direction to that described above. The clock package 2b operates in synchronization with the external clock from the clock supply device 1. However, the output frequency and phase of the VCO 8b do not change significantly, and the output clock from the internal clock distribution terminal 12b is It does not fluctuate due to the phase fluctuation absorbing ability of the internal clock generation unit 11b.

The case where the clock packages 2a and 2b are switched in the opposite direction, that is, the case where the clock package 2b is switched to the clock package 2a is, of course, the same as described above.

The clock generator of the present invention is not limited to the preferred embodiment shown in FIGS. 1 and 2, and various modifications and changes are possible. Such a modification will be described with reference to the block diagram of FIG. This modified clock generator also includes a pair of clock packages 2 connected to the clock supply 1.
a ′ and 2b ′. These clock packages 2a
, 2b 'are external clock switching units 4a and 4b, conversion units 5a and 5b, phase comparison units 6a and 6b, loop filters 7a and 7b, analog switches 16a' and 16b ',
VCOs 8a, 8b, frequency dividers 9a, 9b, selection circuit 10
a, 10b, and internal clock generators 11a, 11b
Consisting of In addition, both clock packages 2a 'and 2b'
Is cross-connected between the clock input terminals 13a and 13b and the clock output terminals 14a and 14b, which is the same as that of the clock generator of FIGS.

The clock generator of FIG. 3 is different from the conventional clock generator of FIG.
1 and 2b 'in that analog switches 16a' and 16b 'are added to the output side of the loop filters 7a and 7b. One input terminal of each of the analog switches 16a 'and 16b' is connected to a corresponding one of the loop filters 7a and 7b.
Are connected respectively. A DC input voltage of +2.5 V is input to the other input terminal. However, this is the case where the VCOs 8a and 8b output the center frequency when the control voltage of + 2.5V is applied, and when the control voltage at the time of the output of the center frequency is other than + 2.5V, the control voltage is adjusted accordingly. Shall be selected. Also, these analog switches 16a 'and 16b' control signals 15a,
15b.

The operation of the clock generator shown in FIG. 3 will be described. For example, assume that the clock package 2a 'is the active system and the clock package 2b' is the standby system. In this case, the analog switch 16a 'is controlled by the control signal 15a so as to select the output of the loop filter 7a. On the other hand, the analog switch 16b '
5b is controlled to select the + 2.5V side. As a result, the control voltage of the VCO 8b is fixed at + 2.5V.

Since the clock from the converter 5a and the clock from the frequency divider 9a usually have a phase difference of 180 °, the control voltage of the VCO 8a is also about + 2.5V.
Both VCOs 8a and 8b output substantially the same frequency. Therefore, the clock packages 2a 'and 2b'
When the switching between the active system and the standby system occurs, the inside of the clock package 2b 'is changed to the external clock switching unit 4b and the analog switch 1 by the change of the control signal 15b.
6b ', the selection circuit 10b is immediately switched in the reverse direction. Therefore, the clock package 2b 'synchronizes (follows) the external clock from the clock supply device 1,
The control voltage of CO8b hardly changes. Therefore, the clock output of the in-device clock distribution terminal 12b distributed to each part in the device hardly fluctuates.

The embodiment of the clock generator according to the present invention has been described in detail. However, the present invention should not be limited to only the specific embodiment, and it can be easily understood by those skilled in the art that various modifications can be made without departing from the gist of the present invention. For example, in the embodiment of FIG. 1, the selection circuits 16a and 16b are arranged and connected to the outputs of the phase comparators 6a and 6b, but may be arranged at the outputs of the loop filters 7a and 7b.

[0042]

As can be understood from the above description, according to the clock generator of the present invention, the control voltage of the VCO of the clock package operating as the standby system of the PLL circuit of the redundant clock package is set to the predetermined value. This makes it possible to prevent a sudden and large change in the control signal when switching between the active system and the standby system, and to effectively avoid the occurrence of a main signal error inside the device. Furthermore, there is a practically remarkable effect that a clock generator that satisfies strict characteristics according to international standards can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a preferred embodiment of a clock generator according to the present invention.

FIG. 2 is a detailed block diagram of an internal clock generation unit used in the clock generation device of FIG. 1;

FIG. 3 is a block diagram of another embodiment of the clock generator of the present invention.

FIG. 4 is a block diagram of a conventional clock generator.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Clock supply device 2a, 2b, 2a ', 2b' Clock package 6a, 6b Phase comparison part 7a, 7b Loop filter 8a, 8b Voltage control oscillator 9a, 9b Divider 16a, 16b Selection circuit 16a ', 16b' Analog switch 11a, 11b Internal clock generation unit 21 Conversion unit

Claims (5)

[Claims] A pair of clock packages in a redundant configuration for receiving an external clock from a reference clock source, each of the pair of clock packages having a phase locked loop circuit, wherein the pair of clock packages is based on a control signal; In a clock generator operating one of the clock packages as an operating system and the other as a standby system, a selection circuit is provided in each of the phase locked loop circuits of the pair of clock packages, and the phase locked loop circuit operates as the standby system Wherein the control voltage of the voltage controlled oscillator is set to a predetermined value. 2. The clock generator according to claim 1, wherein the control voltage of the standby voltage control oscillator is supplied from a phase locked loop circuit of the operating system. 3. The clock generator according to claim 1, wherein the control voltage of the standby voltage-controlled oscillator has a fixed value at which the voltage-controlled oscillator oscillates at a substantially center frequency. 4. The clock generator according to claim 1, wherein said pair of clock packages includes an internal clock generator for outputting a high-precision oscillation frequency to an output side of said phase locked loop circuit. apparatus. 5. The clock generator according to claim 4, wherein said internal clock generator has a phase locked loop including a digital signal processor and has a holdover function.