JP2000349339A - Semiconductor light emitting element and manufacture thereof - Google Patents

Semiconductor light emitting element and manufacture thereof

Info

Publication number
JP2000349339A
JP2000349339A JP15942399A JP15942399A JP2000349339A JP 2000349339 A JP2000349339 A JP 2000349339A JP 15942399 A JP15942399 A JP 15942399A JP 15942399 A JP15942399 A JP 15942399A JP 2000349339 A JP2000349339 A JP 2000349339A
Authority
JP
Japan
Prior art keywords
layer
light emitting
ohmic contact
single metal
alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15942399A
Other languages
Japanese (ja)
Inventor
Yukio Watanabe
辺 幸 雄 渡
Yasuo Idei
井 康 夫 出
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP15942399A priority Critical patent/JP2000349339A/en
Publication of JP2000349339A publication Critical patent/JP2000349339A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light emitting element for decreasing contact resistance, and for improving light extracting efficiency. SOLUTION: A light emitting layer 15 is formed on the upper face of a semiconductor substrate 11, an ohmic contact layer 18 is formed on the upper face of the light emitting layer 15, and single metallic layers or alloy layers 35a, 35b,... are scattered on the upper face of the ohmic contact layer 18. An oxide transparent conductive film 20 is formed on the upper faces of the scattered single metallic layers or alloy layers 35a, 35b,....

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体発光素子およ
びその製造方法に係り、特に、コンタクト抵抗を小さく
するとともに光の取り出し効率を向上するようにした半
導体発光素子およびその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device and a method of manufacturing the same, and more particularly, to a semiconductor light emitting device with reduced contact resistance and improved light extraction efficiency, and a method of manufacturing the same.

【0002】[0002]

【従来の技術および発明が解決しようとする課題】一般
に半導体発光素子10は図12に示すようにn型のGaAs
のような半導体基板11が備えられ、この上面に厚さが
0.5μmのn型のGaAsのようなバッファー層12を形成
するようになっている。
2. Description of the Related Art Generally, a semiconductor light emitting device 10 is an n-type GaAs as shown in FIG.
And a buffer layer 12 such as n-type GaAs having a thickness of 0.5 μm is formed on the upper surface of the semiconductor substrate 11.

【0003】このバッファー層12の上面にはn型のIn
0.5Al0.5Pのような層とn型のGaAsのような層とを10対
程度交互に積層した反射層13が設けられ、この上面に
厚さが0.6μmのn型のIn0.5Al0.5Pのようなクラッド
層14を形成するようになっている。
On the upper surface of the buffer layer 12, n-type In
A reflection layer 13 is provided in which about 10 pairs of layers such as 0.5 Al 0.5 P and layers such as n-type GaAs are alternately laminated, and an n-type In 0.5 Al 0.5 layer having a thickness of 0.6 μm is provided on an upper surface thereof. A cladding layer 14 such as P is formed.

【0004】このクラッド層14の上面に厚さが1.0
μmのZnをドープしたp型のIn0.5(Ga0.7Al0.30.5Pの
ような発光素子を形成する活性層15が設けられ、この
上面に厚さが1.0μmのp型のInO.5Al0.5Pのようなク
ラッド層16を形成するようになっている。
The thickness of the cladding layer 14 is 1.0
An active layer 15 for forming a light-emitting element such as p-type In 0.5 (Ga 0.7 Al 0.3 ) 0.5 P doped with μm of Zn is provided, and a 1.0 μm-thick p-type InO . A cladding layer 16 such as 5 Al 0.5 P is formed.

【0005】このクラッド層16の上面には厚さが0.
1〜3.0μmのn型のGaO.3AlO.7Asのような半導体層1
7が設けられ、その上面に厚さが0.01〜0.03μ
mのp型のGaAsのようなオーミックコンタクト層18を形
成するようになっている。
The upper surface of the cladding layer 16 has a thickness of 0.1 mm.
Semiconductor layer 1 such as n-type Ga O.3 Al O.7 As of 1 to 3.0 μm
7 and a thickness of 0.01 to 0.03 μm
An ohmic contact layer 18 such as p-type GaAs is formed.

【0006】このオーミックコンタクト層18の上面に
は厚さが10〜15nmの連続的に形成した半透明のAu、
Zn、Cr等の金属層19が設けられ、この上面にインジュ
ウム・錫・オキサイドのような酸化物透明導電膜20を
形成するようになっている。
On the upper surface of the ohmic contact layer 18, a continuously formed translucent Au having a thickness of 10 to 15 nm is formed.
A metal layer 19 of Zn, Cr, or the like is provided, and an oxide transparent conductive film 20 such as indium / tin / oxide is formed on the upper surface thereof.

【0007】この酸化物透明導電膜20の上面には厚さ
が0.2μmのAuGeとAuのようなp型のボンディング用電
極21が設けられ、また、半導体基板11の下面には厚
さが200nmのAuGeのようなn型の電極22が設けら
れ、半導体発光素子10を形成するようになっている。
On the upper surface of the transparent oxide conductive film 20, a p-type bonding electrode 21 such as AuGe and Au having a thickness of 0.2 μm is provided, and on the lower surface of the semiconductor substrate 11, the thickness is reduced. An n-type electrode 22 such as 200 nm of AuGe is provided to form the semiconductor light emitting device 10.

【0008】このような半導体発光素子10は金属層1
9を設けたのでコンタクト抵抗を小さくすることができ
るがこの金属層19が厚いと活性層15からの光の取り
出し効率を低下させてしまい、反対に、薄いと光の取り
出し効率を向上できるがコンタクト抵抗を大きくすると
言う問題があった。
[0008] Such a semiconductor light-emitting element 10 has a metal layer 1
9, the contact resistance can be reduced. However, if the metal layer 19 is thick, the light extraction efficiency from the active layer 15 is reduced. Conversely, if the metal layer 19 is thin, the light extraction efficiency can be improved. There was a problem of increasing the resistance.

【0009】そのうえ、この金属層19が連続的に形成
されているため反射層13の反射効率を高めても光の取
り出しを低下させてしまう等と言う問題があった。
In addition, since the metal layer 19 is formed continuously, there is a problem that even if the reflection efficiency of the reflection layer 13 is increased, light extraction is reduced.

【0010】そこで本発明はコンタクト抵抗を小さくす
るとともに光の透過を高めるようにした半導体発光素子
およびその製造方法を提供することを目的とするもので
ある。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor light emitting device having a low contact resistance and a high light transmission, and a method of manufacturing the same.

【0011】[0011]

【課題を解決するための手段】請求項1の発明は半導体
基板の上面に発光層を形成し、この発光層の上面にオー
ミックコンタクト層を形成し、このオーミックコンタク
ト層の上面に単金属層または合金層を点在させ、この点
在させた単金属層または合金層の上面に酸化物透明導電
膜を形成したことを特徴とする半導体発光素子を提供す
るものである。
According to a first aspect of the present invention, a light emitting layer is formed on an upper surface of a semiconductor substrate, an ohmic contact layer is formed on an upper surface of the light emitting layer, and a monometal layer or an ohmic contact layer is formed on the upper surface of the ohmic contact layer. An object of the present invention is to provide a semiconductor light emitting device characterized in that an alloy layer is interspersed, and an oxide transparent conductive film is formed on the upper surface of the interspersed single metal layer or alloy layer.

【0012】また、請求項2の発明は半導体基板の上面
に発光層を形成し、この発光層の上面に反応抑制層を形
成し、この反応抑制層の上面にオーミックコンタクト層
を形成し、このオーミックコンタクト層の上面に単金属
層または合金層を点在させ、この点在させた単金属層ま
たは合金層の上面に酸化物透明導電膜を形成したことを
特徴とする半導体発光素子を提供するものである。
According to a second aspect of the present invention, a light emitting layer is formed on an upper surface of a semiconductor substrate, a reaction suppressing layer is formed on the light emitting layer, and an ohmic contact layer is formed on the upper surface of the reaction suppressing layer. Provided is a semiconductor light emitting device characterized in that a single metal layer or an alloy layer is interspersed on an upper surface of an ohmic contact layer, and an oxide transparent conductive film is formed on an upper surface of the interspersed single metal layer or alloy layer. Things.

【0013】さらに、請求項3の発明は半導体基板の上
面に反射層を介して発光層を形成し、この発光層の上面
に反応抑制層を形成し、この反応抑制層の上面にオーミ
ックコンタクト層を形成し、このオーミックコンタクト
層の上面に単金属層または合金層を点在させ、この点在
させた単金属層または合金層の上面に酸化物透明導電膜
を形成したことを特徴とする半導体発光素子を提供する
ものである。
Further, according to a third aspect of the present invention, a light emitting layer is formed on an upper surface of a semiconductor substrate via a reflective layer, a reaction suppressing layer is formed on the upper surface of the light emitting layer, and an ohmic contact layer is formed on the upper surface of the reaction suppressing layer. Wherein a single metal layer or an alloy layer is interspersed on the upper surface of the ohmic contact layer, and an oxide transparent conductive film is formed on the upper surface of the interspersed single metal layer or the alloy layer. A light-emitting element is provided.

【0014】さらに、請求項4の発明の単金属層または
合金層はAu、Zn、Crの単金属層またはこれらの合金層で
あることを特徴とする半導体発光素子を提供するもので
ある。
Further, the present invention provides a semiconductor light emitting device wherein the single metal layer or the alloy layer is a single metal layer of Au, Zn, Cr or an alloy layer thereof.

【0015】さらに、請求項5の発明は反応抑制層はIn
GaAlPであることを特徴とする半導体発光素子を提供す
るものである。
Further, in the invention according to claim 5, the reaction suppressing layer is preferably made of In.
It is intended to provide a semiconductor light emitting device characterized by being GaAlP.

【0016】さらにまた、請求項6の発明は半導体基板
の上面に発光層を形成し、この発光層の上面に反応抑制
層を形成し、この反応抑制層の上面にオーミックコンタ
クト層を形成し、このオーミックコンタクト層の上面に
単金属層または合金層を蒸着し、この蒸着した単金属層
または合金層を熱処理しオーミックコンタクト層の上面
に単金属層または合金層を点在させるようにしたことを
特徴とする半導体発光素子の製造方法を提供するもので
ある。
Further, according to the invention of claim 6, a light emitting layer is formed on the upper surface of the semiconductor substrate, a reaction suppressing layer is formed on the light emitting layer, and an ohmic contact layer is formed on the upper surface of the reaction suppressing layer. A single metal layer or an alloy layer is deposited on the upper surface of the ohmic contact layer, and the deposited single metal layer or the alloy layer is heat-treated so that the single metal layer or the alloy layer is scattered on the upper surface of the ohmic contact layer. An object of the present invention is to provide a method for manufacturing a semiconductor light emitting device.

【0017】さらに、請求項7の発明の熱処理は350
〜450℃の温度の下で行うことを特徴とする半導体発
光素子の製造方法を提供するものである。
Further, the heat treatment according to the seventh aspect of the present invention is performed
An object of the present invention is to provide a method for manufacturing a semiconductor light emitting device, which is performed at a temperature of about 450 ° C.

【0018】さらに、請求項8の発明の熱処理はAr雰囲
気中で行うことを特徴とする半導体発光素子の製造方法
を提供するものである。
Further, the present invention provides a method for manufacturing a semiconductor light emitting device, wherein the heat treatment is performed in an Ar atmosphere.

【0019】[0019]

【発明の実施の形態】以下本発明半導体発光素子の実施
の形態を添付図面を参照しながら説明する。
Embodiments of the present invention will be described below with reference to the accompanying drawings.

【0020】本発明半導体発光素子30は基本的には従
来の半導体発光素子10とほぼ同様に構成されているの
で従来の半導体発光素子10と同一部分は同一符号を付
して本発明半導体発光素子30を説明する。
Since the semiconductor light emitting device 30 of the present invention is basically constructed in substantially the same manner as the conventional semiconductor light emitting device 10, the same parts as those of the conventional semiconductor light emitting device 10 are denoted by the same reference numerals, and 30 will be described.

【0021】本発明半導体発光素子30には図3に示す
ようにn型のGaAsのような半導体基板11が備えられ、
この上面に厚さが0.5μmのn型のGaAsのようなバッフ
ァー層12を形成するようになっている。
The semiconductor light emitting device 30 of the present invention is provided with a semiconductor substrate 11 such as n-type GaAs as shown in FIG.
On this upper surface, a buffer layer 12 such as n-type GaAs having a thickness of 0.5 μm is formed.

【0022】このバッファー層12の上面にはn型のIn
0.5Al0.5Pのような層とn型のGaAsのような層とを10対
程度交互に積層した反射層13が設けられ、この上面に
厚さが0.6μmのn型のIn0.5Al0.5Pのようなクラッド
層14を形成するようになっている。
On the upper surface of the buffer layer 12, n-type In
A reflection layer 13 is provided in which about 10 pairs of layers such as 0.5 Al 0.5 P and layers such as n-type GaAs are alternately laminated, and an n-type In 0.5 Al 0.5 layer having a thickness of 0.6 μm is provided on an upper surface thereof. A cladding layer 14 such as P is formed.

【0023】このクラッド層14の上面に厚さが1.0
μmのZnをドープしたp型のIn0.5(Ga0.7Al0.3)0.5Pの
ような発光素子を形成する活性層15が設けられ、この
上面に厚さが1.0μmのp型のInO.5Al0.5Pのようなク
ラッド層16を形成するようになっている。
The upper surface of the cladding layer 14 has a thickness of 1.0
An active layer 15 for forming a light-emitting element such as p-type In 0.5 (Ga 0.7 Al 0.3 ) 0.5 P doped with μm Zn is provided, and a 1.0 μm-thick p-type InO . A cladding layer 16 such as 5 Al 0.5 P is formed.

【0024】このクラッド層16の上面には厚さが0.
1〜3.0μmのp型のGaO.3AlO.7Asのような半導体層1
7が設けられ、その上面に図4に示すように厚さが0.
01〜0.03μmのInO.5(Ga0.65Al0.350.5OPのよ
うな反応を抑制する反応抑制層31を形成するようにな
っている。
The upper surface of the cladding layer 16 has a thickness of 0.1 mm.
Semiconductor layer 1 such as p-type Ga O.3 Al O.7 As of 1 to 3.0 μm
7 on the upper surface of which a thickness of 0.
A reaction suppression layer 31 for suppressing a reaction such as In O.5 (Ga 0.65 Al 0.35 ) 0.5 O P of 01 to 0.03 μm is formed.

【0025】この反応抑制層31の上面には図5に示す
ような厚さが0.01〜0.03μmのp型のGaAsのよう
なオーミックコンタクト層18が設けられ、この上面に
図6に示すような厚さが0.O1〜0.2μmのn型のIn
0.5Al0.5Pのような電流ブロック層32を形成するよう
になっている。
An ohmic contact layer 18 such as p-type GaAs having a thickness of 0.01 to 0.03 μm as shown in FIG. 5 is provided on the upper surface of the reaction suppression layer 31. The thickness as shown is 0. O1-0.2 μm n-type In
A current blocking layer 32 of 0.5 Al 0.5 P is formed.

【0026】この電流ブロック層32には図示しないが
ホトレジストが被覆され、その通電領域に相当する部分
を熱燐酸または熱硫酸によりオーミックコンタクト層1
8まで選択的に除去し図7に示すような直径が110μ
mの電流ブロック部33を形成する。
The current blocking layer 32 is coated with a photoresist (not shown), and a portion corresponding to a current-carrying region is formed in the ohmic contact layer 1 with hot phosphoric acid or hot sulfuric acid.
8 to remove 110 μm in diameter as shown in FIG.
An m current block 33 is formed.

【0027】この電流ブロック部33を形成後ホトレジ
ストを除去し水洗いをした後乾燥する。
After the formation of the current block 33, the photoresist is removed, washed with water and dried.

【0028】この電流ブロック部33およびオーミック
コンタクト層18の全表面には図8に示すように厚さが
10〜15nmのAu、Zn、Cr等の金属蒸着膜34が形成さ
れる。
As shown in FIG. 8, a metal deposited film 34 of Au, Zn, Cr or the like having a thickness of 10 to 15 nm is formed on the entire surface of the current block portion 33 and the ohmic contact layer 18.

【0029】この金属蒸着膜34等を形成した半導体基
板11は図示しないがDCマグネトロンスパッタ装置に入
れられ、真空度が約1Eー3torr、温度が150〜20
0℃、Arと酸素との圧力比が100:1の混合ガスの雰
囲気中で約100分程度加熱され、図9に示すように厚
さが240nmのインジュウム・錫・オキサイドのような
酸化物透明導電膜20を形成するようにする。
The semiconductor substrate 11 on which the metal deposited film 34 and the like are formed is placed in a DC magnetron sputtering device (not shown), and the degree of vacuum is about 1E-3 torr and the temperature is 150 to 20.
It is heated for about 100 minutes at 0 ° C. in an atmosphere of a mixed gas having a pressure ratio of Ar and oxygen of 100: 1, and as shown in FIG. 9, a transparent oxide such as indium / tin / oxide having a thickness of 240 nm is provided. The conductive film 20 is formed.

【0030】この酸化物透明導電膜20の上面には厚さ
が0.2μmのAuGeと1μmのAuのような金属膜を蒸着
し、これをパターニング等して図10に示すように直径
約100μmのボンディング用のp型の電極21を形成す
るようになっている。
A metal film such as AuGe having a thickness of 0.2 μm and Au having a thickness of 1 μm is vapor-deposited on the upper surface of the oxide transparent conductive film 20, and this is patterned and the like, as shown in FIG. The p-type electrode 21 for bonding is formed.

【0031】また、半導体基板11の下面を鏡面研磨し
た後厚さが200nmのAuGeのような金属が蒸着され、図
11に示すようにn型の電極22を形成するようになっ
ている。
After the lower surface of the semiconductor substrate 11 is mirror-polished, a metal such as AuGe having a thickness of 200 nm is deposited to form an n-type electrode 22 as shown in FIG.

【0032】このように形成した半導体基板11は35
0〜450℃のAr雰囲気中で約10分間加熱処理され、
Au、Zn、Cr等の金属蒸着膜34を凝縮して点在状態の金
属粒子35a、35b…(図1、図2参照)を形成する。
The semiconductor substrate 11 formed in this way is 35
Heat treatment in an Ar atmosphere of 0 to 450 ° C. for about 10 minutes,
The metal vapor-deposited film 34 of Au, Zn, Cr or the like is condensed to form interspersed metal particles 35a, 35b (see FIGS. 1 and 2).

【0033】この凝縮して点在状態に形成した金属粒子
35a、35b…は面積が50μm×50μmにおいて約1
0箇あり、その大きさが4μm×4μm程度のものであり
発光面に対して約0.02%を占める程度のものであっ
た。
The metal particles 35a, 35b,... Formed in a condensed state by condensation are about 1 μm in area of 50 μm × 50 μm.
There were zero, and the size was about 4 μm × 4 μm, which was about 0.02% of the light emitting surface.

【0034】この金属粒子35a、35b…を有する半導
体基板11を電極21を中心に図示しないダイアモンド
針を備えたスクライプ装置により直径が約を150μm
〜250μm角にけがかれ、ブレイキングにより図1、
図2に示すように半導体発光素子20を形成する。
The semiconductor substrate 11 having the metal particles 35a, 35b... Has a diameter of about 150 μm by a scribing device provided with a diamond needle (not shown) around the electrode 21.
~ 250 μm square, broken by breaking, Figure 1,
The semiconductor light emitting device 20 is formed as shown in FIG.

【0035】この金属粒子35a、35b…を有する半導
体基板30は従来の金属層19を有する半導体発光素子
10と比較すると活性層15の光の取り出し効率を13
0%に向上することができた。
The semiconductor substrate 30 having the metal particles 35a, 35b... Has a light extraction efficiency of the active layer 15 of 13 compared to the conventional semiconductor light emitting device 10 having the metal layer 19.
It could be improved to 0%.

【0036】また、この凝縮して点在状態に形成する金
属粒子35a、35b…と電流ブロック部33とはオーミ
ックコンタクト層18と酸化物透明導電膜20との接触
抵抗を低くするばかりか半導体発光素子30の順方向電
圧を低下させることができる。
The condensed and formed metal particles 35a, 35b... And the current block portion 33 not only reduce the contact resistance between the ohmic contact layer 18 and the oxide transparent conductive film 20, but also emit light from the semiconductor. The forward voltage of the device 30 can be reduced.

【0037】さらに、従来の連続した金属膜19に比べ
通電中の順方向電圧変動を少なくすることができる。
Further, the forward voltage fluctuation during energization can be reduced as compared with the conventional continuous metal film 19.

【0038】その他オーミックコンタクト層18の下側
に反応抑制層を設けたから熱処理中にAu,Ge,Cr等の金
属が活性層15への拡散やその結晶欠陥が防止され、信
頼性の高い発光素子を形成することができた。
In addition, since a reaction suppressing layer is provided below the ohmic contact layer 18, diffusion of metals such as Au, Ge, and Cr into the active layer 15 and crystal defects thereof during heat treatment are prevented, and a highly reliable light emitting device. Could be formed.

【0039】なお、上記実施の形態では活性層15、オ
ーミックコンタクト層18、金属蒸着膜34、酸化物透
明導電膜20等を形成した半導体基板11を熱処理した
が活性層15、オーミックコンタクト層18、金属蒸着
膜34等を蒸着しただけの半導体基板11で熱処理し、
これに酸化物透明導電膜20等を形成するようにしても
よい。
In the above embodiment, the semiconductor substrate 11 on which the active layer 15, the ohmic contact layer 18, the metal deposited film 34, the oxide transparent conductive film 20, etc. are formed is heat-treated. Heat treatment is performed on the semiconductor substrate 11 on which the metal deposition film 34 and the like have just been deposited,
An oxide transparent conductive film 20 or the like may be formed thereon.

【0040】また、オーミックコンタクト層18の上面
に蒸着する金属を単体のAu、Zn、Cr等を用いたがこれを
Au、Zn、Cr等の合金の金属を用いてもほぼ同様に凝縮し
た点在状態の金属粒子を得ることができる。
The metal deposited on the upper surface of the ohmic contact layer 18 is Au, Zn, Cr or the like.
Even in the case of using a metal of an alloy such as Au, Zn, and Cr, it is possible to obtain condensed metal particles in a substantially similar manner.

【0041】[0041]

【発明の効果】請求項1、2の発明は半導体基板の上面
に発光層を形成し、この発光層の上面にオーミックコン
タクト層を形成し、このオーミックコンタクト層の上面
に単金属層または合金層を点在させ、この点在させた単
金属層または合金層の上面に酸化物透明導電膜を形成し
たから低抵抗の光取り出し率を向上した半導体発光素子
を得ることがでえきる。
According to the first and second aspects of the present invention, a light emitting layer is formed on the upper surface of a semiconductor substrate, an ohmic contact layer is formed on the upper surface of the light emitting layer, and a monometal layer or an alloy layer is formed on the upper surface of the ohmic contact layer. And a transparent conductive oxide film is formed on the upper surface of the single metal layer or the alloy layer where the single metal layer or the alloy layer is interspersed, so that a semiconductor light emitting device having a low resistance and an improved light extraction rate can be obtained.

【0042】また、請求項2、5の発明は半導体基板の
上面に発光層を形成し、この発光層の上面に反応抑制層
を形成し、この反応抑制層の上面にオーミックコンタク
ト層を形成し、このオーミックコンタクト層の上面に単
金属層または合金層を点在させ、この点在させた単金属
層または合金層の上面に酸化物透明導電膜を形成したか
ら熱処理において発光層に対する悪影響を及ぼすことが
ない。
According to another aspect of the present invention, a light emitting layer is formed on an upper surface of a semiconductor substrate, a reaction suppression layer is formed on the light emitting layer, and an ohmic contact layer is formed on the reaction suppression layer. A single metal layer or an alloy layer is scattered on the upper surface of the ohmic contact layer, and an oxide transparent conductive film is formed on the upper surface of the scattered single metal layer or the alloy layer. Nothing.

【0043】さらに、請求項3の発明は半導体基板の上
面に反射層を介して発光層を形成し、この発光層の上面
に反応抑制層を形成し、この反応抑制層の上面にオーミ
ックコンタクト層を形成し、このオーミックコンタクト
層の上面に単金属層または合金層を点在させ、この点在
させた単金属層または合金層の上面に酸化物透明導電膜
を形成したから発光層の反射率を向上させることができ
る。
Further, according to a third aspect of the present invention, a light emitting layer is formed on the upper surface of the semiconductor substrate via a reflective layer, a reaction suppressing layer is formed on the light emitting layer, and an ohmic contact layer is formed on the upper surface of the reaction suppressing layer. Was formed, and a single metal layer or an alloy layer was scattered on the upper surface of the ohmic contact layer, and an oxide transparent conductive film was formed on the upper surface of the scattered single metal layer or alloy layer. Can be improved.

【0044】さらにまた、請求項6、7、8の発明は半
導体基板の上面に発光層を形成し、この発光層の上面に
反応抑制層を形成し、この反応抑制層の上面にオーミッ
クコンタクト層を形成し、このオーミックコンタクト層
の上面に単金属層または合金層を蒸着し、この蒸着した
単金属層または合金層を熱処理しオーミックコンタクト
層の上面に単金属層または合金層を点在させるようにし
たから低抵抗の光取り出し率を向上した半導体発光素子
を製造することがでえきる。
Further, according to the present invention, a light emitting layer is formed on the upper surface of the semiconductor substrate, a reaction suppressing layer is formed on the light emitting layer, and an ohmic contact layer is formed on the upper surface of the reaction suppressing layer. Is formed, a single metal layer or an alloy layer is deposited on the upper surface of the ohmic contact layer, and the deposited single metal layer or the alloy layer is heat-treated so that the single metal layer or the alloy layer is dotted on the upper surface of the ohmic contact layer. Thus, it is possible to manufacture a semiconductor light emitting device having a low resistance and an improved light extraction rate.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体発光素子の概要を示す断面図。FIG. 1 is a sectional view showing an outline of a semiconductor light emitting device of the present invention.

【図2】図1の平面を一部を切断した顕微鏡写真。FIG. 2 is a micrograph of the plane of FIG. 1 partially cut away.

【図3】本発明の半導体発光素子の第1の製造工程を示
す説明図。
FIG. 3 is an explanatory view showing a first manufacturing process of the semiconductor light emitting device of the present invention.

【図4】本発明の半導体発光素子の第2の製造工程を示
す説明図。
FIG. 4 is an explanatory view showing a second manufacturing process of the semiconductor light emitting device of the present invention.

【図5】本発明の半導体発光素子の第3の製造工程を示
す説明図。
FIG. 5 is an explanatory view showing a third manufacturing step of the semiconductor light emitting device of the present invention.

【図6】本発明の半導体発光素子の第4の製造工程を示
す説明図。
FIG. 6 is an explanatory view showing a fourth manufacturing step of the semiconductor light emitting device of the present invention.

【図7】本発明の半導体発光素子の第5の製造工程を示
す説明図。
FIG. 7 is an explanatory view showing a fifth manufacturing step of the semiconductor light emitting device of the present invention.

【図8】本発明の半導体発光素子の第6の製造工程を示
す説明図。
FIG. 8 is an explanatory view showing a sixth manufacturing step of the semiconductor light emitting device of the present invention.

【図9】本発明の半導体発光素子の第7の製造工程を示
す説明図。
FIG. 9 is an explanatory view showing a seventh manufacturing step of the semiconductor light emitting device of the present invention.

【図10】本発明の半導体発光素子の第8の製造工程を
示す説明図。
FIG. 10 is an explanatory view showing an eighth manufacturing step of the semiconductor light emitting device of the present invention.

【図11】本発明の半導体発光素子の第9の製造工程を
示す説明図。
FIG. 11 is an explanatory view showing a ninth manufacturing step of the semiconductor light emitting device of the present invention.

【図12】従来の半導体発光素子の概要を示す断面図。FIG. 12 is a sectional view showing an outline of a conventional semiconductor light emitting device.

【符号の説明】 10、30 半導体発光素子 11 半導体基板 12 バッファー層 13 反射層 14 n型のクラッド層 15 活性層 16 p型のクラッド層 17 半導体層 18 オーミックコンタクト層 19 金属層 20 酸化物透明導電膜 31 反応抑制層 32 電流ブロック層 33 電流ブロック部 34 金属蒸着膜 35a、35b… 金属粒子DESCRIPTION OF SYMBOLS 10, 30 Semiconductor light emitting element 11 Semiconductor substrate 12 Buffer layer 13 Reflective layer 14 n-type clad layer 15 Active layer 16 p-type clad layer 17 Semiconductor layer 18 Ohmic contact layer 19 Metal layer 20 Oxide transparent conductive Film 31 Reaction suppression layer 32 Current block layer 33 Current block section 34 Metal deposition film 35a, 35b ... Metal particles

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5F041 AA03 AA14 CA34 CA35 CA39 CA73 CA83 CA85 CA88 CA92 CA98  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F041 AA03 AA14 CA34 CA35 CA39 CA73 CA83 CA85 CA88 CA92 CA98

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】半導体基板の上面に発光層を形成し、 この発光層の上面にオーミックコンタクト層を形成し、 このオーミックコンタクト層の上面に単金属層または合
金層を点在させ、 この点在させた単金属層または合金層の上面に酸化物透
明導電膜を形成し、 たことを特徴とする半導体発光素子。
1. A light emitting layer is formed on an upper surface of a semiconductor substrate, an ohmic contact layer is formed on an upper surface of the light emitting layer, and a single metal layer or an alloy layer is interspersed on the upper surface of the ohmic contact layer. An oxide transparent conductive film is formed on the upper surface of the single metal layer or the alloy layer thus formed.
【請求項2】半導体基板の上面に発光層を形成し、 この発光層の上面に反応抑制層を形成し、 この反応抑制層の上面にオーミックコンタクト層を形成
し、 このオーミックコンタクト層の上面に単金属層または合
金層を点在させ、 この点在させた単金属層または合金層の上面に酸化物透
明導電膜を形成し、 たことを特徴とする半導体発光素子。
2. A light emitting layer is formed on an upper surface of a semiconductor substrate, a reaction suppression layer is formed on an upper surface of the light emitting layer, an ohmic contact layer is formed on an upper surface of the reaction suppression layer, and an ohmic contact layer is formed on an upper surface of the ohmic contact layer. A semiconductor light emitting device comprising: a single metal layer or an alloy layer interspersed; and a transparent oxide conductive film formed on an upper surface of the interspersed single metal layer or alloy layer.
【請求項3】半導体基板の上面に反射層を介して発光層
を形成し、 この発光層の上面に反応抑制層を形成し、 この反応抑制層の上面にオーミックコンタクト層を形成
し、 このオーミックコンタクト層の上面に単金属層または合
金層を点在させ、 この点在させた単金属層または合金層の上面に酸化物透
明導電膜を形成し、 たことを特徴とする半導体発光素子。
3. A light emitting layer is formed on an upper surface of a semiconductor substrate via a reflection layer, a reaction suppressing layer is formed on the light emitting layer, an ohmic contact layer is formed on an upper surface of the reaction suppressing layer, A semiconductor light emitting device comprising: a single metal layer or an alloy layer interspersed on an upper surface of a contact layer; and a transparent oxide conductive film formed on the upper surface of the interspersed single metal layer or the alloy layer.
【請求項4】単金属層または合金層はAu、Zn、Crの単金
属層またはこれらの合金層であることを特徴とする請求
項1、2または3記載の半導体発光素子。
4. The semiconductor light emitting device according to claim 1, wherein the single metal layer or the alloy layer is a single metal layer of Au, Zn, Cr or an alloy layer thereof.
【請求項5】反応抑制層はInGaAlPであることを特徴と
する請求項2または3記載の半導体発光素子の製造方
法。
5. The method according to claim 2, wherein the reaction suppressing layer is made of InGaAlP.
【請求項6】半導体基板の上面に発光層を形成し、 この発光層の上面に反応抑制層を形成し、 この反応抑制層の上面にオーミックコンタクト層を形成
し、 このオーミックコンタクト層の上面に単金属層または合
金層を蒸着し、 この蒸着した単金属層または合金層を熱処理しオーミッ
クコンタクト層の上面に単金属層または合金層を点在さ
せる、 ようにしたことを特徴とする半導体発光素子の製造方
法。
6. A light emitting layer is formed on an upper surface of a semiconductor substrate, a reaction suppressing layer is formed on an upper surface of the light emitting layer, an ohmic contact layer is formed on an upper surface of the reaction suppressing layer, and an ohmic contact layer is formed on an upper surface of the ohmic contact layer. A semiconductor light-emitting element, wherein a single metal layer or an alloy layer is deposited, and the deposited single metal layer or the alloy layer is heat-treated so that the single metal layer or the alloy layer is scattered on the upper surface of the ohmic contact layer. Manufacturing method.
【請求項7】熱処理は350〜450℃の温度の下で行
うことを特徴とする請求項6記載の半導体発光素子の製
造方法。
7. The method according to claim 6, wherein the heat treatment is performed at a temperature of 350 to 450 ° C.
【請求項8】熱処理はAr雰囲気中で行うことを特徴とす
る請求項6または7記載の半導体発光素子の製造方法。
8. The method according to claim 6, wherein the heat treatment is performed in an Ar atmosphere.
JP15942399A 1999-06-07 1999-06-07 Semiconductor light emitting element and manufacture thereof Pending JP2000349339A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15942399A JP2000349339A (en) 1999-06-07 1999-06-07 Semiconductor light emitting element and manufacture thereof

Publications (1)

Publication Number Publication Date
JP2000349339A true JP2000349339A (en) 2000-12-15

Family

ID=15693429

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15942399A Pending JP2000349339A (en) 1999-06-07 1999-06-07 Semiconductor light emitting element and manufacture thereof

Country Status (1)

Country Link
JP (1) JP2000349339A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10203809A1 (en) * 2002-01-31 2003-08-21 Osram Opto Semiconductors Gmbh Radiation-emitting semiconductor component

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10203809A1 (en) * 2002-01-31 2003-08-21 Osram Opto Semiconductors Gmbh Radiation-emitting semiconductor component
US7242025B2 (en) 2002-01-31 2007-07-10 Osram Opto Semiconductors Gmbh Radiation emitting semiconductor component having a nitride compound semiconductor body and a contact metallization layer on its surface
DE10203809B4 (en) * 2002-01-31 2010-05-27 Osram Opto Semiconductors Gmbh Radiation-emitting semiconductor component

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