JP2000349283A - High withstand-voltage semiconductor device and its manufacture - Google Patents

High withstand-voltage semiconductor device and its manufacture

Info

Publication number
JP2000349283A
JP2000349283A JP11155837A JP15583799A JP2000349283A JP 2000349283 A JP2000349283 A JP 2000349283A JP 11155837 A JP11155837 A JP 11155837A JP 15583799 A JP15583799 A JP 15583799A JP 2000349283 A JP2000349283 A JP 2000349283A
Authority
JP
Japan
Prior art keywords
protective film
semiconductor device
semiconductor substrate
hydrogen
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11155837A
Other languages
Japanese (ja)
Other versions
JP3444815B2 (en
Inventor
Takahiko Hori
貴彦 堀
Yukio Takizawa
幸雄 滝沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP15583799A priority Critical patent/JP3444815B2/en
Publication of JP2000349283A publication Critical patent/JP2000349283A/en
Application granted granted Critical
Publication of JP3444815B2 publication Critical patent/JP3444815B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To control an interface state density so as to restrain a breakdown phenomenon from occurring between a source and a drain by a method wherein a protective film of an atom ratio Si/N which is set smaller than a specific value is formed on a semiconductor device provided on a semiconductor substrate. SOLUTION: A gate oxide film 1 is formed on the surface of a semiconductor substrate 10, a gate electrode 2 is formed thereon, ions are implanted using the gate oxide film 1 and the gate electrode 2 as a mask for the formation of source/drain regions 3 and 4. Then, an interlayer insulating film 5, a contact window is provided to the source/drain regions 3 and 4, and then a metal electrode 6 is formed by patterning. Lastly, a stoichimetric silicon nitride film whose atom ratio Si/N is smaller than 0.7 is grown as a protective film 7. By this setup, an electrolytic balance is less lost at an interface, and a breakdown phenomenon occurs less.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、高耐圧半導体装置
およびその製造方法に関するものである。
The present invention relates to a high breakdown voltage semiconductor device and a method of manufacturing the same.

【0002】[0002]

【従来の技術】従来より、半導体、特にパワートランジ
スタ単体あるいはそれを内蔵したICの最上層の保護膜
には、ポリイミドやプラズマナイトライド等が用いられ
ている。後者のプラズマナイトライドは、前者に比べて
外部からの耐湿性、耐アルカリイオン性の面で非常に優
れており、しばしば一般の標準的な半導体装置の保護膜
として用いられる。
2. Description of the Related Art Conventionally, polyimide, plasma nitride, or the like has been used as a protective film on the uppermost layer of a semiconductor, particularly a power transistor alone or an IC containing the same. The latter plasma nitride is extremely superior to the former in terms of moisture resistance and alkali ion resistance from the outside, and is often used as a protective film for general standard semiconductor devices.

【0003】図3は、従来の高耐圧MOS型トランジス
タを含む高耐圧半導体装置の保護膜の製造工程を示す。
図3(a)に示すように、シリコン基板10にはゲート
酸化膜1およびゲート電極2が形成されている。このゲ
ート酸化膜1,ゲート電極2をマスクとして、通常のイ
オン注入を用いて、図3(b)に示すように、ソース
3、ドレイン4が形成される。
FIG. 3 shows a process of manufacturing a protective film of a conventional high breakdown voltage semiconductor device including a high breakdown voltage MOS transistor.
As shown in FIG. 3A, a gate oxide film 1 and a gate electrode 2 are formed on a silicon substrate 10. Using the gate oxide film 1 and the gate electrode 2 as a mask, the source 3 and the drain 4 are formed as shown in FIG.

【0004】図3(c)に示すように、このソース3、
ドレイン4とゲート電極2を覆うように層間絶縁膜5が
形成された後、コンタクトホールが形成され、図3
(d)に示すようにコンタクトホールに金属電極6が形
成される。最後に、図3(e)に示すように、窒素ガス
雰囲気下で基板の全面を覆うように保護膜7が形成され
て半導体装置が形成される。
[0004] As shown in FIG.
After an interlayer insulating film 5 is formed so as to cover the drain 4 and the gate electrode 2, a contact hole is formed.
As shown in (d), the metal electrode 6 is formed in the contact hole. Finally, as shown in FIG. 3E, a protective film 7 is formed so as to cover the entire surface of the substrate in a nitrogen gas atmosphere, and a semiconductor device is formed.

【0005】このような半導体装置の製造工程では、保
護膜7として、耐湿性、耐アルカリイオン性に優れたプ
ラズマナイトライドが用いられることが多く、この保護
膜7は、原子数比でSi:N=3:4すなわち(Si/
N)=0.7とほぼSi34の化学量論的組成で形成さ
れる。上記のようにして製造された高耐圧MOSトラン
ジスタは、動作時に所望の特性をもって動作することが
要求されると共に、非動作時においてもゲート電圧が0
ボルトもしくはオープン状態で、ソース−ドレイン間に
印加される数百ボルトの電圧により電流が流れない事が
必要とされている。
In the manufacturing process of such a semiconductor device, a plasma nitride excellent in moisture resistance and alkali ion resistance is often used as the protective film 7, and this protective film 7 is composed of Si: N = 3: 4, that is, (Si /
N) = 0.7 and a stoichiometric composition of approximately Si 3 N 4 . The high breakdown voltage MOS transistor manufactured as described above is required to operate with desired characteristics during operation and has a gate voltage of 0 even during non-operation.
It is necessary that no current flows due to a voltage of several hundred volts applied between the source and the drain in a volt or open state.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、上記従
来の製造方法によって形成されたMOS型トランジスタ
では、図3(e)に示すように、シリコン基板10と層
間絶縁膜5との界面に×印で表示された界面準位8が形
成されやすくなる。この界面準位8は、ソース3,ドレ
イン4のような高濃度に不純物が拡散された領域の表面
上だけでなく、シリコン基板10の表面やMOS型トラ
ンジスタのチャンネル領域のような低不純物濃度領域に
も形成され、特に低不純物濃度領域では、界面準位がト
ランジスタの特性に与える影響が大きくなる。
However, in the MOS transistor formed by the above-described conventional manufacturing method, as shown in FIG. 3E, an X mark is formed at the interface between the silicon substrate 10 and the interlayer insulating film 5. The indicated interface level 8 is easily formed. This interface state 8 is formed not only on the surface of a region where impurities are diffused at a high concentration such as the source 3 and the drain 4, but also on a surface of the silicon substrate 10 or a low impurity concentration region such as a channel region of a MOS transistor. In particular, in the low impurity concentration region, the influence of the interface state on the characteristics of the transistor increases.

【0007】すなわち、ドレイン4のチャンネルに近い
部分や、低不純物濃度領域、特にチャンネル領域では、
不均一に界面準位が生じると、ソース3とドレイン4の
間に数百ボルトの高電圧が印加されたとき、チャンネル
部の例えば横方向の電界強度分布が不均一となり、ドレ
イン4の端部付近で電界強度が強調されて最大となり、
降伏現象が発生して、ソース−ドレイン間に電流が流れ
てしまうという問題がある。
That is, in the portion of the drain 4 close to the channel or in the low impurity concentration region, particularly in the channel region,
When the interface state is generated non-uniformly, when a high voltage of several hundred volts is applied between the source 3 and the drain 4, for example, the electric field intensity distribution in the horizontal direction becomes non-uniform, and the end of the drain 4 In the vicinity, the electric field intensity is emphasized and becomes maximum,
There is a problem that a breakdown phenomenon occurs and current flows between the source and the drain.

【0008】このような界面準位8に伴う降伏現象は、
通常の低電圧駆動のMOS型トランジスタでは問題にな
る場合は少ないが、高耐圧デバイスでは重要な問題とな
り、トランジスタがオフ状態の時に特に問題とされるも
のである。本発明は前記問題点を解決し、界面準位を制
御してソース−ドレイン間の降伏現象を減少させる高耐
圧半導体装置およびその製造方法を提供することを目的
とする。
The breakdown phenomenon associated with the interface state 8 is as follows.
This is rarely a problem with a normal low-voltage-drive MOS transistor, but it is a significant problem with a high-breakdown-voltage device, particularly when the transistor is off. SUMMARY OF THE INVENTION It is an object of the present invention to provide a high-breakdown-voltage semiconductor device which solves the above-mentioned problems and controls the interface state to reduce a source-drain breakdown phenomenon, and a method of manufacturing the same.

【0009】[0009]

【課題を解決するための手段】本発明の高耐圧半導体装
置は、半導体基板の表面を覆う保護膜の成分を制御した
したことを特徴とする。この本発明によると、界面準位
に起因する固有の問題を解決することができる。
A high breakdown voltage semiconductor device according to the present invention is characterized in that components of a protective film covering the surface of a semiconductor substrate are controlled. According to the present invention, it is possible to solve an inherent problem caused by an interface state.

【0010】また、本発明の高耐圧半導体装置の製造方
法は、保護膜の製造工程を特殊にしたことを特徴とす
る。この本発明によると、チャンネル領域界面などにお
ける電界バランスのくずれの頻度が減少し、降伏減少が
発生しにくくなる。
Further, a method of manufacturing a high withstand voltage semiconductor device according to the present invention is characterized in that a manufacturing process of a protective film is special. According to the present invention, the frequency of disruption of the electric field balance at the interface of the channel region or the like is reduced, and the breakdown is less likely to occur.

【0011】[0011]

【発明の実施の形態】請求項1記載の高耐圧半導体装置
は、半導体基板に形成された半導体素子の上に、Siと
Nの原子数の比(Si/N)が0.7より小さい保護膜
を形成したことを特徴とする。請求項2記載の高耐圧半
導体装置は、請求項1において、半導体基板に形成され
た半導体素子の上に、SiとNの原子数の比(Si/
N)が0.6以下の保護膜を形成したことを特徴とす
る。
According to a first aspect of the present invention, there is provided a high withstand voltage semiconductor device comprising a semiconductor element formed on a semiconductor substrate and having a ratio of the number of atoms of Si to N (Si / N) smaller than 0.7. A film is formed. According to a second aspect of the present invention, there is provided a high breakdown voltage semiconductor device according to the first aspect, wherein a ratio of the number of atoms of Si and N (Si / N) is provided on the semiconductor element formed on the semiconductor substrate.
N) is characterized in that a protective film having a thickness of 0.6 or less is formed.

【0012】請求項3記載の高耐圧半導体装置は、半導
体基板に形成された半導体素子の上に、2.5×1022
atoms/cm3以上の水素を含有するシリコンナイドライド
膜を保護膜として形成したことを特徴とする。請求項4
記載の高耐圧半導体装置はl導体基板に形成された半導
体素子の上に形成され、SiとNの原子数の比(Si/
N)が0.7より小さい第1の保護膜と、第1の保護膜
の上に形成されSiとNの原子数の比(Si/N)が
0.7程度の第2の保護膜とを設けたことを特徴とす
る。
[0012] High voltage semiconductor device according to claim 3 includes, on a semiconductor device formed on a semiconductor substrate, 2.5 × 10 22
A silicon hydride film containing hydrogen of atoms / cm 3 or more is formed as a protective film. Claim 4
The described high breakdown voltage semiconductor device is formed on a semiconductor element formed on an l-conductor substrate, and has a ratio of the number of atoms of Si and N (Si / N).
N) a first protective film having a value smaller than 0.7, and a second protective film formed on the first protective film and having a ratio of the number of atoms of Si and N (Si / N) of about 0.7. Is provided.

【0013】請求項5記載の高耐圧半導体装置の製造方
法は、半導体基板に形成された半導体素子の上に保護膜
を形成するに際して、水素を7%以上含有した不活性ガ
ス中で前記半導体基板を熱処理して界面準位の密度を減
少させ、前記熱処理後の半導体素子の上に保護膜を形成
することを特徴とする。請求項6記載の高耐圧半導体装
置の製造方法は、半導体基板に形成された半導体素子の
上に、SiとNの原子数の比(Si/N)を0.7より
小さくして2.5×1022atoms/cm3以上の水素を含有
するシリコンナイドライド膜を含む保護膜を形成するこ
とを特徴とする。
A method of manufacturing a high-breakdown-voltage semiconductor device according to claim 5, wherein the semiconductor substrate is formed in an inert gas containing at least 7% of hydrogen when a protective film is formed on a semiconductor element formed on the semiconductor substrate. Is subjected to heat treatment to reduce the density of interface states, and a protective film is formed on the semiconductor element after the heat treatment. The method of manufacturing a high withstand voltage semiconductor device according to claim 6, wherein the ratio of the number of atoms of Si and N (Si / N) is smaller than 0.7 on the semiconductor element formed on the semiconductor substrate. A protection film including a silicon hydride film containing hydrogen of × 10 22 atoms / cm 3 or more is formed.

【0014】請求項7記載の高耐圧半導体装置の製造方
法は、半導体基板に形成された半導体素子の上に保護膜
を形成するに際して、水素を7%以上含有した不活性ガ
ス中で前記半導体基板を熱処理して界面準位の密度を減
少させ、モノシランガスとアンモニアガスの比を調整し
ながら前記熱処理した半導体基板の上に2.5×10 22
atoms/cm3以上の水素を含有するシリコンナイドライド
膜を含む保護膜を形成することを特徴とする。
A method of manufacturing a high withstand voltage semiconductor device according to claim 7.
The method uses a protective film on a semiconductor element formed on a semiconductor substrate.
When forming an inert gas containing 7% or more hydrogen
Heat treatment of the semiconductor substrate in the
And adjust the ratio of monosilane gas to ammonia gas.
2.5 × 10 on the heat-treated semiconductor substrate twenty two
atoms / cmThreeSilicon hydride containing above hydrogen
A protective film including a film is formed.

【0015】請求項8記載の高耐圧半導体装置の製造方
法は、半導体基板に形成された半導体素子の上に保護膜
を形成するに際して、水素を7%以上含有した不活性ガ
ス中で前記半導体基板を熱処理して界面準位の密度を減
少させ、前記熱処理後の半導体素子の上に保護膜を形成
し、不活性ガスや水素含有ガスなどを用いて前記保護膜
に拡散のための熱処理を施すことを特徴とする。
9. The method of manufacturing a high-breakdown-voltage semiconductor device according to claim 8, wherein said semiconductor substrate is formed in an inert gas containing at least 7% of hydrogen when forming a protective film on a semiconductor element formed on the semiconductor substrate. Heat treatment to reduce the density of interface states, form a protective film on the semiconductor device after the heat treatment, and perform a heat treatment for diffusion on the protective film using an inert gas or a hydrogen-containing gas. It is characterized by the following.

【0016】請求項9記載の高耐圧半導体装置の製造方
法は、請求項5または請求項8において、300℃〜6
00℃の温度で熱処理を行うことを特徴とする。以下、
本発明の高耐圧半導体装置とその製造方法を高耐圧半導
体装置としてMOS型トランジスタを例に挙げ、具体的
な実施の形態に基づいて説明する。なお、上記従来例を
示す図3と同様をなすものについては、同一の符号を付
けて説明する。
According to a ninth aspect of the present invention, there is provided a method of manufacturing a high breakdown voltage semiconductor device according to the fifth or eighth aspect, wherein
The heat treatment is performed at a temperature of 00 ° C. Less than,
A high breakdown voltage semiconductor device and a method of manufacturing the same according to the present invention will be described based on a specific embodiment, taking a MOS transistor as an example of a high breakdown voltage semiconductor device. The same components as those shown in FIG. 3 showing the conventional example are denoted by the same reference numerals.

【0017】(実施の形態1)図1は本発明の(実施の
形態1)を示す。この(実施の形態1)では、従来のM
OS型トランジスタよりも界面準位8に伴なう降伏現象
を抑えるために、半導体基板10に形成された半導体素
子の上に保護膜7を形成する前に、半導体基板10に熱
処理を施した点で異なるが、それ以外の基本的な構成は
上記従来例を示す図3と同様である。
(Embodiment 1) FIG. 1 shows (Embodiment 1) of the present invention. In this (Embodiment 1), the conventional M
In order to suppress the breakdown phenomenon accompanying the interface level 8 more than the OS type transistor, the semiconductor substrate 10 is subjected to a heat treatment before the protective film 7 is formed on the semiconductor element formed on the semiconductor substrate 10. However, the other basic configuration is the same as that of FIG. 3 showing the above conventional example.

【0018】以下にその具体例を示す。図1(a)に示
すように、シリコン基板10の表面にゲート酸化膜1を
約40nm形成し、その上に不純物を含むシリコン膜か
らなる約3μmのゲート長のゲート電極2を形成した。
このゲート酸化膜1およびゲート電極2をマスクとして
イオン注入を行い、図1(b)に示すように、完成時に
約3μmの接合深さとなるソース3、ドレイン4の領域
を形成した。
A specific example will be described below. As shown in FIG. 1A, a gate oxide film 1 having a thickness of about 40 nm was formed on the surface of a silicon substrate 10, and a gate electrode 2 made of a silicon film containing impurities and having a gate length of about 3 μm was formed thereon.
Using the gate oxide film 1 and the gate electrode 2 as a mask, ion implantation was performed to form a source 3 and a drain 4 having a junction depth of about 3 μm upon completion, as shown in FIG.

【0019】次いで、図1(c)に示すように、層間絶
縁膜5であるシリコン酸化膜を熱CVD法やプラズマC
VD法で約2μmの厚さに堆積し、ソース3、ドレイン
4の領域にコンタクト窓を開口した後、図1(d)に示
すように、Al/Si/Cuからなるアルミニウムを主
成分とする合金の金属電極6をパターン形成した。そし
て図1(e)では、この(実施の形態1)に特徴的な工
程である熱処理を、水素を7%以上含む窒素雰囲気下で
約400℃の温度で30分間実施した。
Next, as shown in FIG. 1C, a silicon oxide film as the interlayer insulating film 5 is formed by thermal CVD or plasma CVD.
After being deposited to a thickness of about 2 μm by a VD method and opening contact windows in the regions of the source 3 and the drain 4, as shown in FIG. An alloy metal electrode 6 was patterned. In FIG. 1E, a heat treatment, which is a characteristic step of the first embodiment, was performed at a temperature of about 400 ° C. for 30 minutes in a nitrogen atmosphere containing 7% or more of hydrogen.

【0020】なお、ここでは熱処理温度を約400℃と
したが、必要に応じて300℃〜600℃を使用するこ
とができる。この温度範囲は主として金属電極6のコン
タクト界面の熱的安定性によって決まり、金属電極6と
ソース3あるいはドレイン4との界面に熱的に安定なバ
リヤメタルなどが形成されるときは600℃近い熱処理
が可能となる。
Although the heat treatment temperature is set to about 400 ° C. here, 300 ° C. to 600 ° C. can be used if necessary. This temperature range is mainly determined by the thermal stability of the contact interface of the metal electrode 6, and when a thermally stable barrier metal or the like is formed at the interface between the metal electrode 6 and the source 3 or the drain 4, a heat treatment close to 600 ° C. It becomes possible.

【0021】最後に、図1(f)に示すように、従来と
同様に原子数比でSi:N=3:4となるようストイキ
オメトリックなシリコンナイトライド膜を保護膜7とし
て成長させた。具体的には、モノシランとアンモニアの
ガスを流量比=1:1、成長温度を380℃、成長時間
を2分、キャリアガスに窒素を用いてプラズマCVD法
で成長させ、膜厚は800nm、屈折率は2.05の保
護膜7を形成した。なお、堆積直後のナイトライド膜に
含まれる水素量は1.5×1022atoms/cm3であった。
Finally, as shown in FIG. 1F, a stoichiometric silicon nitride film was grown as the protective film 7 so that the atomic ratio was Si: N = 3: 4 as in the conventional case. . Specifically, monosilane and ammonia gas are grown by plasma CVD using a flow rate ratio of 1: 1, a growth temperature of 380 ° C., a growth time of 2 minutes, and nitrogen as a carrier gas. The protective film 7 having a rate of 2.05 was formed. The amount of hydrogen contained in the nitride film immediately after the deposition was 1.5 × 10 22 atoms / cm 3 .

【0022】このように、保護膜7を形成する前に水素
を含む雰囲気下で熱処理を行うことで、約400℃とい
う比較的低温であっても層間絶縁膜5の中を水素が容易
に拡散していき、ソース3、ドレイン4、シリコン基板
10の界面に到達することができる。その結果、図1
(e)で存在する界面準位8が補修され、界面準位8が
有していた電荷が消滅して、図1(f)に示すように、
界面準位8の密度を減少させることができる。
As described above, by performing the heat treatment in an atmosphere containing hydrogen before forming the protective film 7, the hydrogen easily diffuses into the interlayer insulating film 5 even at a relatively low temperature of about 400 ° C. Then, it can reach the interface between the source 3, the drain 4, and the silicon substrate 10. As a result, FIG.
The interface state 8 existing in (e) is repaired, and the electric charge of the interface state 8 disappears, and as shown in FIG.
The density of the interface states 8 can be reduced.

【0023】得られたMOS型トランジスタは、チャン
ネル領域界面などにおける電界バランスのくずれの頻度
が減少し、降伏現象が発生しにくいものであった。この
MOS型トランジスタのソース3,ドレイン4間に、動
作時とは逆方向に600ボルトの電圧を印加して、ゲー
トの0ボルト印加またはオープン状態、基板電位0ボル
トというバイアス条件下で、ソース3,ドレイン4の間
に電流リークに関する試験を実施した結果、歩留まりは
従来よりも18%上昇した。
In the obtained MOS transistor, the frequency of the electric field balance at the interface of the channel region and the like is reduced, and the breakdown phenomenon is less likely to occur. A voltage of 600 volts is applied between the source 3 and the drain 4 of the MOS transistor in a direction opposite to the operation, and the source 3 is applied under a bias condition of applying 0 volt to the gate or in an open state and the substrate potential of 0 volt. As a result of a test on current leakage between the drain 4 and the drain 4, the yield was increased by 18% as compared with the conventional case.

【0024】なお、この(実施の形態1)では、図1
(e)の熱処理を水素を7%以上含有する窒素雰囲気下
で行ったが、本発明はこれに限定されるものではなく、
水素を7%以上含有した不活性ガス中で熱処理を行うも
のであればよい。また、不活性ガス中の水素濃度は製造
条件が許す限り高い方が好ましく、不活性ガス中に約5
0%以上の水素を含有することが望ましい。
In this (Embodiment 1), FIG.
The heat treatment (e) was performed in a nitrogen atmosphere containing 7% or more of hydrogen, but the present invention is not limited to this.
Any material may be used as long as heat treatment is performed in an inert gas containing 7% or more of hydrogen. Further, it is preferable that the hydrogen concentration in the inert gas is as high as the production conditions permit.
It is desirable to contain 0% or more of hydrogen.

【0025】また、上記(実施の形態1)において、保
護膜7を形成する前の熱処理では、層間絶縁膜5に入っ
た水素がソース3、ドレイン4、シリコン基板10の界
面に到達するまで十分に熱処理を行ったが、水素雰囲気
下での熱処理を水素が層間絶縁膜5に含まれる程度に行
い、保護膜7としてのシリコンナイトライド膜を形成し
た後、不活性ガスや水素含有ガス等を用いて再度の熱処
理を行い、層間絶縁膜5中の水素を前記界面に到達させ
てもよい。
Also, in the above (Embodiment 1), in the heat treatment before forming the protective film 7, it is sufficient that hydrogen entering the interlayer insulating film 5 reaches the interface between the source 3, the drain 4 and the silicon substrate 10. After performing heat treatment in a hydrogen atmosphere to the extent that hydrogen is contained in the interlayer insulating film 5 and forming a silicon nitride film as the protective film 7, an inert gas, a hydrogen-containing gas, or the like is removed. The heat treatment may be performed again to cause hydrogen in the interlayer insulating film 5 to reach the interface.

【0026】(実施の形態2)図2は(実施の形態2)
を示し、保護膜7aの製造工程の手順は上記従来例を示
す図3と同じであるが、保護膜7aの成分構成が従来例
での保護膜7とは異なっている。半導体基板10に形成
された半導体素子の上に保護膜7aを形成するに際し
て、この(実施の形態2)の場合には、図3(e)にお
いて従来のキャリアガスである窒素に代わって、不活性
ガスであるモノシランとアンモニアガスを用いる。
(Embodiment 2) FIG. 2 shows (Embodiment 2)
The manufacturing procedure of the protective film 7a is the same as that of FIG. 3 showing the conventional example, but the component configuration of the protective film 7a is different from that of the protective film 7 in the conventional example. When forming the protective film 7a on the semiconductor element formed on the semiconductor substrate 10, in the case of this (Embodiment 2), instead of nitrogen as a conventional carrier gas in FIG. Monosilane and ammonia gas, which are active gases, are used.

【0027】そして、保護膜7a中のSiとNの原子数
の比(Si/N)が0.7よりも小さくなるようにモノ
シランとアンモニアガスの比を調整して、2.5×10
22atoms/cm3以上の水素を含有するシリコンナイドライ
ド膜を保護膜7aとして形成する。このような保護膜7
aを設けると、比較的低温の状態で水素9が容易に層間
絶縁膜5中を拡散していき、ソース3、ドレイン4、シ
リコン基板10の界面に到達して、そこに存在する界面
準位を補修するため、界面準位8の密度を減少させるこ
とができる。
Then, the ratio between monosilane and ammonia gas is adjusted so that the ratio of the number of atoms of Si and N in the protective film 7a (Si / N) becomes smaller than 0.7, and
A silicon hydride film containing hydrogen of 22 atoms / cm 3 or more is formed as a protective film 7a. Such a protective film 7
When a is provided, hydrogen 9 easily diffuses in the interlayer insulating film 5 at a relatively low temperature, reaches the interface between the source 3, the drain 4, and the silicon substrate 10, and the interface state existing there. Is repaired, the density of the interface states 8 can be reduced.

【0028】具体的には、保護膜7aを形成するに際
し、キャリアガスとしてモノシランとアンモニアのガス
を用い、その流量比を調整してモノシラン:アンモニア
=1:8とアンモニアガスの割合を高くして、成長温度
を380℃、成長時間を1.5分とし、さらにキャリア
ガスに窒素を用いて所定の膜厚になるまでプラズマCV
D法で成長させた。
Specifically, when forming the protective film 7a, a gas of monosilane and ammonia is used as a carrier gas, and the flow ratio is adjusted to increase the ratio of monosilane: ammonia = 1: 8 to ammonia gas. The growth temperature is set to 380 ° C., the growth time is set to 1.5 minutes, and the plasma CV is further increased to a predetermined thickness by using nitrogen as a carrier gas.
Grown by method D.

【0029】得られた保護膜7aは、原子数比でSi:
N=6:10(Si/N=0.6)と窒素リッチになっ
た構成を有する膜となり、膜厚800nmの条件で形成
すると自動的に屈折率は1.8となった。また、堆積直
後のナイトライド膜に含まれる水素量は3.0×1022
atoms/cm3であった。これに対し、図3に示した従来の
製造方法で形成されたストイキオメトリックな組成の保
護膜7であるシリコンナイトライド膜は、屈折率が2.
05、堆積直後の膜に含まれる水素量が1.5×1022
atoms/cm3であった。
The obtained protective film 7a has an atomic ratio of Si:
A film having a nitrogen-rich structure with N = 6: 10 (Si / N = 0.6) was obtained. When the film was formed under the condition of a film thickness of 800 nm, the refractive index automatically became 1.8. The amount of hydrogen contained in the nitride film immediately after the deposition was 3.0 × 10 22
atoms / cm 3 . In contrast, the silicon nitride film, which is the protective film 7 having the stoichiometric composition formed by the conventional manufacturing method shown in FIG.
05, the amount of hydrogen contained in the film immediately after deposition is 1.5 × 10 22
atoms / cm 3 .

【0030】このように、キャリアガスの組成を調整す
ることで、従来よりも保護膜7aの水素含有量を多くす
ることができる。窒素リッチシリコンナイトライド膜の
原子構成の比(Si/N)は、0.7よりも小さければ
小さいほど含有する水素量が大きくなるので好ましく、
より望ましくはSiとNの原子数の比(Si/N)が
0.6以下とすることが好ましい。
Thus, by adjusting the composition of the carrier gas, the hydrogen content of the protective film 7a can be increased as compared with the conventional case. It is preferable that the atomic composition ratio (Si / N) of the nitrogen-rich silicon nitride film be smaller than 0.7 because the contained hydrogen amount becomes larger.
More preferably, the ratio of the number of atoms of Si and N (Si / N) is preferably 0.6 or less.

【0031】以上のように、保護膜7aとして水素を多
く含むシリコンナイトライド膜を形成すると、ナイトラ
イド膜形成中の約380℃という温度で水素9が容易に
層間絶縁膜5中を拡散していき、ソース3、ドレイン
4、シリコン基板10の界面に到達し、そこに存在する
界面準位を補修することによって、界面準位8の密度を
減少させることができる。
As described above, when a silicon nitride film containing a large amount of hydrogen is formed as the protective film 7a, hydrogen 9 easily diffuses in the interlayer insulating film 5 at a temperature of about 380 ° C. during the formation of the nitride film. The density of the interface state 8 can be reduced by reaching the interface between the source 3, the drain 4, and the silicon substrate 10 and repairing the interface state existing there.

【0032】この窒素リッチのシリコンナイトライド膜
を、耐圧600ボルトのパワーMOS型トランジスタに
適用し、トランジスタのソース・ドレイン間に、動作時
とは逆方向に600ボルトの電圧を印加し、ゲート電圧
を0ボルトまたはオープン状態、基板電圧を0ボルトと
して検査すると、ソース・ドレイン間リーク電流に関す
る歩留まりは、従来のトランジスタよりも15%上昇し
た。
This nitrogen-rich silicon nitride film is applied to a power MOS transistor having a withstand voltage of 600 volts, and a voltage of 600 volts is applied between the source and the drain of the transistor in a direction opposite to that of the operation, and a gate voltage is applied. Is 0 volts or an open state and the substrate voltage is 0 volts, the yield related to the source-drain leakage current is increased by 15% as compared with the conventional transistor.

【0033】なお、この(実施の形態2)では、含有水
素量が3.0×1022atoms/cm3の膜を採用したが、実
質的に2.5×1022atoms/cm3以上の水素含有量があ
れば界面準位を減少させる効果がある。また、保護膜7
は窒素リッチシリコンナイトライド膜の1層構造とした
が、もしこの膜の耐湿性、耐アルカリイオン性が充分な
ものでなければ、まず窒素リッチシリコンナイトライド
膜上を従来のストイキオメトリックなシリコンナイトラ
イド膜で覆った2層構造の保護膜としてもよい。
[0033] In this Embodiment 2, although the hydrogen content has adopted a film of 3.0 × 10 22 atoms / cm 3 , substantially 2.5 × 10 22 atoms / cm 3 or more The presence of hydrogen content has the effect of reducing interface states. Also, the protective film 7
Has a one-layer structure of a nitrogen-rich silicon nitride film. If the film has insufficient moisture resistance and alkali ion resistance, first, a conventional stoichiometric silicon nitride film is formed on the nitrogen-rich silicon nitride film. The protective film may have a two-layer structure covered with a nitride film.

【0034】すなわち、SiとNの原子数の比(Si/
N)が0.7より小さい第1の保護膜と、第1の保護膜
の上に形成されSiとNの原子数の比(Si/N)が
0.7程度の第2の保護膜とを設けた2層構造の保護膜
としてもよい。このような構成によっても、第2の保護
膜により耐湿性、耐アルカリイオン性が向上するため、
MOSトランジスタの信頼性を一層高めることができ
る。
That is, the ratio of the number of atoms of Si and N (Si /
N) a first protective film having a smaller value than 0.7, and a second protective film formed on the first protective film and having a ratio of the number of atoms of Si to N (Si / N) of about 0.7. May be used as a protective film having a two-layer structure. Even with such a configuration, moisture resistance and alkali ion resistance are improved by the second protective film.
The reliability of the MOS transistor can be further improved.

【0035】(実施の形態3)上記(実施の形態1)で
は、保護膜7を形成する前に半導体基板10に熱処理を
施して上記従来例と同様の構成を有する保護膜7を形成
したが、この(実施の形態3)では、上記(実施の形態
1)での熱処理を施した後、上記(実施の形態2)と同
様の組成を有する保護膜7を形成する。
(Embodiment 3) In the above (Embodiment 1), before forming the protective film 7, the semiconductor substrate 10 is subjected to a heat treatment to form the protective film 7 having the same configuration as that of the conventional example. In this (Embodiment 3), after performing the heat treatment in the above (Embodiment 1), a protective film 7 having the same composition as the above (Embodiment 2) is formed.

【0036】すなわち、半導体基板10に形成された半
導体素子の上に保護膜7を形成するに際して、水素を7
%以上含有した不活性ガス中で半導体基板10を熱処理
して界面準位の密度を減少させ、その後、モノシランガ
スとアンモニアガスの比を調整しながら熱処理した半導
体基板の上に2.5×1022atoms/cm3以上の水素を含
有するシリコンナイドライド膜を含む保護膜7を形成す
る。
That is, when forming the protective film 7 on the semiconductor element formed on the semiconductor substrate 10, hydrogen is
% Or more in an inert gas containing by heat-treating the semiconductor substrate 10 to reduce the density of interface states, then, monosilane gas and ammonia gas 2.5 × 10 on a semiconductor substrate having a specific heat-treated while adjusting the 22 A protection film 7 including a silicon hydride film containing hydrogen of atoms / cm 3 or more is formed.

【0037】このような構成とすると、界面準位を制御
してソース−ドレイン間の降伏現象を減少でき、チャン
ネル領域における電界バランスのくずれの頻度を少なく
し、より一層の品質改善が実現できる。なお上記各実施
の形態の説明においてはパワーMOSトランジスタの例
をあげたが、本発明はこれに限定されるものではなく、
バイポーラトランジスタ、サイリスタ、絶縁ゲートバイ
ポーラトランジスタなどの他の素子においても、界面準
位に起因する固有の問題を解決することができる。
With such a configuration, it is possible to reduce the breakdown phenomenon between the source and the drain by controlling the interface state, reduce the frequency of the electric field balance in the channel region, and further improve the quality. In the description of the above embodiments, an example of a power MOS transistor has been described, but the present invention is not limited to this.
In other elements such as a bipolar transistor, a thyristor, and an insulated gate bipolar transistor, a problem inherent to an interface state can be solved.

【0038】[0038]

【発明の効果】以上のように本発明の高耐圧半導体装置
によると、半導体基板に形成された半導体素子の上に、
SiとNの原子数の比(Si/N)が0.7より小さ
く、2.5×1022atoms/cm3以上の水素を含有するシ
リコンナイドライド膜を保護膜として形成したことで、
界面での電界バランスの崩れる頻度が減少して降伏現象
を減らすことができる。
As described above, according to the high breakdown voltage semiconductor device of the present invention, the semiconductor device formed on the semiconductor substrate is
By forming a silicon hydride film having a ratio of the number of atoms of Si and N (Si / N) smaller than 0.7 and containing hydrogen of 2.5 × 10 22 atoms / cm 3 or more as a protective film,
The frequency at which the electric field balance at the interface is lost is reduced, so that the breakdown phenomenon can be reduced.

【0039】また、本発明の高耐圧半導体装置の製造方
法によると、水素を7%以上含有した不活性ガス中で前
記半導体基板を熱処理して界面準位の密度を減少させ、
前記熱処理後の半導体素子の上に保護膜を形成すること
で、保護膜あるいは水素雰囲気中から供給される水素に
よりシリコン基板と層間絶縁膜界面に形成される界面準
位を減少させ、界面での電界バランスのくずれる頻度が
少ない高耐圧半導体素子を容易に実現できる。
Further, according to the method of manufacturing a high breakdown voltage semiconductor device of the present invention, the density of interface states is reduced by heat-treating the semiconductor substrate in an inert gas containing 7% or more of hydrogen.
By forming a protective film on the semiconductor element after the heat treatment, hydrogen supplied from the protective film or the hydrogen atmosphere reduces an interface state formed at the interface between the silicon substrate and the interlayer insulating film, It is possible to easily realize a high withstand voltage semiconductor element in which the electric field balance is less frequently broken.

【0040】その結果、逆方向耐圧とした数百ボルトを
有する高耐圧半導体装置において、半導体基板表面に存
在する界面準位による耐圧の低下、耐圧変動が少ない半
導体装置の製造が可能となる。
As a result, in a high withstand voltage semiconductor device having a reverse breakdown voltage of several hundred volts, it is possible to manufacture a semiconductor device in which the withstand voltage is reduced and the withstand voltage fluctuation is small due to the interface state existing on the semiconductor substrate surface.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(実施の形態1)における高耐圧MOSトラン
ジスタの製造工程を示す図
FIG. 1 is a view showing a manufacturing process of a high breakdown voltage MOS transistor in (Embodiment 1);

【図2】(実施の形態1)における高耐圧MOSトラン
ジスタの断面図
FIG. 2 is a cross-sectional view of a high-breakdown-voltage MOS transistor according to Embodiment 1;

【図3】従来の高耐圧MOSトランジスタの製造工程を
示す図
FIG. 3 is a diagram showing a manufacturing process of a conventional high breakdown voltage MOS transistor.

【符号の説明】[Explanation of symbols]

1 ゲート酸化膜 2 ゲート電極 3 ソース 4 ドレイン 5 層間絶縁膜 6 金属電極 7a 保護膜 8 界面準位 9 水素 10 シリコン基板 DESCRIPTION OF SYMBOLS 1 Gate oxide film 2 Gate electrode 3 Source 4 Drain 5 Interlayer insulating film 6 Metal electrode 7a Protective film 8 Interface state 9 Hydrogen 10 Silicon substrate

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5F005 AH04 BB02 5F040 DA00 DA21 DC01 EB14 EB18 EL02 FC00 5F058 BA01 BD10 BF07 BF23 BF30 BJ01 BJ03  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F005 AH04 BB02 5F040 DA00 DA21 DC01 EB14 EB18 EL02 FC00 5F058 BA01 BD10 BF07 BF23 BF30 BJ01 BJ03

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】半導体基板に形成された半導体素子の上
に、SiとNの原子数の比(Si/N)が0.7より小
さい保護膜を形成した高耐圧半導体装置。
1. A high breakdown voltage semiconductor device in which a protective film having a ratio of the number of atoms of Si and N (Si / N) smaller than 0.7 is formed on a semiconductor element formed on a semiconductor substrate.
【請求項2】半導体基板に形成された半導体素子の上
に、SiとNの原子数の比(Si/N)が0.6以下の
保護膜を形成した請求項1記載の高耐圧半導体装置。
2. The high breakdown voltage semiconductor device according to claim 1, wherein a protective film having an atomic ratio of Si and N (Si / N) of 0.6 or less is formed on the semiconductor element formed on the semiconductor substrate. .
【請求項3】半導体基板に形成された半導体素子の上
に、2.5×1022atoms/cm3以上の水素を含有するシ
リコンナイドライド膜を保護膜として形成した高耐圧半
導体装置。
3. A high breakdown voltage semiconductor device in which a silicon hydride film containing at least 2.5 × 10 22 atoms / cm 3 of hydrogen is formed as a protective film on a semiconductor element formed on a semiconductor substrate.
【請求項4】半導体基板に形成された半導体素子の上に
形成され、SiとNの原子数の比(Si/N)が0.7
より小さい第1の保護膜と、 第1の保護膜の上に形成されSiとNの原子数の比(S
i/N)が0.7程度の第2の保護膜とを設けた高耐圧
半導体装置。
4. A semiconductor device formed on a semiconductor substrate and having a ratio of the number of atoms of Si and N (Si / N) of 0.7
A smaller first protective film, and a ratio of the number of atoms of Si and N formed on the first protective film (S
A high withstand voltage semiconductor device provided with a second protective film having a ratio (i / N) of about 0.7.
【請求項5】半導体基板に形成された半導体素子の上に
保護膜を形成するに際して、 水素を7%以上含有した不活性ガス中で前記半導体基板
を熱処理して界面準位の密度を減少させ、 前記熱処理後の半導体素子の上に保護膜を形成する高耐
圧半導体装置の製造方法。
5. When forming a protective film on a semiconductor element formed on a semiconductor substrate, the semiconductor substrate is heat-treated in an inert gas containing 7% or more of hydrogen to reduce the density of interface states. A method for manufacturing a high breakdown voltage semiconductor device, wherein a protective film is formed on a semiconductor element after the heat treatment.
【請求項6】半導体基板に形成された半導体素子の上
に、SiとNの原子数の比(Si/N)を0.7より小
さくして2.5×1022atoms/cm3以上の水素を含有す
るシリコンナイドライド膜を含む保護膜を形成する高耐
圧半導体装置の製造方法。
6. A semiconductor device formed on a semiconductor substrate, wherein a ratio of the number of atoms of Si and N (Si / N) is smaller than 0.7 and is not less than 2.5 × 10 22 atoms / cm 3 . A method for manufacturing a high-breakdown-voltage semiconductor device in which a protective film including a silicon hydride film containing hydrogen is formed.
【請求項7】半導体基板に形成された半導体素子の上に
保護膜を形成するに際して、 水素を7%以上含有した不活性ガス中で前記半導体基板
を熱処理して界面準位の密度を減少させ、 モノシランガスとアンモニアガスの比を調整しながら前
記熱処理した半導体基板の上に2.5×1022atoms/c
m3以上の水素を含有するシリコンナイドライド膜を含む
保護膜を形成する高耐圧半導体装置の製造方法。
7. When forming a protective film on a semiconductor element formed on a semiconductor substrate, the semiconductor substrate is heat-treated in an inert gas containing at least 7% of hydrogen to reduce the density of interface states. 2.5 × 10 22 atoms / c on the heat-treated semiconductor substrate while adjusting the ratio of monosilane gas to ammonia gas.
A method for manufacturing a high withstand voltage semiconductor device for forming a protective film including a silicon hydride film containing hydrogen of m 3 or more.
【請求項8】半導体基板に形成された半導体素子の上に
保護膜を形成するに際して、 水素を7%以上含有した不活性ガス中で前記半導体基板
を熱処理して、 前記熱処理後の半導体素子の上に保護膜を形成し、 不活性ガスや水素含有ガスなどを用いて前記保護膜に拡
散のための熱処理を施す高耐圧半導体装置の製造方法。
8. When forming a protective film on a semiconductor element formed on a semiconductor substrate, the semiconductor substrate is heat-treated in an inert gas containing 7% or more of hydrogen. A method for manufacturing a high breakdown voltage semiconductor device, wherein a protective film is formed thereon, and a heat treatment for diffusion is performed on the protective film using an inert gas or a hydrogen-containing gas.
【請求項9】300℃〜600℃の温度で熱処理を行う
請求項5または請求項8記載の高耐圧半導体装置の製造
方法。
9. The method according to claim 5, wherein the heat treatment is performed at a temperature of 300 ° C. to 600 ° C.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7372113B2 (en) 2002-05-29 2008-05-13 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same

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JPH05166802A (en) * 1991-12-13 1993-07-02 Ricoh Co Ltd Semiconductor device
JPH0774167A (en) * 1993-06-30 1995-03-17 Kawasaki Steel Corp Manufacture of semiconductor device
JPH07235615A (en) * 1993-12-31 1995-09-05 Ricoh Co Ltd Manufacture of semiconductor device with plsma-silicon nitride film

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05166802A (en) * 1991-12-13 1993-07-02 Ricoh Co Ltd Semiconductor device
JPH0774167A (en) * 1993-06-30 1995-03-17 Kawasaki Steel Corp Manufacture of semiconductor device
JPH07235615A (en) * 1993-12-31 1995-09-05 Ricoh Co Ltd Manufacture of semiconductor device with plsma-silicon nitride film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7372113B2 (en) 2002-05-29 2008-05-13 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same

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