JP2000349013A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance accuracy in alignment between a gate electrode and a recess, in the formation of a semiconductor device with a recess concurrently using an EB lithography and a photolithography. SOLUTION: An EB mark 109a and a recess 110a are made at the same time, by a (second) photolithography using one time of photoresist film pattern 122a. Since the EB mark 109a, the recess, the openings for formation of the EB mark and the recess, or the opening for formation of the EB mark, and the recess are made at the same time by one time photolithography, the accuracy in alignment between the recess and the gate electrode becomes equal to the accuracy of alignment of on time of EB lithography. As a result, a compound semiconductor device superior in high-speed operation property can be manufactured easily.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a compound semiconductor device having a recess formed by using photolithography and EB lithography.

[0002]

2. Description of the Related Art A compound semiconductor device having a recess and a gate electrode is first formed, for example, by a single EB lithography to form a recess, and furthermore, to form an E used for this.
The gate electrode is formed by lift-off using the B register film pattern. However, recently, with the demand for a preferable setting position of the gate electrode and the progress of the photolithography technology, a recess is formed by photolithography, and the gate electrode is formed by EB lithography.

Referring to FIG. 12, which is a schematic sectional view of a manufacturing process of a compound semiconductor device, photolithography and EB
An example of a recent method for manufacturing a compound semiconductor device using lithography is as follows.

First, on a surface of a semi-insulating GaAs substrate 401, a GaAs layer 402 having a thickness of, for example, about 200 nm, an n-type AlGaAs layer 403 having a thickness of, for example, about 5 nm, and a 150 nm, for example, are formed by epitaxial growth.
An n-type GaAs layer 404 having a film thickness of about the same is formed. G
A first layer for photolithography is formed on the surface of the
Is formed. Using the photoresist film pattern 421 as a mask, the GaAs layer 404 is anisotropically etched,
An alignment mark 407 for photolithography having a depth of about 00 nm is formed.
(A)].

Next, the photoresist film pattern 42
1 is removed. Subsequently, the alignment mark 40
7, a second photoresist film pattern 422 is formed on the surface of the GaAs layer 404. Using the photoresist film pattern 422 as a mask, the GaAs layer 4 is etched with an etching gas containing at least fluorine (F).
04 is selectively etched to form a recess 410. The opening width of the recess 410 is, for example, about 0.7 μm, and the opening length (gate width) is, for example, about 100 μm (FIG. 12B).

[0006] The photoresist film pattern 422 is removed, and a third photoresist film pattern 424 using the alignment mark 407 is formed on the surface of the GaAs layer 404. Thereafter, a conductive film 433 is formed on the entire surface [FIG. 12 (c)].

The photoresist film pattern 424 is lifted off, and a second alignment mark (composed of a conductor film 433) for EB lithography (EB mark) 409 is formed on the surface of the GaAs layer 404. Subsequently, GaAs is formed using the alignment mark 407.
A fourth photoresist film pattern 423 is formed on the surface of the s layer 404, and the ohmic metal 4
11 is formed (FIG. 12D).

The photoresist film pattern 423 is lifted off, and a source electrode 412 (consisting of a conductor film 411) and a drain electrode 413 are formed on the surface of the GaAs layer 404 (FIG. 12E).

The order of forming the EB mark 409 (using the third photoresist film pattern 424) and forming the source electrode 412 and the drain electrode 413 (using the fourth photoresist film pattern 423). May be reversed. Further, the formation of the EB mark 409 and the formation of the source electrode 412 and the drain electrode 413 may be performed simultaneously by one photolithography.

[0010] Thereafter, Ga is utilized by using the EB mark 409.
An EB resist film pattern 425 is formed on the surface of the As layer 404.
Is formed, and a gate metal 414 is formed on the entire surface [FIG. 12 (f)]. The EB resist film pattern 425 is lifted off, a gate electrode 415 (made of the gate metal 414) is formed in the recess, and the formation of the compound semiconductor device is completed. The gate length (corresponding to the line width of the gate electrode 415) is, for example, 0.18 μm. In order to obtain a high-speed operation characteristic in this compound semiconductor device, the gate electrode 412 is not located at the center of the recess 410 (for example, about 0.1 μm from the center of the recess 410 to the source side). (FIG. 12 (g)).

[0011]

In the above-described conventional method for manufacturing a compound semiconductor device described with reference to FIG.
For example, for photolithography exposure (wavelength 365 nm
When the i-line is used, the alignment accuracy in one photolithography is, for example, about 0.1 μm.
The alignment accuracy of EB lithography is, for example, about 0.05 μm.

In the above-described manufacturing method, the alignment accuracy between the recess and the gate electrode is two times by photolithography and one time.
EB lithography is required, so ((0.1
μm) ² + (0.1 μm) ² + (0.05 μm) ² )
^1/2 = 0.15 μm.

Unlike the above-described manufacturing method, the alignment mark for the photoresist may be used as the EB mark in some cases. However, even in this case, the alignment accuracy between the recess and the gate electrode is two times by photolithography and one time EB
Since it requires lithography, ((0.1 μm) ²
+ (0.05 μm) ² ) ^1/2 ≒ approximately 0.11 μm.

As is apparent from the above, in the conventional method of manufacturing a semiconductor device using photolithography and EB lithography, the alignment accuracy becomes larger than the set position of the gate electrode. It becomes difficult to manufacture a compound semiconductor device having the same.

Accordingly, an object of the present invention is to provide a method of manufacturing a compound semiconductor device having high-speed operation characteristics. It is a further object of the present invention to use photolithography and E
It is an object of the present invention to provide a method for manufacturing a semiconductor device using B lithography, in which alignment accuracy between a recess and a gate electrode is improved.

[0016]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method comprising:
A first layer including at least one of Group III and Group V, a second layer including at least Group III, and a third layer including a first compound semiconductor. A laminated film is formed, and a fourth layer composed of a stopper layer is formed on the surface of the third layer, and a second compound semiconductor having a required film thickness of the same component as that of the first compound semiconductor. Forming a second stacked film composed of the fifth layer and the fifth layer and the fourth layer sequentially anisotropically etching using the first photoresist film pattern as a mask, Forming a first alignment mark (for photolithography) and a region for forming an alignment mark (for second alignment mark for EB lithography) made of the second laminated film on the surface of the first laminated film The process of At least, the third and fifth layers are selectively anisotropically etched using another photoresist film pattern covering the first alignment mark as a mask, and the second alignment is formed in the alignment mark forming region. Forming a mark (EB mark) and forming a recess in the surface of the first laminated film.

According to a second aspect of the method of manufacturing a semiconductor device of the present invention, a step of forming a layer having at least an upper surface made of a compound semiconductor on a surface or a surface of a semiconductor substrate and forming a conductor film on the entire surface Anisotropically etching the conductive film using the first photoresist film pattern as a mask, and forming a first alignment mark (for photolithography) comprising the conductive film on the surface of the semiconductor substrate; Forming a second alignment mark (for EB lithography) (for EB lithography) and simultaneously forming an opening for recess in this conductor film on the surface of the layer;
Forming a recess in the surface of the layer by etching the layer to a required depth using at least the second photoresist film pattern covering the first and second alignment marks and the opening as a mask; And

According to a third aspect of the method of manufacturing a semiconductor device of the present invention, a step of forming a layer having at least an upper surface made of a compound semiconductor on a surface or a surface of a semiconductor substrate and forming an insulating film on the entire surface; The insulating film is selectively anisotropically etched using the first photoresist film pattern as a mask, and the surface of the semiconductor substrate or the surface thereof and the layer are brought to a first predetermined depth. A first opening for forming a first alignment mark (for photolithography) and a first opening (for EB lithography) penetrating this conductor film (for EB lithography)
Forming a second opening for forming a second alignment mark on or above the surface of the semiconductor substrate, and simultaneously forming a recess in the surface of the layer; and a second photoresist covering at least the recess. Using the film pattern and the first and second openings as masks, the surface or the surface of the semiconductor substrate is further selectively anisotropically etched until a second required depth is reached. A first alignment mark and a second alignment mark on or on the surface of
Forming an alignment mark (EB mark).

[0019]

Next, the present invention will be described with reference to the drawings.

A semiconductor device to which the manufacturing method according to the first embodiment of the present invention is applied includes at least one of Group III and Group V provided on the surface of a semiconductor substrate. A) a first layer, a second layer (comprising at least Group III) and (comprising a compound semiconductor layer)
A recess (having the third layer removed) is formed on the surface of the first laminated film including the third layer, a gate electrode is formed in the recess, and a source is formed on the surface of the first laminated film. ,
This is a compound semiconductor device in which an ohmic electrode serving as a drain electrode is formed. The feature of the first embodiment resides in that a second alignment mark (EB mark) for EB lithography is formed by photolithography in which a recess is formed.

The EB mark and the first alignment mark for photolithography in the first embodiment are formed by processing the second laminated film provided on the surface of the first laminated film. Become. The second stacked film is formed of a second stacked film in which a fifth layer is stacked on a stopper layer which is a fourth layer. The fifth layer is made of a compound semiconductor layer having the same thickness as the compound semiconductor layer constituting the third layer and having a required thickness. The first alignment mark is formed of a convex-shaped portion left after the second laminated film is anisotropically etched. By photolithography in which the first alignment mark is formed, an alignment mark formation region (for an EB mark) formed of the second laminated film is formed at the same time. The EB mark is formed of a concave portion in which the fifth layer in the alignment mark forming region is selectively anisotropically etched.

In the first embodiment, the following is preferred. The semiconductor substrate includes, for example, a semi-insulating compound semiconductor substrate typified by a semi-insulating GaAs substrate, a semiconductor substrate having a high-resistance Ge layer provided on a surface of a Si substrate, and the like. The first layer is a compound semiconductor layer, I
It is composed of an n layer or an As layer. The second layer is made of, for example, a compound semiconductor layer or an Al layer, and forms a shot junction with a gate metal forming a gate electrode, and is resistant to anisotropic etching of the third (and fifth) layer. (Each) must function as a stopper. The third layer is, for example, an n-type ohmic layer, and the thickness of the third layer is, for example, about 50 nm to 150 nm. When the second layer is composed of a compound semiconductor layer, the fourth layer (stopper layer) may be composed of a compound semiconductor layer having the same component as the second layer, but is not limited thereto. Alternatively, an insulating film such as a silicon oxide film or a silicon nitride film may be used. The required thickness of the fifth layer is preferably 400 nm or more. For example, when the third and fifth layers are made of GaAs layers and the fourth layer (stopper layer) is made of a compound semiconductor layer, the fourth layer may contain Al or In as a component. preferable. Further, in this case, the thickness of the fourth layer is preferably, for example, at most about 5 nm.

Referring to FIG. 1, which is a schematic cross-sectional view of the manufacturing process of the semiconductor device, the semiconductor device according to the first example of the first embodiment is formed as follows.

First, on the surface of the semi-insulating GaAs substrate 101, a first layer (for example, undoped, for example, 2
A GaAs layer 102 (having a thickness of about 00 nm) and a second layer (for example, n-type having a thickness of about 5 nm to 10 nm)
the lGaAs layer 103 and the third layer (for example, 50
n-type GaAs layer 10 having a thickness of about 10 nm to 150 nm
4 is formed by epitaxial growth. Further, a fourth layer (for example, a 5 nm-thick n-type) AlGaAs layer 105 and a fifth layer GaAs (having a thickness of at least about 400 nm)
A second stacked film composed of the s layer 106 is formed by epitaxial growth. On the surface of the second laminated film, (first
1) A photoresist film pattern 121 is formed [FIG. 1 (a)].

Next, the GaAs layer 10 is anisotropically etched using the photoresist film pattern 121 as a mask.
6 is selectively anisotropically etched to form a GaAs layer 10.
6A and the GaAs layer 106B are left. At this time, the etching is performed using F such as BCl ₃ + SF _6.
, The AlGaAs layer 105 functions as a stopper layer because the boiling point of AlF ₃ is high. Further, the exposed AlGaAs layer 104 is etched away by anisotropic etching using, for example, BCl ₃ + Ar as an etching gas or a washing process using the photoresist film pattern 121 as a mask.
The GaAs layer 105A and the AlGaAs layer 105B are remaining formed. At this time, since the surface of the GaAs layer 103 is also slightly etched, the thickness of the AlGaAs layer 105 is preferably sufficiently small (for example, about 5 nm). As a result, A on the surface of the first laminated film
a convex (first) photolithography alignment mark 107 made of (a second laminated film of) the lGaAs layer 105A and the GaAs layer 106A, and AlGaAs
An alignment mark forming region 108 (for an EB mark) composed of the s layer 105B and the GaAs layer 106B (the second laminated film thereof) is formed (FIG. 1B).

When the fifth and third layers are composed of the GaAs layer 106 and the GaAs layer 103 as in the first embodiment, A
As another compound semiconductor layer instead of the lGaAs layer 105, there is a compound semiconductor layer containing Al or In (the boiling point of InF ₃ is high) such as an AlAs layer, an InGaP layer, or an InGaAs layer. Further, in this case, AlG
Instead of the aAs layer 105, it is also possible to use an insulating film such as SiO ₂ or Si ₃ N ₄ or a conductor film such as silicide or Al. When an insulating film is used for the fourth layer, the restriction on the film thickness is looser than that of the AlGaAs layer 105. Note that when the second layer is not a compound semiconductor layer,
The third to fifth layers are not always formed by epitaxial growth. When the second layer is a compound semiconductor layer and the fourth layer is not a compound semiconductor layer, the third layer is formed by epitaxial growth, but the fifth layer is not necessarily formed by epitaxial growth. .

Next, after the photoresist film pattern 121 is removed, using the alignment mark 107,
A (second) photoresist film pattern 122a is formed. The GaAs layer 106B and the GaAs layer 104 in the alignment mark forming region 108 (the AlGaAs layer 105B and the AlGaAs layer 1 respectively) are formed by anisotropic etching using the photoresist film pattern 122a as a mask.
03, a recessed (second) alignment mark (EB mark) 109a for EB lithography is formed on the surface of the first laminated film, and at the same time, a recess 110a is formed. It is formed on the surface of the first laminated film. The bottom of the recess 110a is the AlGaAs layer 1
03 upper surface. The opening width of the recess 110a is, for example, about 0.7 μm, and the opening length (gate width) thereof is, for example, about 100 μm (FIG. 1C). The etching gas used for this anisotropic etching is AlGaAs
For example, since the GaAs layer is etched with high selectivity to the s layer and high smooth etching is required when forming the recess 110a, for example, S
It consists of F ₆ + SiCl ₄ .

The alignment mark 107 (for photolithography using a step) has a step of 100
A thickness of about nm is sufficient. However, it is not enough to satisfy the thickness of the GaAs layer 106, and it is required that the GaAs layer 106 has a film thickness necessary for alignment of EB lithography by detecting a step. The thickness of the GaAs layer 104 may be any value that is preferable as the depth of the recess 110a. AlG as the second layer
The functions required for the aAs layer 103 are to have the selectivity required for the anisotropic etching and to form a Schottky junction with the gate electrode. If these functions are satisfied, for example, as the second layer, AlG
In some cases, a compound semiconductor layer different from aAs, or an Al layer may be employed. The first layer is made of undoped Ga.
It is not limited to the As layer, but may be, for example, n-type GaAs having a thickness of about 100 nm to 300 nm depending on the purpose.
Layer, for example, undoped InGa having a thickness of about 10 nm.
Other compound semiconductor layers such as an As layer, and further an In layer or an As layer may be used.

Next, the photoresist film pattern 122a
Is removed, a (third) photoresist film pattern 123a is formed using the alignment mark 107 again. For example, the ohmic metal 111 is formed on the entire surface by sputtering. Ohmic Metal 1
Reference numeral 11 denotes, for example, a film in which a Ni layer, an AuGe layer, and an Au layer are sequentially stacked, but is not limited thereto (FIG. 1D).

Subsequently, a photoresist film pattern 123 is formed.
is lifted off, and a source electrode 112a (made of ohmic metal 111) and a drain electrode 113a are formed on the surface of the first laminated film [FIG.
(E)].

Next, using the EB mark 109a,
A B resist film pattern 125a is formed. The gate metal 114 is formed on the entire surface by, for example, sputtering. The gate metal 114 has, for example, a structure in which an Al layer is stacked on a Ti layer, but is not limited to this (FIG. 1F).

Thereafter, the EB resist film pattern 125a
Is lifted off, and the gate electrode 1 is
15a are formed. Thus, the semiconductor device according to the first example of the first embodiment is completed. The line width (gate length) of the gate electrode 115a is 0.1 μm to 0.2 μm.
μm, for example, 0.18 μm.
m. This gate electrode 115a is
It is provided at a position close to the source side by about 0.1 μm from the center of “a” (FIG. 1G).

In the first example of the first embodiment, the EB mark 109a is formed by one photolithography using the second photoresist film pattern 122a.
And recess 110a are formed at the same time. Therefore, the alignment accuracy of the gate electrode 115a with respect to the recess 110a is determined only by the alignment accuracy (about 0.05 μm) of one EB lithography. As a result, according to the method of manufacturing the semiconductor device according to the first embodiment of the first embodiment, the alignment accuracy of the gate electrode with respect to the recess is significantly improved as compared with the conventional manufacturing method, and the high-speed operation characteristics are improved. It becomes easier to obtain a better semiconductor device. For example, the average value of the maximum oscillation frequency in the conventional semiconductor device having the above-described dimension parameter is about 150 GHz. In the semiconductor device according to the first example of the first embodiment employing the same dimension parameters, a maximum oscillation frequency of about 210 GHz was obtained on average.

Referring to FIG. 2, which is a schematic cross-sectional view of the manufacturing process of the semiconductor device, the semiconductor device according to the second example of the first embodiment is formed as follows.

First, as in the first embodiment, the surface of the semi-insulating GaAs substrate 101 (as a first layer)
A first laminated film including a GaAs layer 102, an AlGaAs layer 103 (as a second layer), and a GaAs layer 104 (as a third layer) is formed by epitaxial growth, and further, an AlGaAs layer 105 (as a fourth layer).
And (as a fifth layer) a second laminated film composed of the GaAs layer 106 is formed by epitaxial growth. A (first) photoresist film pattern 121 is formed on the surface of the second laminated film. GaAs by anisotropic etching using the photoresist film pattern 121 as a mask
Layer 106 is selectively etched to form GaAs layer 10.
6A and the GaAs layer 106B are left. Further, the exposed AlGaAs layer 104 is removed by anisotropic etching using the photoresist film pattern 121 as a mask, and the AlGaAs layers 105A and 105A are removed.
The lGaAs layer 105B is left. This allows
An alignment mark 107 is provided on the surface of the first laminated film.
And an alignment mark formation scheduled area 108 (FIG. 2A).

Next, as in the first embodiment, after the photoresist film pattern 121 is removed, a (second) photoresist film pattern 122b is formed using the alignment mark 107. Using the photoresist film pattern 122b as a mask, for example, SF ₆ + SiC
Anisotropic etching using an etching gas composed of l ₄ is performed to form an EB mark 109b on the surface of the first laminated film, and at the same time, to form a recess 110b on the surface of the first laminated film. . The dimensions of the recess 110b are, for example, the same as the dimensions of the recess 110a (FIG. 2B).

Next, the photoresist film pattern 122b
Is removed. After that, unlike the first embodiment,
An EB resist film pattern 125b is formed using the EB mark 109b. A gate metal 114 is formed on the entire surface by, for example, sputtering [FIG.
(C)].

Subsequently, the EB resist film pattern 125b
Is lifted off, and the gate electrode 1 is formed in the recess 110b.
15b is formed [FIG. 2 (d)].

Next, using the alignment mark 107 again, the (third) photoresist film pattern 123b is used.
Is formed. For example, the ohmic metal 111 is formed on the entire surface by sputtering [FIG. 2 (e)].

Subsequently, a photoresist film pattern 123 is formed.
b is lifted off, and a source electrode 112b (made of ohmic metal 111) and a drain electrode 113b are formed on the surface of the first laminated film. This allows
The semiconductor device according to the second example of the first embodiment is completed. The line width (gate length) of the gate electrode 115b is also preferably in the range of 0.1 μm to 0.2 μm,
For example, it is about 0.18 μm. This gate electrode 11
5b is also 0.1 μm from the center of the recess 110b to the source side.
It is provided at a position close to the extent [FIG. 2 (f)].

The second example of the first embodiment is as follows.
The second embodiment has the same advantages as the first embodiment of the first embodiment.

Referring to FIG. 3, which is a schematic cross-sectional view of the manufacturing process of the semiconductor device, the semiconductor device according to the third example of the first embodiment is formed as follows.

First, as in the first and second embodiments,
On a surface of a semi-insulating GaAs substrate 101, a GaAs layer 102 (as a first layer) and an AlGa (as a second layer)
As layer 103 and GaAs layer 10 (as third layer)
4 is formed by epitaxial growth, and further (as a fourth layer) an AlGaAs layer 1 is formed.
A second stacked film composed of the GaAs layer 05 and the GaAs layer 106 (as a fifth layer) is formed by epitaxial growth. A (first) photoresist film pattern 121 is formed on the surface of the second laminated film. G by anisotropic etching using the photoresist film pattern 121 as a mask
The aAs layer 106 is selectively etched to form GaAs
The layer 106A and the GaAs layer 106B are left. Further, the AlGaAs layer 1 exposed by anisotropic etching using the photoresist film pattern 121 as a mask.
04 is removed by etching, and the AlGaAs layer 105A is removed.
And the AlGaAs layer 105B is left. As a result, an alignment mark 107 and a region 108 for forming an alignment mark are formed on the surface of the first laminated film (FIG. 3A).

Next, the photoresist film pattern 121 is removed. Thereafter, unlike the first and second embodiments, the (second)
A photoresist film pattern 123c is formed. For example, the ohmic metal 111 is formed on the entire surface by sputtering [FIG. 3B].

Subsequently, a photoresist film pattern 123 is formed.
c is lifted off, and a source electrode 112c (made of ohmic metal 111) and a drain electrode 113c are formed on the surface of the first laminated film [FIG.
(C)].

Next, the (third) photoresist film pattern 122c is reused by using the alignment mark 107 again.
Is formed. Using the photoresist film pattern 122c as a mask, anisotropic etching using an etching gas composed of, for example, SF ₆ + SiCl ₄ is performed, and EB
A mark 109c is formed on the surface of the first laminated film, and at the same time, a recess 110c is formed on the surface of the first laminated film. The dimensions of the recess 110c are the same as the dimensions of the recess 110a, for example [FIG.
(D)].

Next, the photoresist film pattern 122c
Is removed. Thereafter, an EB resist film pattern 125c is formed using the EB mark 109c. The gate metal 114 is formed on the entire surface by, for example, sputtering [FIG. 3E].

Subsequently, the EB resist film pattern 125c
Is lifted off, and the gate electrode 1 is
15c is formed. Thus, the semiconductor device according to the third example of the first embodiment is completed. The line width (gate length) of the gate electrode 115c is also 0.1 μm to 0.2 μm.
μm, for example, 0.18 μm.
m. This gate electrode 115c is also recess 110
It is provided at a position close to the source side by about 0.1 μm from the center of b (FIG. 3 (f)).

The third example of the first embodiment is also
The second embodiment has the advantages of the first and second embodiments of the first embodiment.

In the semiconductor device to which the manufacturing method according to the second embodiment of the present invention is applied, a recess is formed on the surface of a semiconductor substrate or a layer provided on the surface (at least the upper surface is made of a compound semiconductor). A gate electrode is formed in the recess, and a source and drain electrode is formed on the surface of this layer. This layer may be a single compound semiconductor layer or the first compound semiconductor layer of the first embodiment.
It has the same structure as that of the laminated film. When this layer has the same structure as the first laminated film, this layer is provided on the surface of the semiconductor substrate. When this layer is composed of a single compound semiconductor layer, when it is provided on the surface of the semiconductor substrate,
It may be provided on the surface of the semiconductor substrate by introducing impurities such as ion implantation.

The feature of the second embodiment is that an EB mark (which is a second alignment mark) (and a first alignment mark) and an opening for forming a recess are simultaneously formed by one photolithography. In that it is formed. The EB mark (and the first alignment mark) and the opening for forming the recess are formed in a conductor film provided on the semiconductor substrate so as to cover the layer. In the second embodiment, in both photolithography and EB lithography, reflection of light and electron beams between the first alignment mark and EB mark made of a conductive film and the above-mentioned layer (at least the upper surface is made of a compound semiconductor). The difference between the rates is used.

Referring to FIG. 4 which is a schematic cross-sectional view of the manufacturing process of the semiconductor device, the semiconductor device according to the first example of the second embodiment of the present invention is formed as follows.

First, as in the first example of the first embodiment, a first layer (for example, undoped, for example, 20 μm) is formed on the surface of the semi-insulating GaAs substrate 201.
A GaAs layer 202A (having a thickness of about 0 nm), and a second layer A (for example, n-type having a thickness of about 5 nm to 10 nm)
the lGaAs layer 203 and the third layer (for example, 50
n-type GaAs layer 20 having a thickness of about
4 is formed by epitaxial growth. Next, unlike the first embodiment, a WSi film 2 is formed on the entire surface by, for example, sputtering as a conductor film.
31A are formed. The thickness of the WSi film 231A is preferably at least about several nm. As the conductor film, another silicide can be used instead of the WSi film 231A. A (first) photoresist film pattern 226 is formed on the surface of the WSi film 231A (FIG. 4A).

Next, for example, as in CF ₄ + SF ₆ (C
The WSi film 231A is selectively etched and removed by dry etching using the photoresist film pattern 226 as a mask with a gas not containing l as an etching gas. Thereby, an opening 240A for forming a recess is formed in the WSi film 231A, and at the same time, the WSi film 2 is formed.
31A (first alignment mark for photolithography) and EB mark 209A (second alignment mark for EB lithography)
Is formed on the surface of the laminated film (FIG. 4B).

Next, a photoresist film pattern 226 is formed.
After removal, use the alignment mark 207A.
To form a (second) photoresist film pattern 227
Is done. At least the alignment mark 207A and
The EB mark 209A indicates the photoresist film pattern 2
27, but at least the opening 240A
Is not covered by this photoresist film pattern 227
To) exposed. This photoresist film pattern 22
7 and opening 240A as a mask, for example, Cl _Two + S
iCl_Four To the GaAs layer 204 using
Dry etching is selectively performed to form recess 2
10A is formed in the opening 240A in a self-aligned manner. Re
The opening width of the process 210A is, for example, about 0.7 μm,
The opening length (gate width) is, for example, about 100 μm.
[FIG. 4 (c)]. In this etching, the AlGaAs layer
203 also functions as a stopper layer. Also this etch
If a smoothing gas is used, highly smooth etching can be performed.
You.

Subsequently, a photoresist film pattern 227 is formed.
The exposed WSi film 231A is dry-etched using, for example, SF ₆ or the like as an etching gas with the mask as a mask.
Are selectively removed by etching [FIG. 4 (d)].

The restrictions on the configuration of the semiconductor substrate and the laminated film in this embodiment are the same as the restrictions on the configuration of the semiconductor substrate and the first laminated film in the first embodiment of the first embodiment. . In the present embodiment, the conductive film may include a means for selectively etching the third layer with respect to the conductive film, in addition to the constituent materials of the second and third layers (constituting the stacked film). , A conductive film is selected selectively with respect to the second and third layers by an etching means. In the first embodiment, since the fourth layer is removed before the formation of the recess, it is possible to employ Al or the like as the fourth layer. However, in this embodiment, it is necessary to remove the conductive film after forming the recess (without damaging the bottom surface of the recess), and thus it is not preferable to use Al as the conductive film.

Next, after the photoresist film pattern 227 is removed, a (third) photoresist film pattern 223a is formed again using the alignment mark 207A. For example, the ohmic metal 211A is formed on the entire surface by sputtering. The ohmic metal 211A is, for example, a film in which a Ni layer, an AuGe layer, and an Au layer are sequentially stacked, but is not limited thereto (FIG. 4E).

Subsequently, a photoresist film pattern 223 is formed.
is lifted off, and the source electrode 21 (made of the ohmic metal 211A) is formed on the surface of the GaAs layer 204.
2Aa and a drain electrode 213Aa are formed [FIG. 4 (f)].

Next, using the EB mark 209A,
A B resist film pattern 225a is formed. For example, the gate metal 214A is formed on the entire surface by sputtering. The gate metal 214A is formed, for example, by adding A to the Ti layer.
It has a structure in which one layer is laminated, but is not limited to this (FIG. 4G).

Thereafter, the EB resist film pattern 225a
Is lifted off, and the gate electrode 2 is formed in the recess 210A.
15Aa is formed. Thus, the semiconductor device according to the first example of the second embodiment is completed. The line width (gate length) of the gate electrode 215Aa is 0.1 μm or more.
It is preferably in the range of 0.2 μm, for example, 0.
It is about 18 μm. The gate electrode 215Aa is provided at a position close to the source side by about 0.1 μm from the center of the recess 210A [FIG. 4 (h)].

In the first example of the second embodiment, the first photoresist film pattern 226 is used.
The EB mark 209A and the opening 240A for forming the recess 210A are formed simultaneously by photolithography. Further, the recess 210A has an opening 240A.
Therefore, the alignment accuracy of the gate electrode 215Aa with respect to the recess 210A is determined only by the alignment accuracy of one EB lithography (about 0.05 μm). That is, the method of manufacturing the semiconductor device according to the first example of the second embodiment also has the same effects as those of the first embodiment.

The technical idea of the first embodiment of the second embodiment is that, instead of the above-mentioned laminated film (consisting of the first, second and third layers), on the surface of the semiconductor substrate A single compound semiconductor layer is formed, and an n-type compound semiconductor layer is formed on the surface of a semi-insulating compound semiconductor substrate (or a predetermined region of the surface) by, for example, introducing impurities by ion implantation. Applicable.

Referring to FIG. 5, which is a schematic cross-sectional view of a manufacturing process of a semiconductor device, a semiconductor device according to an application of the first embodiment of the second embodiment is formed as follows.

First, an n-type GaAs layer 202B having a thickness of, for example, about 300 nm is formed on the surface of the semi-insulating GaAs substrate 201. Next, a WSi film 231B is formed on the entire surface by, for example, sputtering. WSi film 2
A (first) photoresist film pattern 226 is formed on the surface of 31B (FIG. 5A).

Next, for example, CF ₄ + SF ₆ (like C
The WSi film 231B is selectively etched and removed by dry etching using the photoresist film pattern 231B as a mask with a gas not containing l as an etching gas. Thereby, an opening 240B for forming a recess is formed in the WSi film 231B, and at the same time, the alignment marks 207B and E formed of the WSi film 231B are formed.
A B mark 209B is left on the surface of the GaAs film 202B (FIG. 5B).

Next, a photoresist film pattern 226 is formed.
After removal, use the alignment mark 207B.
To form a (second) photoresist film pattern 227
Is done. At least the alignment mark 207B and
The EB mark 209B is the photoresist film pattern 2
27, but at least the opening 240B
Is not covered by this photoresist film pattern 227
To) exposed. This photoresist film pattern 22
7 and opening 240B as a mask, for example, Cl _Two + S
iCl_Four Was used as an etching gas (GaAs layer 202B).
GaAs by selective (dry etching)
The layer 202B has a required depth (in the range of 50 nm to 150 nm).
) Is etched so that the recess 210B is
40B is formed in a self-aligned manner. Opening recess 210B
The opening width is, for example, about 0.7 μm, and the opening length (ge
Is about 100 μm, for example [see FIG.
(C)].

Subsequently, a photoresist film pattern 227 is formed.
Was a mask, for example, by dry etching using SF ₆ or the like as etching gas, the exposed WSi film 231B
Is selectively removed by etching [FIG. 5 (d)].

In the present application example, when the n-type compound semiconductor layer is formed in a predetermined region on the surface of the semi-insulating compound semiconductor substrate, the following is obtained. The conductor film has a form that covers the surface of the semi-insulating compound semiconductor substrate, including the upper surface of the n-type compound semiconductor layer (rather than being formed only on the surface of the n-type compound semiconductor layer). Formed. In this case, the first alignment mark and the EB
The mark (not on the surface of the n-type compound semiconductor layer)
It is preferably formed on the surface of the semi-insulating compound semiconductor substrate where the n-type compound semiconductor layer is not formed.

Next, after the photoresist film pattern 227 is removed, a (third) photoresist film pattern 223a is formed again using the alignment mark 207B. For example, the ohmic metal 211B is formed on the entire surface by sputtering. The ohmic metal 211B is, for example, a film in which a Ni layer, an AuGe layer, and an Au layer are sequentially stacked, but is not limited to this (FIG. 5E).

Subsequently, a photoresist film pattern 223 is formed.
is lifted off, and the source electrode 2 (made of ohmic metal 211B) is formed on the surface of the GaAs layer 202B.
12Ba and a drain electrode 213Ba are formed [FIG. 5 (f)].

Next, using the EB mark 209B,
A B resist film pattern 225a is formed. For example, the gate metal 214B is formed on the entire surface by sputtering. The gate metal 214B is formed by, for example,
It has a structure in which one layer is laminated, but is not limited to this (FIG. 5 (g)).

Thereafter, the EB resist film pattern 225a
Is lifted off, and the gate electrode 2 is
15Ba is formed. Thus, the semiconductor device according to the application example of the first example of the second embodiment is completed. The line width (gate length) of the gate electrode 215Ba is 0.5.
It is preferably in the range of 1 μm to 0.2 μm, for example, about 0.18 μm. This gate electrode 215B
a is provided at a position close to the source side by about 0.1 μm from the center of the recess 210B [FIG. 5 (h)].

An application example of the first embodiment of the second embodiment has the same effect as that of the first embodiment of the second embodiment.

Referring to FIG. 6, which is a schematic cross-sectional view of a manufacturing process of a semiconductor device, a semiconductor device according to a second example of the second embodiment of the present invention is formed as follows.

First, on the surface of the semi-insulating GaAs substrate 201, a GaAs layer 202A as a first layer and a second layer are formed on the surface of the semi-insulating GaAs substrate 201, as in the first example of the second embodiment. AlGaAs layer 203 and GaAs as third layer
A laminated film including the layer 204 is formed by epitaxial growth. Next, a WSi film (not shown in the figure) is formed as a conductive film over the entire surface by, for example, sputtering. W
A first photoresist film pattern (not shown) is formed on the surface of the Si film. Next, for example, CF ₄ + SF
The WSi film is selectively etched and removed by dry etching using ₆ (a gas containing no Cl as described above) as an etching gas and the first photoresist film pattern as a mask. As a result, an opening (not shown) for forming a recess is formed in the WSi film.
Alignment marks 207A and 207 made of WSi film
A B mark 209A is left on the surface of the laminated film.

Next, after the first photoresist film pattern is removed, a (second) photoresist film pattern 227 is formed using the alignment mark 207A. Using the photoresist film pattern 227 and the opening as a mask, dry etching is selectively performed on the GaAs layer 204 using, for example, Cl ₂ + SiCl ₄ as an etching gas, and a recess 210A is formed in the opening in a self-aligned manner. Is done. The opening width of the recess 210A is, for example, about 0.7 μm, and the opening length (gate width) thereof is, for example, about 100 μm. Subsequently, using the photoresist film pattern 227 as a mask, for example, SF
_The exposed portion of the WSi film is selectively removed by dry etching using ₆ or the like as an etching gas [FIG. 6 (a)].

The restrictions on the configuration of the semiconductor substrate and the laminated film in this example are the same as the restrictions on the configuration of the semiconductor substrate and the first laminated film in the first example of the second embodiment. .

Next, after the photoresist film pattern 227 is removed, an EB resist film pattern 225b is formed using the EB mark 209A. For example, the gate metal 214A is formed on the entire surface by sputtering. The gate metal 214A has, for example, a structure in which an Al layer is laminated on a Ti layer, but is not limited to this (FIG. 6B).

Thereafter, the EB resist film pattern 225b
Is lifted off, and the gate electrode 2 is formed in the recess 210A.
15Ab is formed. The line width (gate length) of the gate electrode 215Ab is preferably in the range of 0.1 μm to 0.2 μm, for example, about 0.18 μm. The gate electrode 215Ab is provided at a position close to the source side from the center of the recess 210A by about 0.1 μm (FIG. 6C).

Next, the (third) photoresist film pattern 223 is again utilized by using the alignment mark 207A.
b is formed. For example, the ohmic metal 211A is formed on the entire surface by sputtering. The ohmic metal 211A includes, for example, a Ni layer, an AuGe layer, and an Au layer.
Although the layers are formed of sequentially laminated films, the present invention is not limited thereto (FIG. 6D).

Subsequently, a photoresist film pattern 223 is formed.
is lifted off, and the source electrode 21 (made of the ohmic metal 211A) is formed on the surface of the GaAs layer 204.
2Ab and a drain electrode 213Ab are formed. Thus, the semiconductor device according to the second example of the second embodiment is completed [FIG. 6 (e)].

The method of manufacturing the semiconductor device according to the second embodiment of the second embodiment has the same effects as those of the first embodiment.

The technical idea of the second embodiment of the second embodiment is that the above-mentioned laminated film (consisting of the first, second and third layers) is formed on the surface of the semiconductor substrate instead of the laminated film. A single compound semiconductor layer is formed, and an n-type compound semiconductor layer is formed on the surface of a semi-insulating compound semiconductor substrate (or a predetermined region of the surface) by, for example, introducing impurities by ion implantation. Applicable.

Referring to FIG. 7, which is a schematic cross-sectional view of a manufacturing process of a semiconductor device, a semiconductor device according to an application of the first embodiment of the second embodiment is formed as follows.

First, an n-type GaAs layer 202B having a thickness of, for example, about 300 nm is formed on the surface of the semi-insulating GaAs substrate 201. Next, a WSi film (not shown in the figure) is formed as a conductor film on the entire surface by, for example, sputtering. A first photoresist film pattern (not shown) is formed on the surface of the WSi film. Next, the WSi film is selectively etched and removed by dry etching using, for example, CF ₄ + SF ₆ (a gas containing no Cl such as SF ₄ ) as a mask with the first photoresist film pattern as a mask. You. Thereby, the above W
An opening (not shown) for forming a recess is formed in the Si film, and at the same time, the alignment mark 207B and the EB mark 209B made of the WSi film are formed on the GaAs film 202.
B is formed on the surface of B.

Next, after the first photoresist film pattern is removed, a (second) photoresist film pattern 227 is formed using the alignment mark 207B. Using the photoresist film pattern 227 and the opening as a mask, the GaAs layer 202B using, for example, Cl ₂ + SiCl ₄ as an etching gas is etched to a required depth (range of 50 nm to 150 nm), and the recess 210B is opened. The part is formed in a self-aligned manner. The opening width of the recess 210B is, for example, about 0.7 μm, and the opening length (gate width) thereof is, for example, 100 μm.
It is about. Subsequently, the photoresist film pattern 227
Was a mask, for example, by dry etching using SF ₆ or the like as etching gas, the exposed WSi film 231B
Are selectively removed by etching [FIG. 7 (a)].

In the present application example, when the n-type compound semiconductor layer is formed in a predetermined region on the surface of the semi-insulating compound semiconductor substrate, the following is obtained. The conductor film has a form that covers the surface of the semi-insulating compound semiconductor substrate, including the upper surface of the n-type compound semiconductor layer (rather than being formed only on the surface of the n-type compound semiconductor layer). Formed. In this case, the first alignment mark and the EB
The mark (not on the surface of the n-type compound semiconductor layer)
It is preferably formed on the surface of the semi-insulating compound semiconductor substrate where the n-type compound semiconductor layer is not formed.

Next, after the photoresist film pattern 227 is removed, an EB resist film pattern 225b is formed using the EB mark 209B. For example, the gate metal 214B is formed on the entire surface by sputtering. The gate metal 214B has, for example, a structure in which an Al layer is laminated on a Ti layer, but is not limited to this (FIG. 7B).

Thereafter, the EB resist film pattern 225b
Is lifted off, and the gate electrode 2 is
15Bb is formed. The line width (gate length) of the gate electrode 215Bb is preferably in the range of 0.1 μm to 0.2 μm, for example, about 0.18 μm. The gate electrode 215Bb is provided at a position close to the source side by about 0.1 μm from the center of the recess 210B [FIG. 7 (c)].

Next, using the alignment mark 207B again, the (third) photoresist film pattern 223 is used.
b is formed. For example, the ohmic metal 211B is formed on the entire surface by sputtering. The ohmic metal 211B includes, for example, a Ni layer, an AuGe layer, and an Au layer.
Although the layers are formed of sequentially laminated films, the present invention is not limited thereto (FIG. 7D).

Subsequently, a photoresist film pattern 223 is formed.
b is lifted off, and the source electrode 2 (made of ohmic metal 211B) is formed on the surface of the GaAs layer 202B.
12Bb and a drain electrode 213Bb are formed (FIG. 7E). As a result, a semiconductor device according to an application example of the second example of the second embodiment is completed.

An application example of the second embodiment of the second embodiment has the same effect as that of the second embodiment of the second embodiment.

The semiconductor device to which the manufacturing method of the third embodiment of the present invention is applied is also provided on the surface of the semiconductor substrate or at least on the surface thereof (at least the upper surface is a compound), as in the second embodiment. This is a compound semiconductor device in which a recess is formed on the surface of a layer (comprising a semiconductor), a gate electrode is formed in the recess, and source and drain electrodes are formed on the surface of this layer. This layer is composed of a single compound semiconductor layer or a laminated film having the same structure as the first laminated film of the first embodiment. When this layer is made of the laminated film, this layer is provided on the surface of the semiconductor substrate. When this layer is formed of a single compound semiconductor layer, there are a case where it is provided on the surface of the semiconductor substrate and a case where it is provided on the surface of the semiconductor substrate by introduction of impurities such as ion implantation.

The feature of the third embodiment is that the (second alignment mark) EB mark formation (second alignment mark)
1) and the recess (i.e., the first opening for forming the first alignment mark) and the recess are formed simultaneously by one photolithography. The (second) opening for forming the EB mark (and the first opening for forming the first alignment mark) is formed in an insulating film provided on the semiconductor substrate so as to cover the above layer. Is done. Book 3
In the embodiment, the step formed by the EB mark provided on the surface of the semiconductor substrate or on the surface in a self-aligned manner with the (second) opening is used for EB lithography alignment.

Referring to FIG. 8, which is a schematic cross-sectional view of a manufacturing process of a semiconductor device, a semiconductor device according to a first example of the third embodiment of the present invention is formed as follows.

First, as in the first embodiment of the first and second embodiments, a first layer (for example, undoped, for example, 200 nm) is formed on the surface of the semi-insulating GaAs substrate 301. GaAs layer 302A (with a thickness of about
A laminated film composed of an AlGaAs layer 303 (for example, n-type with a thickness of about 5 nm to 10 nm) and a GaAs layer 304 (for example, n-type with a thickness of about 100 nm) is formed by epitaxial growth. It is formed.
The GaAs layer 304 has a thickness of 50 nm to 1 nm.
Preferably it is in the range of 50 nm. Next, unlike the first and second embodiments, a SiO ₂ film 332A is formed as an insulating film on the entire surface by, for example, a CVD method. The thickness of the SiO ₂ film 332A is at least 1
It is preferably about 0 nm. SiO ₂ film 332A
Instead, an insulating film such as a Si ₃ N ₄ film that can be selectively etched away (with respect to a compound semiconductor) with an etching gas containing no Cl, or a recess (formed in a later step) is damaged. It is also possible to employ an insulating film that can be wet-etched without imparting the same. S
A (first) photoresist film pattern 328 is formed on the surface of the iO ₂ film 332A (FIG. 8A).

[0098] Then, for example, CF ₄ + CHF ₃ (the gas does not contain Cl as) as an etching gas, by dry etching using a photoresist film pattern 328 as a mask, SiO ₂ film 332A is selectively etched Removed. Thereby, the SiO ₂ film 332A has
(First) opening 3 for forming first alignment mark
37A and opening 33 (for EB mark formation)
9A is formed. Photoresist film pattern 3
Using the mask 28 as a mask, the GaAs layer 304 is selectively anisotropically etched using, for example, BCl ₃ + SF ₆ as an etching gas. As a result, a recess 310A is formed. The opening width of the recess 310A is, for example, about 0.7 μm, and the opening length (gate width) thereof is, for example, 100 μm.
m. In this etching, the AlGaAs layer 30
3 also functions as a stopper layer. If this etching gas is used, highly smooth etching can be performed (FIG. 8B).

At the time of this etching, the opening 3
The GaAs layer 304 is etched in a self-aligned manner at 37A and 339A. At this stage, the concave shape related to the opening 339A does not function as an EB mark. On the other hand, the opening 337A itself and the concave shape related to the opening 337A (because the step is at least about 10 nm or more) function as an alignment mark for photolithography. However, at this stage, the opening 337A itself and the concave shape related to the opening 337A are not referred to as “alignment marks” for convenience (including avoiding complexity).

Next, after the photoresist film pattern 328 is removed, a (second) photoresist film pattern 329 is formed using the concave shape associated with the opening 307A. At least the recess 310A is covered with the photoresist film pattern 329 and the opening 3
37A and the opening 339A are exposed without being covered by the photoresist film pattern 329. Subsequently, the photoresist film pattern 329 and the openings 337A and 339 are formed.
A as a mask, for example, using Cl ₂ + SiCl ₄ as an etching gas, the AlGaAs layer 303 and the GaAs layer 3.
02A and the semi-insulating GaAs substrate 301 are sequentially anisotropically etched until the total film thickness becomes at least about 300 nm. Thereby, the openings 337A, 33
9A, an alignment mark 307A (a first alignment mark for photolithography) and an EB mark 309A (which is a second alignment mark for EB lithography) having a depth of at least about 400 nm are formed in a self-aligned manner. [FIG. 8 (c)].

After the photoresist film pattern 329 is removed, the SiO ₂ film 332A is selectively removed by wet etching using a hydrofluoric acid (HF) -based etchant (FIG. 8D).

Next, a (third) photoresist film pattern 323a is formed using the alignment mark 307A. For example, ohmic metal 311A is formed on the entire surface by sputtering. The ohmic metal 311A is, for example, a film in which a Ni layer, an AuGe layer, and an Au layer are sequentially stacked, but is not limited thereto (FIG. 8E).

Subsequently, a photoresist film pattern 323 is formed.
is lifted off, and the source electrode 31 (made of ohmic metal 311A) is formed on the surface of the GaAs layer 304.
2Aa and a drain electrode 313Aa are formed [FIG. 8 (f)].

Next, using the EB mark 309A,
A B resist film pattern 325a is formed. For example, the gate metal 314A is formed on the entire surface by sputtering. The gate metal 314A is formed, for example, by adding A to the Ti layer.
It has a structure in which one layer is laminated, but is not limited to this (FIG. 8 (g)).

Thereafter, the EB resist film pattern 325a
Is lifted off, and the gate electrode 3 is formed in the recess 310A.
15Aa is formed. Thus, the semiconductor device according to the first example of the third embodiment is completed. The line width (gate length) of the gate electrode 315Aa is 0.1 μm or more.
It is preferably in the range of 0.2 μm, for example, 0.1 μm.
It is about 18 μm. The gate electrode 315Aa is provided at a position close to the source side by about 0.1 μm from the center of the recess 310A [FIG. 8 (h)].

In the first example of the third embodiment, the first example using the first photoresist film pattern 328
The opening 339A for the EB mark and the recess 310A are formed at the same time by the second photolithography.
Further, since the EB mark 309A can be formed in the opening 339A in a self-aligned manner, the recess 210A
Alignment accuracy of the gate electrode 315Aa with respect to
EB lithography alignment accuracy (0.05
μm) alone. That is, the method of manufacturing the semiconductor device according to the first example of the third embodiment has the same effects as those of the first and second embodiments.

The technical idea of the first embodiment of the third embodiment is that, instead of the above-mentioned laminated film (comprising the first, second and third layers), A single compound semiconductor layer is formed, and an n-type compound semiconductor layer is formed on the surface of a semi-insulating compound semiconductor substrate (or a predetermined region of the surface) by, for example, introducing impurities by ion implantation. Applicable.

Referring to FIG. 9, which is a schematic cross-sectional view of a manufacturing process of a semiconductor device, a semiconductor device according to an application of the first embodiment of the third embodiment is formed as follows.

First, an n-type GaAs layer 302B having a thickness of, for example, about 300 nm is formed on the surface of the semi-insulating GaAs substrate 301. Next, an SiO ₂ film 332B is formed on the entire surface by, for example, a CVD method. SiO ₂ film 33
A (first) photoresist film pattern 328 is formed on the surface of 2B (FIG. 9A).

Next, an SiO ₂ film 332B is formed by dry etching using, for example, CF ₄ + CHF ₃ as an etching gas and a photoresist film pattern 328 as a mask.
Is selectively removed by etching. Thereby, the SiO
_The opening 337B and the opening 339 are provided in the _two films 332A.
B is formed. Further, a photoresist film pattern 32
8 as a mask, for example, using BCl ₃ + SF ₆ as an etching gas,
It is selectively anisotropically etched by a thickness of about m. As a result, a recess 310B is formed. Recess 310
The opening width of B is, for example, about 0.7 μm, and the opening length (gate width) thereof is, for example, about 100 μm [FIG.
(B)].

Next, after the photoresist film pattern 328 is removed, a (second) photoresist film pattern 329 is formed using the concave shape associated with the opening 337B. Subsequently, the photoresist film pattern 3
29 and the openings 337A and 339A as masks, for example, Cl ₂ + SiCl ₄ as an etching gas and GaAs.
Until the total film thickness of the s layer 302B and the semi-insulating GaAs substrate 301 becomes at least about 300 nm, these are sequentially anisotropically etched. Thereby, the opening 33
7B and 339B, respectively, at least 4
An alignment mark 307B (a first alignment mark for photolithography) and an EB mark 309B (which is a second alignment mark for EB lithography) having a depth of about 00 nm are formed (FIG. 9C).

After the photoresist film pattern 329 is removed, the SiO ₂ film 332B is selectively removed by wet etching using a hydrofluoric acid (HF) -based etchant (FIG. 9D).

In the present application example, when the n-type compound semiconductor layer is formed in a predetermined region on the surface of the semi-insulating compound semiconductor substrate, the following is obtained. The insulating film is (n
Rather than being formed only on the surface of the n-type compound semiconductor layer), it is formed so as to cover the surface of the semi-insulating compound semiconductor substrate including the upper surface of the n-type compound semiconductor layer. In this case, the first and second openings are formed on the surface of the semi-insulating compound semiconductor substrate where the n-type compound semiconductor layer is not formed (not on the surface of the n-type compound semiconductor layer). The first alignment mark and the EB mark are preferably formed on the surface of the semi-insulating compound semiconductor substrate where the n-type compound semiconductor layer is not formed (not on the surface of the n-type compound semiconductor layer). It is preferably formed.

Next, a (third) photoresist film pattern 323a is formed using the alignment mark 307B. For example, the ohmic metal 311B is formed on the entire surface by sputtering. The ohmic metal 311B is, for example, a film in which a Ni layer, an AuGe layer, and an Au layer are sequentially stacked, but is not limited thereto (FIG. 9E).

Subsequently, a photoresist film pattern 323 is formed.
is lifted off, and the source electrode 3 (made of ohmic metal 311B) is formed on the surface of the GaAs layer 302B.
12Ba and a drain electrode 313Ba are formed [FIG. 9 (f)].

Next, using the EB mark 309B,
A B resist film pattern 325a is formed. For example, the gate metal 314B is formed on the entire surface by sputtering. The gate metal 314B is formed, for example, by adding A to the Ti layer.
It has a structure in which one layer is laminated, but is not limited to this (FIG. 9G).

Thereafter, the EB resist film pattern 325a
Is lifted off, and the gate electrode 3 is formed in the recess 310B.
15Ba is formed. Thus, the semiconductor device according to the application example of the first example of the third embodiment is completed. The line width (gate length) of the gate electrode 315Ba is 0.
It is preferably in the range of 1 μm to 0.2 μm, for example, about 0.18 μm. This gate electrode 315B
a is provided at a position close to the source side by about 0.1 μm from the center of the recess 310B [FIG. 9 (h)].

An application example of the first embodiment of the third embodiment has the same effect as that of the first embodiment of the third embodiment.

Referring to FIG. 10, which is a schematic cross-sectional view of a manufacturing process of a semiconductor device, the second embodiment according to the third embodiment of the present invention is described.
The semiconductor device according to the embodiment is formed as follows.

First, as in the first example of the third embodiment, a first layer (eg, undoped, eg, 20 μm) is formed on the surface of the semi-insulating GaAs substrate 301.
A GaAs layer 302A (having a thickness of about 0 nm), and a second layer (eg, n-type having a thickness of about 5 nm to 10 nm)
the lGaAs layer 303 and the third layer (for example, 10
A stacked film including the n-type (GaAs layer) 304 having a thickness of about 0 nm is formed by epitaxial growth. In addition,
The thickness of the GaAs layer 304 is 50 nm to 150 n.
It is preferably in the range of m. Next, as an insulating film,
For example, an SiO ₂ film (not shown) is formed on the entire surface by a CVD method. A first photoresist film pattern (not shown) is formed on the surface of the SiO ₂ film. Next, for example, CF ₄ + CHF ₃ (a gas containing no Cl such as)
Is used as an etching gas, and dry etching is performed using the first photoresist film pattern as a mask.
The O ₂ film is selectively etched away. This allows
In the SiO ₂ film, a first opening (not shown) for forming a first alignment mark and a second opening (not shown) for forming an EB mark are formed. Further, using the first photoresist film pattern as a mask, for example, BCl ₃ + SF ₆ is used as an etching gas to form GaAs.
Layer 304 is selectively anisotropically etched. As a result, a recess 310A is formed. The opening width of the recess 310A is, for example, about 0.7 μm, and the opening length (gate width) thereof is, for example, about 100 μm.

Next, after the first photoresist film pattern is removed, a second photoresist film pattern (not shown) is formed using the concave shape associated with the first opening 307A. It is formed. Subsequently, using the second photoresist film pattern and the first and second openings as masks, and using, for example, Cl ₂ + SiCl ₄ as an etching gas, the AlGaAs layer 303, the GaAs layer 302A,
The total thickness of the semi-insulating GaAs substrate 301 is at least 3
These are sequentially anisotropically etched until the thickness becomes about 00 nm. Thereby, the (first) alignment mark 307A (the second alignment mark for EB lithography) and the (first lithography alignment mark) 307A having a depth of at least about 400 nm are respectively self-aligned with the first and second openings. EB mark 309A is formed. After the second photoresist film pattern is removed, the SiO ₂ film 332A is selectively removed by wet etching using a hydrofluoric acid (HF) -based etchant (FIG. 10A).

The restrictions on the configuration of the semiconductor substrate and the laminated film in the present example are the same as the restrictions on the configuration of the semiconductor substrate and the laminated film in the first example of the third embodiment. The definition of the (first) alignment mark in this embodiment is the same as that in the first embodiment of the third embodiment.

Next, using the EB mark 309A,
A B resist film pattern 325b is formed. For example, the gate metal 314A is formed on the entire surface by sputtering. The gate metal 314A is formed, for example, by adding A to the Ti layer.
It has a structure in which one layer is laminated, but is not limited to this (FIG. 10B).

Thereafter, the EB resist film pattern 325b
Is lifted off, and the gate electrode 3 is formed in the recess 310A.
15Ab is formed. The line width (gate length) of the gate electrode 315Ab is preferably in the range of 0.1 μm to 0.2 μm, for example, about 0.18 μm. This gate electrode 315Ab is provided at a position close to the source side by about 0.1 μm from the center of the recess 310A [FIG. 10 (c)].

Next, a (third) photoresist film pattern 323b is formed using the alignment mark 307A. For example, ohmic metal 311A is formed on the entire surface by sputtering. The ohmic metal 311A is, for example, a film in which a Ni layer, an AuGe layer, and an Au layer are sequentially stacked, but is not limited thereto (FIG. 10D).

Subsequently, a photoresist film pattern 323 is formed.
b is lifted off, and the source electrode 31 (made of ohmic metal 311A) is formed on the surface of the GaAs layer 304.
2Ab and a drain electrode 313Ab are formed. Thus, the semiconductor device according to the second example of the third embodiment is completed. [FIG. 10 (e)].

The method of manufacturing the semiconductor device according to the second example of the third embodiment has the same effects as those of the first and second embodiments.

The technical idea of the second embodiment of the third embodiment is that the laminated film (consisting of the first, second and third layers) is formed on the surface of the semiconductor substrate instead of the laminated film. A single compound semiconductor layer is formed, and an n-type compound semiconductor layer is formed on the surface of a semi-insulating compound semiconductor substrate (or a predetermined region of the surface) by, for example, introducing impurities by ion implantation. Applicable.

Referring to FIG. 11, which is a schematic cross-sectional view of a manufacturing process of a semiconductor device, a semiconductor device according to an application of the first embodiment of the third embodiment is formed as follows.

First, an n-type GaAs layer 302B having a thickness of, for example, about 300 nm is formed on the surface of the semi-insulating GaAs substrate 301. Next, a SiO ₂ film (not shown) is formed as an insulating film on the entire surface by, eg, CVD. A first photoresist film pattern (not shown) is formed on the surface of the SiO ₂ film. Then, for example, C
By using F ₄ + CHF ₃ as an etching gas, the SiO ₂ film is selectively etched away by dry etching using the first photoresist film pattern as a mask. Thereby, the SiO ₂ film is formed (for forming a second alignment mark for photolithography).
A first opening (not shown) and a second opening (not shown) (for forming a second alignment mark for EB lithography) are formed. First
Using the photoresist film pattern as a mask, for example, B
By using Cl ₃ + SF ₆ as an etching gas, the GaAs layer 302B is selectively anisotropically etched to a thickness of, for example, about 100 nm. As a result, a recess 310B is formed. The opening width of the recess 310B is, for example, 0.7 μm.
m, and its opening length (gate width) is, for example, 10
It is about 0 μm.

Next, after the first photoresist film pattern is removed, a second photoresist film pattern (not shown) is formed by utilizing the concave shape associated with the first opening. Is done. Subsequently, the GaAs layer 302B and the semi-insulating GaAs substrate 3 are formed by using the second photoresist film pattern and the first and second openings as a mask and using, for example, Cl ₂ + SiCl ₄ as an etching gas.
These are sequentially anisotropically etched until the total film thickness of 01 becomes at least about 300 nm. As a result, the (first) photolithography alignment marks 307B, (EB) having a depth of at least about 400 nm are respectively self-aligned with the first and second openings.
A second alignment mark for lithography) E
A B mark 309B is formed. After the second photoresist film pattern is removed, the Si film is etched by wet etching using a hydrofluoric acid (HF) -based etchant.
The O ₂ film is selectively removed [FIG. 11 (a)].

In this application example, the case where the n-type compound semiconductor layer is formed in a predetermined region on the surface of the semi-insulating compound semiconductor substrate is as follows. The insulating film (rather than being formed only on the surface of the n-type compound semiconductor layer) has a form covering the surface of the semi-insulating compound semiconductor substrate including the upper surface of the n-type compound semiconductor layer. It is formed. In this case, the first and second openings are formed on the surface of the semi-insulating compound semiconductor substrate where the n-type compound semiconductor layer is not formed (not on the surface of the n-type compound semiconductor layer). The first alignment mark and the EB mark are preferably formed on the surface of the semi-insulating compound semiconductor substrate where the n-type compound semiconductor layer is not formed (not on the surface of the n-type compound semiconductor layer). It is preferably formed.

Next, using the EB mark 309B,
A B resist film pattern 325b is formed. For example, the gate metal 314B is formed on the entire surface by sputtering. The gate metal 314B is formed, for example, by adding A to the Ti layer.
It has a structure in which one layer is laminated, but is not limited to this (FIG. 11B).

Thereafter, the EB resist film pattern 325b
Is lifted off, and the gate electrode 3 is formed in the recess 310B.
15Bb is formed. The line width (gate length) of the gate electrode 315Bb is preferably in the range of 0.1 μm to 0.2 μm, for example, about 0.18 μm. The gate electrode 315Bb is provided at a position close to the source side by about 0.1 μm from the center of the recess 310B (FIG. 11C).

Next, a (third) photoresist film pattern 323b is formed using the alignment mark 307B. For example, the ohmic metal 311B is formed on the entire surface by sputtering. The ohmic metal 311B is, for example, a film in which a Ni layer, an AuGe layer, and an Au layer are sequentially stacked, but is not limited to this (FIG. 11D).

Subsequently, a photoresist film pattern 323 is formed.
b is lifted off, and the source electrode 3 (made of ohmic metal 311B) is formed on the surface of the GaAs layer 302B.
12Bb and a drain electrode 313Bb are formed.
Thus, a semiconductor device according to an application example of the second embodiment of the third embodiment is completed (FIG. 11E).

An application example of the second embodiment of the third embodiment has the same effect as that of the second embodiment of the third embodiment.

[0138]

As described above, according to the method of manufacturing a semiconductor device of the present invention, an opening for forming an EB mark and a recess, an opening for forming an EB mark and a recell, or an opening for forming an EB mark is formed by one photolithography. Are formed at the same time, the alignment accuracy of the recess and the gate electrode is equal to the alignment accuracy of one EB lithography. As a result, a compound semiconductor device having excellent high-speed operation characteristics can be easily manufactured.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a manufacturing process according to a first example of the first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a manufacturing process according to a second example of the first embodiment.

FIG. 3 is a schematic cross-sectional view of a manufacturing process in a third example of the first embodiment.

FIG. 4 is a schematic cross-sectional view of a manufacturing process of the second example of the present invention and the first example of the embodiment.

FIG. 5 is a schematic cross-sectional view of a manufacturing process of an application example of the first embodiment of the second embodiment.

FIG. 6 is a schematic cross-sectional view of a manufacturing process in a second example of the second embodiment.

FIG. 7 is a schematic cross-sectional view of a manufacturing process of an application example of the second embodiment of the second embodiment.

FIG. 8 is a schematic sectional view of a manufacturing process according to a third example of the present invention and a first example of the embodiment.

FIG. 9 is a schematic cross-sectional view of a manufacturing process of an application example of the first example of the third embodiment.

FIG. 10 is a schematic cross-sectional view of a manufacturing step of the second example of the third embodiment.

FIG. 11 is a schematic cross-sectional view of a manufacturing process of an application example of the second example of the third embodiment.

FIG. 12 is a schematic cross-sectional view of a manufacturing process for describing an example of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

101,201,301,401 Semi-insulating GaAs
Substrates 102, 104, 106, 106A, 106B, 202
A, 202B, 204, 302A, 302B, 304,
402,404 GaAs layers 103,105,105A, 105B, 203,30
3,403,404 AlGaAs layers 107,207A, 207B, 307A, 307B, 4
07 Alignment mark 108 Alignment mark formation planned areas 109a, 109b, 109c, 209A, 209B,
309A, 309B, 409 EB mark 110a, 110b, 110c, 210A, 210B,
310A, 310B, 410 Recesses 111, 211A, 211B, 311A, 311B, 4
11 Ohmic metal 112a, 112b, 112c, 212Aa, 212A
b, 212Ba, 212Bb, 312Aa, 312A
b, 312Ba, 312Bb, 412 Source electrode 113a, 113b, 113c, 213Aa, 213A
b, 213Ba, 213Bb, 313Aa, 313A
b, 313Ba, 313Bb, 413 Drain electrode 114, 214A, 214B, 314A, 314B
Gate metal 115a, 115b, 115c, 215Aa, 215A
b, 215Ba, 215Bb, 315Aa, 315A
b, 315Ba, 315Bb, 415 Gate electrode 121, 122a, 122b, 122c, 123a, 1
23b, 123c, 223a, 223b, 226, 22
7,323a, 323b, 328,329,421,4
22, 423, 424 photoresist film patterns 125a, 125b, 125c, 225a, 225b,
325a, 325b, 425 EB resist film pattern 231A, 231B WSi film 240A, 240B, 337A, 337B, 339A,
339B Opening 332A, 332B SiO ₂ film 433 Conductor film

Continued on front page F term (reference) 2H096 AA25 EA02 EA06 HA13 HA14 HA23 5F046 AA09 AA26 EA12 EA13 EA14 EA18 EA20 EA23 EA26 EB01 5F056 FA06 5F102 GB01 GC01 GD01 GJ05 GR04 GR10 GR12 GS01 GT03 HC16 HC1

Claims (17)

[Claims] A first layer comprising at least one of Group III and Group V on a surface of a semiconductor substrate;
A second layer comprising at least a group III and a first layer;
Forming a first laminated film composed of a third layer composed of a compound semiconductor of the above, and a fourth layer composed of a stopper layer on the surface of the third layer, having the same constitution as that of the first compound semiconductor; Forming a second laminated film composed of a second layer composed of a second compound semiconductor having a required film thickness of the component and a fifth layer composed of the first photoresist film pattern as a mask. Layer and the fourth layer are sequentially anisotropically etched to form a first alignment mark (for photolithography) and a (for EB lithography) made of the second laminated film on the surface of the first laminated film. Forming an alignment mark formation region (of the second alignment mark); and forming the third and fifth alignment masks using another photoresist film pattern covering at least the first alignment mark as a mask.
Is selectively anisotropically etched to form a second alignment mark (E
Forming a B mark) and forming a recess in the surface of the first laminated film. 2. a step of forming the first stacked film on a surface of the semiconductor substrate, forming the second stacked film on a surface of the first stacked film; Forming the first alignment mark and the region where the alignment mark is to be formed by anisotropic etching using a resist film pattern as a mask; and, after removing the first photoresist film pattern, at least the first photoresist film pattern. Using the second photoresist film pattern covering the alignment mark as a mask,
Selectively anisotropically etching the first layer to form the second alignment mark in the region where the alignment mark is to be formed, and simultaneously forming the recess in the surface of the first laminated film; After removing the photoresist film pattern, an ohmic metal is formed on the entire surface using the third photoresist film pattern as a mask, and the third photoresist film pattern is lifted off to form a source and a source made of the ohmic metal. The first ohmic electrode for the drain is
Forming a gate metal on the entire surface using the EB resist film pattern as a mask, and lifting off the EB resist film pattern to form a gate electrode made of the gate metal in the recess. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the steps of: A step of forming the first laminated film on a surface of the semiconductor substrate, forming the second laminated film on a surface of the first laminated film; Forming the first alignment mark and the region where the alignment mark is to be formed by anisotropic etching using a resist film pattern as a mask; and, after removing the first photoresist film pattern, at least the first photoresist film pattern. Using the second photoresist film pattern covering the alignment mark as a mask,
Selectively anisotropically etching the layer to form the second alignment mark in a region where the alignment mark is to be formed, and simultaneously forming the recess in the surface of the first stacked film; 2 after removing the photoresist film pattern 2
Forming a gate metal on the entire surface by using the B resist film pattern as a mask, lifting off the EB resist film pattern to form a gate electrode made of the gate metal in the recess, and forming a third photoresist film pattern. Using the mask as a mask, an ohmic metal is formed on the entire surface, and the third photoresist film pattern is lifted off to form source and drain ohmic electrodes made of the ohmic metal on the surface of the first laminated film. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the steps of: 4. A step of forming the first laminated film on a surface of the semiconductor substrate, and forming the second laminated film on a surface of the first laminated film; Forming the first alignment mark and the region where the alignment mark is to be formed by anisotropic etching using a resist film pattern as a mask; and, after removing the first photoresist film pattern, at least the first photoresist film pattern. An ohmic metal is formed on the entire surface by using the second photoresist film pattern covering the alignment mark as a mask, and the third photoresist film pattern is lifted off to form source and drain ohmic electrodes made of the ohmic metal. Forming on the surface of the first laminated film; and a third photoresist covering at least the first alignment mark. The third and fifth layers are selectively anisotropically etched using the resist film pattern as a mask to form the second alignment mark in the alignment mark formation scheduled region and at the same time as forming the first laminated film. Forming the recess in the surface; removing the third photoresist film pattern;
Forming a gate metal on the entire surface by using the B resist film pattern as a mask, and lifting off the EB resist film pattern to form a gate electrode made of the gate metal in the recess. 2. The method for manufacturing a semiconductor device according to claim 1. 5. The semiconductor device according to claim 1, wherein the semiconductor substrate is a semi-insulating GaAs substrate, the second layer is an AlGaAs layer, and the fourth layer is a compound semiconductor layer containing Al or In as a component. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 6. A step of forming a layer having at least an upper surface made of a compound semiconductor on a surface or a surface of a semiconductor substrate, forming a conductor film on the entire surface, and using the first photoresist film pattern as a mask. The conductor film is anisotropically etched to form a first alignment mark (for photolithography) and a second alignment mark (for EB lithography) made of the conductor film on the surface of the semiconductor substrate. Mark), and at the same time, forming a recess opening in the conductive film on the surface of the layer; and a second photoresist film pattern covering at least the first and second alignment marks. Forming a recess in the surface of the layer by etching the layer to a required depth using the opening and the mask as a mask. Manufacturing method. 7. A step of forming the layer on the surface or on the surface of the semiconductor substrate and forming the conductor film on the entire surface, and anisotropic etching using the first photoresist film pattern as a mask. Forming the first alignment mark and the second alignment mark and the opening; and removing the first photoresist film pattern, and then forming the second photoresist film pattern and the opening. Forming the recess by etching using a mask, further etching and removing the conductive film using the second photoresist film pattern as a mask, and removing the second photoresist film pattern. An ohmic metal is formed on the entire surface using the third photoresist film pattern as a mask, and the third photoresist film pattern is removed. Forming an ohmic electrode for the source and the drain made of the ohmic metal on the surface of the layer by forming a gate metal on the entire surface using the EB resist film pattern as a mask; Forming a gate electrode made of the gate metal in the recess by lifting off the semiconductor device. 8. A step of forming the layer on the surface or on the surface of the semiconductor substrate and forming the conductor film on the entire surface, and anisotropic etching using the first photoresist film pattern as a mask. Forming the first alignment mark and the second alignment mark and the opening; and removing the first photoresist film pattern, and then forming the second photoresist film pattern and the opening. Forming the recess by etching using a mask, further removing the conductive film by etching using the second photoresist film pattern as a mask, and removing E by removing the second photoresist film pattern.
Forming a gate metal on the entire surface by using the B resist film pattern as a mask, lifting off the EB resist film pattern to form a gate electrode made of the gate metal in the recess, and forming a third photoresist film pattern. Forming an ohmic metal as a mask over the entire surface, lifting off the third photoresist film pattern, and forming source and drain ohmic electrodes made of the ohmic metal on the surface of the layer. 7. The method for manufacturing a semiconductor device according to claim 6, wherein: 9. The method for manufacturing a semiconductor device according to claim 6, wherein said semiconductor substrate is made of a semi-insulating GaAs substrate, and said layer is made of a GaAl layer. 10. The semiconductor substrate comprises a semi-insulating GaAs substrate, and the layer comprises a first layer comprising at least one of Group III and Group V, at least an I-th layer.
9. The method of manufacturing a semiconductor device according to claim 6, wherein the semiconductor device is a laminated film including a second layer containing Group II and a third layer formed of the compound semiconductor. Method. 11. The first layer constituting the laminated film comprises a first compound semiconductor layer, the second layer comprises an AlGaAs layer which is a second compound semiconductor layer, and the third layer 11. The method of manufacturing a semiconductor device according to claim 10, wherein the semiconductor device comprises a GaAs layer having a thickness corresponding to a required depth of the recess. 12. A semiconductor substrate comprising:
Forming a layer having at least an upper surface made of a compound semiconductor and forming an insulating film over the entire surface; selectively anisotropically etching the insulating film using the first photoresist film pattern as a mask; Anisotropically etching the surface or on the surface of the semiconductor substrate and the layer until the layer has a first predetermined depth,
A first (for photolithography) penetrating the conductor film
The first opening for forming an alignment mark of (E) and (E)
Forming a second opening for forming a second alignment mark (for B lithography) on or on the surface of the semiconductor substrate, and simultaneously forming a recess in the surface of the layer; and covering at least the recess Using the second photoresist film pattern and the first and second openings as masks, a second
Is further selectively anisotropically etched on the surface or the surface of the semiconductor substrate until a required depth is reached, and the first alignment mark and the second alignment mark (EB) are formed on the surface or the surface of the semiconductor substrate. Forming a mark). 13. The step of forming the layer on a surface or on the surface of the semiconductor substrate, forming the insulating film on the entire surface, and performing the anisotropic etching using the first photoresist film pattern as a mask. Forming the first opening and the second opening and the recess; removing the first photoresist film pattern; and then removing the second photoresist film pattern and the first and second openings. Forming the first alignment mark and the second alignment mark by anisotropic etching using a portion as a mask; and selectively etching the insulating film after removing the second photoresist film pattern. Removing step, using the third photoresist film pattern as a mask, forming an ohmic metal on the entire surface, and forming the third photoresist film pattern Forming an ohmic electrode for the source and the drain made of the ohmic metal on the surface of the layer by forming a gate metal on the entire surface using the EB resist film pattern as a mask; Forming a gate electrode made of the gate metal in the recess by lifting off the gate electrode.
The manufacturing method of the semiconductor device described in the above. 14. A step of forming the layer on the surface or the surface of the semiconductor substrate, forming the insulating film on the entire surface, and performing the anisotropic etching using the first photoresist film pattern as a mask. Forming the first opening and the second opening and the recess; removing the first photoresist film pattern; and then removing the second photoresist film pattern and the first and second openings. Forming the first alignment mark and the second alignment mark by anisotropic etching using a portion as a mask; and selectively etching the insulating film after removing the second photoresist film pattern. Removing step; forming a gate metal on the entire surface using the EB resist film pattern as a mask; lifting off the EB resist film pattern; Forming a gate electrode made of metal in the recess; forming an ohmic metal on the entire surface using the third photoresist film pattern as a mask; lifting off the third photoresist film pattern to remove the ohmic metal from the ohmic metal; Forming the ohmic electrodes for source and drain on the surface of the layer. 15. The method according to claim 12, wherein said semiconductor substrate is made of a semi-insulating GaAs substrate, and said layer is made of a GaAl layer. 16. The semiconductor device according to claim 16, wherein the semiconductor substrate is a semi-insulating GaAs substrate, and the layer is a first layer including at least one of Group III and Group V, and at least an I-th layer.
15. The manufacturing method of a semiconductor device according to claim 12, wherein the semiconductor device is a laminated film including a second layer containing Group II and a third layer composed of the compound semiconductor. Method. 17. The semiconductor device according to claim 17, wherein the layer is formed of the laminated film, the first layer is formed of a first compound semiconductor layer, the second layer is formed of an AlGaAs layer which is a second compound semiconductor layer, 17. The method according to claim 16, wherein the third layer comprises a GaAs layer having a thickness corresponding to a required depth of the recess.