JP2000346909A - Internal voltage monitoring circuit - Google Patents

Internal voltage monitoring circuit

Info

Publication number
JP2000346909A
JP2000346909A JP11159095A JP15909599A JP2000346909A JP 2000346909 A JP2000346909 A JP 2000346909A JP 11159095 A JP11159095 A JP 11159095A JP 15909599 A JP15909599 A JP 15909599A JP 2000346909 A JP2000346909 A JP 2000346909A
Authority
JP
Japan
Prior art keywords
voltage
comparator
internal
internal voltage
monitored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11159095A
Other languages
Japanese (ja)
Inventor
Katsuhiko Shishido
勝彦 宍戸
Toshihiko Sakai
俊彦 堺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP11159095A priority Critical patent/JP2000346909A/en
Publication of JP2000346909A publication Critical patent/JP2000346909A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To enhance the reliability of an internal voltage monitoring circuit by comparing a reference voltage which is provided at the outside with an internal voltage and obtaining a linear value. SOLUTION: A power supply voltage 21 and a resistance division part 22 are connected to a comparator 24. The comparator 24 is connected to a reference voltage 23 from the outside of a microprocessor, and it is connected to a multiplexer 25. A value which changes the reference voltage 23 at the outside and which is compared with an internal voltage by the comparator 24 can select the voltage of an element which is to be monitored by the control signal of the multiplexer 25. Each voltage is outputted as a linear value. When it is compared with the internal voltage by the comparator 24, an error which is caused by an external noise or the like can be suppressed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、マイクロプロセッ
サ等に使用され、内部電圧をモニタする回路に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for monitoring an internal voltage used in a microprocessor or the like.

【0002】[0002]

【従来の技術】最近では低消費電力化等のため、1つの
LSI中に、それぞれの回路を異なる電源電圧で動作させ
ることが一般に行われる。この際、それぞれの電源電圧
をLSI外部から与える方法もあるが、外部端子数を減ら
すため、外部から与えられた1つの電源電圧から他の電
源電圧を生成する方法が広くとられている。
2. Description of the Related Art Recently, to reduce power consumption and the like, one
In an LSI, it is common practice to operate each circuit at a different power supply voltage. At this time, there is a method of supplying each power supply voltage from the outside of the LSI. However, in order to reduce the number of external terminals, a method of generating another power supply voltage from one externally supplied power supply voltage is widely used.

【0003】このような手法を採る場合、正確に意図し
た電源電圧が生成されているか、検査時等にモニタする
ことが行われる。
When such a method is adopted, it is monitored during an inspection or the like whether an intended power supply voltage is generated accurately.

【0004】図1は、従来のマイクロプロセッサの内部
電圧をモニタする回路の概略図である。同図において電
源電圧11は、マイクロプロセッサ外部から印加する電
源電圧であり、抵抗分割12は、電源電圧、或いは昇圧
された電圧を内部回路1、内部回路2等々で使用するた
め、抵抗分割12により分圧していることを示してい
る。また、メモリセル13は書き込み時の電圧、消去時
の電圧、或いは読み出し時の電圧をモニタしていること
を示している。メモリセルの値は、センスアンプを介し
てデジタル値で判定する。
FIG. 1 is a schematic diagram of a circuit for monitoring the internal voltage of a conventional microprocessor. In the figure, a power supply voltage 11 is a power supply voltage applied from the outside of the microprocessor, and a resistance division 12 is used by the resistance division 12 in order to use a power supply voltage or a boosted voltage in the internal circuit 1, the internal circuit 2, and the like. This indicates that partial pressure is applied. Further, it indicates that the memory cell 13 monitors a voltage at the time of writing, a voltage at the time of erasing, or a voltage at the time of reading. The value of the memory cell is determined by a digital value via a sense amplifier.

【0005】以上の構成をもつ従来の内部電圧モニタ回
路は、選択したい内部電圧をモニタする際、外部の出力
端子14で直接モニタするという構成になっている。
The conventional internal voltage monitoring circuit having the above configuration is configured to directly monitor the internal voltage to be selected at the external output terminal 14 when monitoring the internal voltage to be selected.

【0006】[0006]

【発明が解決しようとする課題】内部電圧モニタ回路に
おいては、ノイズ等によって内部電圧測定値が変化しな
いことが要求される。ところが図1に示した従来の内部
電圧モニタ回路では、外部に出力端子14を設け内部電
圧をモニタしている。この方法では前記出力端子14か
らのノイズ等の外的要因で誤判定する可能性があった。
In the internal voltage monitor circuit, it is required that the measured internal voltage does not change due to noise or the like. However, in the conventional internal voltage monitor circuit shown in FIG. 1, an output terminal 14 is provided outside to monitor the internal voltage. In this method, there is a possibility that an erroneous determination is made due to an external factor such as noise from the output terminal 14.

【0007】また、内部のA/Dコンバータを使用する場
合においても、出力電圧がA/Dのビット精度に律速する
ため、正確な値が測定できなかった。
Further, even when an internal A / D converter is used, an accurate value cannot be measured because the output voltage is limited by the A / D bit precision.

【0008】本発明はかかる課題に鑑み、ノイズ等の影
響で誤判定せず、結果として信頼性を高めることを目的
とする。
The present invention has been made in consideration of the above problems, and has as its object to improve the reliability without erroneous determination due to the influence of noise or the like.

【0009】[0009]

【課題を解決するための手段】この課題を解決するため
に本発明の内部電圧モニタ回路は、電源電圧の分圧、昇
圧、メモリセル電圧を測定するために、外部にリファレ
ンス電圧を備える。前記リファレンス電圧と前記内部電
圧をコンパレートすることで、リニアな値を得ることを
特徴とするものである。
In order to solve this problem, an internal voltage monitor circuit according to the present invention includes an external reference voltage for measuring a divided voltage, a boosted voltage of a power supply voltage, and a memory cell voltage. A linear value is obtained by comparing the reference voltage and the internal voltage.

【0010】[0010]

【発明の実施の形態】(実施の形態1)図2は、本発明
の内部電圧モニタ回路の実施の形態における構成図であ
り、以下に本発明の実施の形態について図面を用いて説
明する。
(Embodiment 1) FIG. 2 is a configuration diagram of an embodiment of an internal voltage monitor circuit of the present invention. The embodiment of the present invention will be described below with reference to the drawings.

【0011】図2に示すように、マイクロプロセッサを
構成する要素である電源電圧21、前記電源電圧21を
内部回路1、内部回路2等で使用するため分圧する抵抗
分割22を示している。また、マイクロプロセッサ外部
から印加するリファレンス電圧23、電圧モニタしたい
素子と前記外部リファレンス電圧23とコンパレートす
るコンパレータ24、コンパレートした値を選択するマ
ルチプレクサ25を示している。
As shown in FIG. 2, a power supply voltage 21, which is a component of the microprocessor, and a resistor divider 22 for dividing the power supply voltage 21 for use in the internal circuit 1, the internal circuit 2 and the like are shown. Also shown are a reference voltage 23 applied from outside the microprocessor, an element to be monitored, a comparator 24 for comparing with the external reference voltage 23, and a multiplexer 25 for selecting a compared value.

【0012】電源電圧21と抵抗分割22は、コンパレ
ータ24と接続している。電源電圧21と抵抗分割22
に接続されたコンパレータ24は、マイクロプロセッサ
外部からリファレンス電圧23と接続され、各々接続さ
れたコンパレータ24はマルチプレクサ25に接続して
いる。外部リファレンス電圧23を変化させ、コンパレ
ータ24とコンパレートした値はマルチプレクサ25の
制御信号26によってモニタしたい素子の電圧を選択で
きる。各々の電圧値はリニアな値として出力され、コン
パレータ24とコンパレートすることで外的ノイズ等の
要因による誤差が抑えられる。
The power supply voltage 21 and the resistor divider 22 are connected to a comparator 24. Power supply voltage 21 and resistance divider 22
Are connected to a reference voltage 23 from outside the microprocessor, and the connected comparators 24 are connected to a multiplexer 25. The value obtained by changing the external reference voltage 23 and comparing with the comparator 24 can select the voltage of the element to be monitored by the control signal 26 of the multiplexer 25. Each voltage value is output as a linear value, and by comparing with the comparator 24, an error due to a factor such as external noise is suppressed.

【0013】内部電圧モニタしない際は、外部リファレ
ンス電圧23はトライステートバッファ27の制御信号
によって切り離すことが出来るという構成になってい
る。
When the internal voltage is not monitored, the external reference voltage 23 can be cut off by the control signal of the tri-state buffer 27.

【0014】(実施の形態2)図3は、本発明の内部電
圧モニタ回路の実施の形態における構成図であり、以下
に本発明の実施の形態について図面を用いて説明する。
(Embodiment 2) FIG. 3 is a block diagram of an embodiment of an internal voltage monitor circuit of the present invention. The embodiment of the present invention will be described below with reference to the drawings.

【0015】図3に示すように、フラッシュメモリを構
成するメモリセル31を示している。また、マイクロプ
ロセッサ外部から印加するリファレンス電圧32、電圧
モニタしたいメモリセル31はゲート、ソース、ドレイ
ンの電圧とコンパレートするコンパレータ33に接続さ
れ、前記コンパレータ33はコンパレートした値を選択
するマルチプレクサ34に接続される。外部リファレン
ス電圧32を変化させ、コンパレータ33とコンパレー
トした値はマルチプレクサ34の制御信号35によって
モニタしたいメモリセルの電圧を選択できる。各々の電
圧値はリニアな値として出力され、コンパレータ33と
コンパレートすることで外的ノイズ等の要因による誤差
が抑えられる。
FIG. 3 shows a memory cell 31 constituting a flash memory. Further, a reference voltage 32 applied from outside the microprocessor and a memory cell 31 to be monitored are connected to a comparator 33 which compares the voltage with the gate, source and drain, and the comparator 33 sends a signal to a multiplexer 34 for selecting a compared value. Connected. The value obtained by changing the external reference voltage 32 and comparing with the comparator 33 can select the voltage of the memory cell to be monitored by the control signal 35 of the multiplexer 34. Each voltage value is output as a linear value, and by comparing with the comparator 33, an error due to a factor such as external noise is suppressed.

【0016】内部電圧モニタしない際は、外部リファレ
ンス電圧32はトライステートバッファ36の制御信号
によって切り離すことが出来るという構成になってい
る。
When not monitoring the internal voltage, the external reference voltage 32 can be cut off by the control signal of the tri-state buffer 36.

【0017】[0017]

【発明の効果】以上のように、本発明の内部電圧モニタ
回路はマイクロプロセッサの命令によりCPUを動作さ
せ、マルチプレクサを用いて内部電圧モニタしたい素子
を任意に選択出来、コンパレータを用いて、外部のリフ
ァレンス電圧とコンパレートすることで、内部の電圧
(電源電圧の分圧、昇圧、メモリセル電圧)を精度良く
リニアに測定でき、且つ外的ノイズ等で誤作動しない製
品を提供するものである。
As described above, the internal voltage monitor circuit of the present invention can operate the CPU in accordance with the instruction of the microprocessor, arbitrarily select the element whose internal voltage is to be monitored using the multiplexer, and use the comparator to control the external voltage. By providing a comparison with a reference voltage, it is possible to provide a product that can accurately and linearly measure an internal voltage (voltage division, boosting of a power supply voltage, and a memory cell voltage) and that does not malfunction due to external noise or the like.

【図面の簡単な説明】[Brief description of the drawings]

【図1】従来の内部電圧モニタ回路を含むマイクロプロ
セッサのブロック図
FIG. 1 is a block diagram of a microprocessor including a conventional internal voltage monitor circuit.

【図2】本発明の内部電圧モニタ回路を含むマイクロプ
ロセッサのブロック図
FIG. 2 is a block diagram of a microprocessor including an internal voltage monitor circuit of the present invention.

【図3】本発明の内部電圧モニタ回路を含むマイクロプ
ロセッサのブロック図
FIG. 3 is a block diagram of a microprocessor including an internal voltage monitor circuit according to the present invention.

【符号の説明】[Explanation of symbols]

21 電源電圧 22 抵抗分割 23 リファレンス電圧 24 コンパレータ 25 マルチプレクサ 26 制御信号 27 トライステートバッファ 31 メモリセル 32 リファレンス電圧 33 コンパレータ 34 マルチプレクサ 35 制御信号 36 トライステートバッファ Reference Signs List 21 power supply voltage 22 resistance division 23 reference voltage 24 comparator 25 multiplexer 26 control signal 27 tri-state buffer 31 memory cell 32 reference voltage 33 comparator 34 multiplexer 35 control signal 36 tri-state buffer

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 2G032 AA03 AB19 AC03 AD01 AK14 AK15 AL05 5F038 BB05 BG03 BH19 DF04 DF06 DT12 EZ20  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G032 AA03 AB19 AC03 AD01 AK14 AK15 AL05 5F038 BB05 BG03 BH19 DF04 DF06 DT12 EZ20

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 マイクロプロセッサ内部にコンパレータ
を設け、電圧モニタしたい素子と、前記コンパレータと
を接続し、更にマイクロプロセッサ外部から電圧モニタ
したい前記素子に接続された前記コンパレータにリファ
レンス電圧を接続し、前記リファレンス電圧の電圧値を
変化させ、前記コンパレータとコンパレートした、リニ
アな値をモニタすることを特徴とする内部電圧モニタ回
路。
A comparator is provided inside a microprocessor, an element whose voltage is to be monitored is connected to the comparator, and a reference voltage is connected to the comparator connected to the element whose voltage is to be monitored from outside the microprocessor. An internal voltage monitor circuit which changes a voltage value of a reference voltage and monitors a linear value which is compared with the comparator.
【請求項2】 マイクロプロセッサ内部にコンパレータ
を設け、電圧モニタしたい複数の素子と、前記コンパレ
ータとを接続し、更にマイクロプロセッサ外部から電圧
モニタしたい前記素子に接続された前記コンパレータに
リファレンス電圧を接続し、前記リファレンス電圧の電
圧値を変化させ、前記コンパレータとコンパレートし
た、リニアな値をマルチプレクサに接続し、複数の電圧
モニタしたい前記素子から前記マルチプレクサで電圧モ
ニタしたい素子を選択出来ることを特徴とする内部電圧
モニタ回路。
2. A comparator is provided inside a microprocessor, a plurality of elements to be monitored for voltage are connected to the comparator, and a reference voltage is connected to the comparator connected to the element to be monitored for voltage from outside the microprocessor. Changing the voltage value of the reference voltage, connecting a linear value that is compared with the comparator to a multiplexer, and selecting an element whose voltage is to be monitored by the multiplexer from a plurality of elements whose voltage is to be monitored. Internal voltage monitor circuit.
JP11159095A 1999-06-07 1999-06-07 Internal voltage monitoring circuit Pending JP2000346909A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11159095A JP2000346909A (en) 1999-06-07 1999-06-07 Internal voltage monitoring circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11159095A JP2000346909A (en) 1999-06-07 1999-06-07 Internal voltage monitoring circuit

Publications (1)

Publication Number Publication Date
JP2000346909A true JP2000346909A (en) 2000-12-15

Family

ID=15686137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11159095A Pending JP2000346909A (en) 1999-06-07 1999-06-07 Internal voltage monitoring circuit

Country Status (1)

Country Link
JP (1) JP2000346909A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI407128B (en) * 2009-09-15 2013-09-01 Himax Analogic Inc Digital circuit and voltage detecting circuit therein
US9146598B2 (en) 2013-01-30 2015-09-29 Renesas Electronics Corporation Monitor circuit, semiconductor integrated circuit, semiconductor device, and method of controlling power supply voltage of semiconductor device
US9960739B2 (en) 2015-06-22 2018-05-01 Rohm Co., Ltd. Semiconductor integrated circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI407128B (en) * 2009-09-15 2013-09-01 Himax Analogic Inc Digital circuit and voltage detecting circuit therein
US9146598B2 (en) 2013-01-30 2015-09-29 Renesas Electronics Corporation Monitor circuit, semiconductor integrated circuit, semiconductor device, and method of controlling power supply voltage of semiconductor device
US9647654B2 (en) 2013-01-30 2017-05-09 Renesas Electronics Corporation Monitor circuit, semiconductor integrated circuit, semiconductor device, and method of controlling power supply voltage of semiconductor device
US9960739B2 (en) 2015-06-22 2018-05-01 Rohm Co., Ltd. Semiconductor integrated circuit

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