JP2000341284A - Atm connecting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently accommodate a non-ATM communication terminal in an ATM network by storing sampled values of a data signal and a control signal from a non-ATM terminal in a buffer memory area of the same plane synchronously, reading out and composing them into an ATM cell and sending the cell out to the ATM network. SOLUTION: When an ATM device receives communication data and a control signal from a non-ATM communication terminal, a connecting device 103 samples the control signal in constant cycles and writes sampled values to a specific area of the same plane of a receiving buffer memory 206 synchronously with the communication data. A readout control part 208 reads out and sends them to an ATM cell conversion part 209, which composes an ATM cell in specific format and sends it out to the ATM network through an output interface 210. The ATM cell conversion part 209 monitors the state of sampled values and stops transmission to the ATM network once detecting a change, so that effective data transmission is not performed in case of a fault, etc., and unnecessary data discarding can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an existing non-ATM (Asyn
The present invention relates to a technology for accommodating a terminal device of a chronous transfer mode (asynchronous transfer mode) in an ATM network.

[0002]

2. Description of the Related Art In recent years, with the development of ATM networks, there are existing terminals that are not yet compatible with ATM (asynchronous transfer mode). Generally, when performing data communication between existing non-ATM terminals, a handshake for confirming the state of each other is performed by a control signal, and data transmission and reception are performed after a link is established between the terminals. FIG. 12 shows an example of the procedure by the handshake. Protocols related to these handshakes are standardized by ITU-T (Telecommunication Standardization Sector of the International Telecommunication Union), and V.24, V.35, and X.21 are typical examples. It should be noted that these standards also specify the formats of the transmission / reception data signal and the control signal.

[0003]

In recent years, with the development of the broadband ISDN (Integrated Services Digital Network) based on the ATM system, there is a problem that it is desired to efficiently accommodate existing non-ATM communication terminals in the ATM network. .

Furthermore, when data communication is performed between non-ATM terminals via an ATM network, how to handle control signals between non-ATM terminals becomes a problem. As a method to solve this problem, assuming that the control signal of the non-ATM terminal is always activated (ON) in the ATM network without transmitting and receiving the control signal, it is as if the control signal is transmitted and received. A technique for establishing a handshake in a pseudo manner by creating such a state is conceivable. In this way, a handshake can be established in a pseudo manner without transmitting / receiving a control signal, and only a data signal can be converted into an ATM cell by an ATM cell assembling / disassembling apparatus to transmit / receive a data signal.

[0005] However, in this method, the control signal is assumed to be always activated even when the communication partner terminal is disconnected due to a failure or the like. However, there is a problem that a data signal is transmitted without knowing that a failure has occurred, and as a result, the data signal is discarded.

Therefore, if data transmission and reception are performed between the terminals by the handshake, it is desirable to transfer not only a data signal but also a control signal via an ATM network. For example, a control signal and a data signal are treated as CBR (fixed transmission rate) signals, only the control signal is assembled into an ATM cell by AAL1 and transferred, and after a link is established between terminals by the control signal, the data signal is converted to AAL1. It is conceivable to assemble and transfer to an ATM cell according to the above.

However, in this case, since all control signals are transmitted each time, the efficiency of use of the transmission band is poor, and furthermore, in the case of data communication between terminals having a strict delay, the delay affects the terminal device. There is a problem that a timeout occurs and data signals cannot be transmitted / received normally.

[0008] Therefore, an object of the present invention is to solve the problem when connecting existing non-ATM terminals via an ATM network.

[0009]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a first aspect of the present invention is a connection device for connecting a communication terminal performing communication by handshake to an ATM network, the first device receiving a data signal from the communication terminal. Interface and
A second interface that receives a control signal from the communication terminal, a sampling unit that samples the control signal received at the second interface, and outputs a sample value of the control signal, and that the sampling unit outputs A synchronization unit that synchronizes the sample value of the control signal with the data signal received by the first interface unit, and stores the sample value of the control signal and the data signal synchronized by the synchronization unit A storage unit, a reading unit that reads the sample value of the control signal and the data signal stored in the storage unit, and the sample value of the control signal and the data signal that are read by the reading unit are the same. A storage unit that stores the control signal sample value and the data signal in the storage unit.
An ATM output interface for outputting M cells to the ATM network.

When the control signal monitoring section monitors the state of the control signal when storing the data signal in the payload field section, and the control signal monitoring section detects a change in the level of any of the control signals, the ATM signal is transmitted to the ATM. The cell assembling / disassembling unit writes the identifier of the changed control signal in the control signal trigger field unit, and the arithmetic unit determines the time from the start of storing the data signal in the payload field unit until the level of the control signal changes. It is obtained by calculation, and the calculation result is stored in the time information field of the ATM cell.

The storage section of the present invention comprises a data signal storage buffer area for storing a data signal, and a sample value storage buffer area for storing a sample value of a control signal. The sample value storage buffer area is characterized in that buffer areas of the same buffer size are divided into the same number of planes.

Further, the ATM cell of the present invention protects an ATM header, a payload field for storing the data signal, a sequence number field indicating the order in which the ATM cells are assembled, and the sequence number. A sequence number protection field portion, a control signal status field portion indicating a status of the control signal when storing the data signal in the payload field portion, and an identifier of a control signal having a changed level among a plurality of control signals. And a time information field for storing a time from when the data signal starts to be stored in the payload field until the level of the control signal changes.

Further, the present invention provides a third interface for receiving an ATM cell from an ATM network, and an ATM cell decomposing unit for decomposing the ATM cell received at the third interface and outputting a transmission control signal. A control unit that controls the output of the data signal from the ATM output interface based on the transmission control signal output by the ATM cell disassembly unit. At this time, the control signal is restored from the information stored in the control signal status field, the control signal trigger field, and the time information field of the ATM cell. In particular, in restoring the position where the control signal is inverted, the position from the position where the data signal is started to be stored in the payload to the position where the data signal is inverted is calculated based on the value of the time information field.

[0014] Further, the control unit of the present invention monitors the transmission control signal based on a specific cycle, and when the control signal changes, determines that the partner terminal has failed, and sends a signal from the ATM output interface to the failed terminal. By stopping the output of the data signal, data is prevented from being discarded.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention accommodates an existing non-ATM terminal device in an ATM device and performs communication between the non-ATM terminal devices. FIG. 1 shows a network configuration example of the present invention. The existing non-ATM terminal device 101 is connected to the ATM device 102. An existing non-ATM device with which the communication terminal 101 communicates
111 is connected to the ATM device 107. And ATM devices 102 and 107
Are connected to the ATM network 106 and constitute a network system as a whole. Further, the ATM devices 102 and 107 include at least connection devices 103 and 110, switching devices 104 and 109, and ATM line interface devices 105 and 108, respectively.

Next, a configuration example of the connection devices 103 and 110 according to the present invention will be described. FIG. 2 is a configuration block diagram showing one embodiment of the connection device 102 according to the present invention. As shown in FIG.
The connection device 102 includes a signal control unit 203, a storage unit 204, a read control unit 208, an ATM cell conversion unit 209, and an ATM output interface 210.

Further, the signal control section 203 comprises an interface 203A on the transmitting side and an interface 203B on the receiving side. As shown in FIG. 3, the transmission side interface 203A
S / P converter 301, FIFO memory 302, and parallel I / O port
303, a sampling unit 304, a timer 305, and a synchronization unit 306
Consists of

The storage unit 204 of the connection device comprises a reception buffer memory 206 and a transmission buffer memory 207, as shown in FIG. The reception buffer memory 206 and the transmission buffer memory 207 include data signal storage buffer areas 402 and 404 for storing data signals, and sample value storage buffer areas 403 and 403 for storing sample values of control signals, respectively.
405. Further, the data signal storage buffer areas 402 and 404 and the sample value storage buffer area 4
03, 405 has a configuration in which buffer areas of the same buffer size are divided into the same number of planes.

The ATM cell converter 209, as shown in FIG.
ATM cell assembling / disassembling unit 501, change point detecting unit 502, arithmetic unit 5
03, signal definition unit 504, buffer write control unit 505, AT
Determination section 506 for determining the state of the control signal stored in the M cell
Consists of

FIG. 6 shows an embodiment in which a control signal is transferred. An ER signal 601 in the figure is a signal indicating data terminal ready. The RS signal 602 is a signal indicating a transmission request. The DR signal 603 is a data set ready signal. The CS signal 604 is a signal indicating that transmission is possible. The CD signal 605 is a carrier detection signal. Hereinafter, the communication terminal 101
The operation of each device when a data communication request is issued from the communication terminal 111 to the communication terminal 111 will be described.

The communication terminal 101 turns on the data terminal ready 1200 according to the sequence shown in FIG.
Set to OFF. The connection device 103 turns on the STATUS part of the cell format shown in FIG.
Assuming that there is no data in the payload, the cell is immediately assembled with invalid data and transmitted. Upon receiving the request, the connection device 110 disassembles the cell, determines that the data terminal is ready 1200 ON, and turns on the data terminal ready of the communication terminal 111. In the same way, set the data set ready 12
01 ON, transmission request 1202, transmission enabled 1203, carrier detection 1204
And the sequence are processed, and the data signal can be transmitted and received.

The operation of the signal control section 203A shown in FIG. 3 will be described. When the data signal 201 transmitted by the communication terminal 101 is received by the signal control unit 203, the S / P conversion unit 301
To S / P conversion. The FIFO memory 302 stores the converted data signal. On the other hand, when data terminal ready ER601 and transmission request RS602, which are the control signals transmitted by communication terminal 101, are received by signal control section 203A, these control signals are converted into parallel I / O signals.
It is housed in port 303. The sampling unit 304 samples the states of the ER 601 and RS 602 accommodated in the parallel I / O port 303 at regular intervals, and obtains sample values ERA 610 and RS
Generate A611. The sampling cycle at this time is timer 30
5 is monitored by time.

Next, the synchronization unit 306 stores the data signal 201 and the sample values ERA610 and RSA611 in the FIFO memory 302,
Read synchronously from the sampling unit. In addition, the synchronization unit
A data buffer 306 writes the data signal 201 to the data signal storage buffer area 402 of the reception buffer memory 206, and on the other hand, stores sample values ERA610 and RSA611 in the reception buffer corresponding to the surface on which the data signal 201 is written to the data signal storage buffer area 402 The data is written to the storage surface of the sample value storage buffer area 403 in the area 206. In other words, write on the same side.

Here, the write timing will be described with reference to FIG. FIG. 7 shows an example in which the received data signal 201 and the control signal 202 are signal-
The timing when 203A writes to the reception buffer memory 206 is shown.

The sampling section 304 reads the state of the control signal 202 to be processed at a fixed period at a sample timing 701, and generates a sample value 205. In order to maintain the timing relationship between the sample timing 701 and the reception of the data signal 201, the sample signal storage buffer area of the (n + 1) plane is A sample value storage surface 403 is prepared, and writing of the sample value 205 to the sample value storage surface is performed on the same surface as the data signal storage surface.

For example, in the example of FIG. 7, when the data signal 201 for the buffer area corresponding to the plane 0 is accumulated, the sample value of the control signal 202 at the sample timing 701 is "1".
Therefore, the data signal 201 and the sample value “1” are synchronously written to the surface 0 of the data signal storage buffer area 402 and the sample value storage buffer area 403, respectively. At the next sample timing, the data signal 201 and the sample value “11” are written to the surface 1. As described above, the data signal 201 and the sample value 205 are written synchronously while the buffer storage surface is incremented by one.

As described above, when the data signal 201 and the sample value 602 are written synchronously, the read control unit 208
The data signal 201 and the sample values ERA610 and RSA611 stored in the data signal storage buffer area 402 and the sample value storage buffer area 403, respectively, are read and the ATM cell conversion unit 209 is read.
To send to.

The ATM cell converter 209 assembles and disassembles ATM cells having a format as shown in FIG. In the case where both the data signal and the control signal are transferred between the communication terminals as in the present invention, it is necessary to transfer both the data signal and the control signal while maintaining a certain timing relationship. It is preferable to transfer the data by AAL1. However, other methods can be adopted. FIG. 13 shows an example of converting CBR data into ATM cells. FIG. 14 shows the cell format of AAL1. AA
In L1, the ATM header 1400 and the AAL1 header are standardly determined to be 5 bytes and 1 byte, respectively. The unstructured data payload stores CBR data separated by 47 bytes. In the case of structured data, the payload is reduced by the amount of the pointer 1403.

The biggest difference from the conventional ATM cell format shown in FIG. 14 lies in the payload field. In the present invention, a control signal status field (STATUS) section 803 storing the status of a plurality of control signals in the payload field section (47 bytes or less) of the AAL1 and the level of the plurality of control signals are changed. Control signal trigger field (SIG TRG) unit 804 for storing the identifier of the object, and the level of the control signal changes after starting to store the data signal in the payload field unit when a change in level is detected in the control signal. It is characterized in that a time information field (TIME STAMP) unit 802 for storing the time up to is provided. Therefore, by providing these, the payload section 801 for storing the data signal has a size smaller than 47 bytes.

The ATM cell converter 209 stores the data signal 201 read by the read controller 208 in the payload field 801, and stores the sample values ERA 610 and RSA 611 in the control signal status field (STATUS) 803.

Further, the change point detecting section 502 outputs the sample value ERA
Monitor the status of 610 and RSA 611. The signal definition unit 504 defines a signal at which a change point is detected in advance using a binary value.
For example, if a change point is detected in the sample value RSA611,
The sample value RSA611 defined by the signal definition unit 504
Is output to the ATM cell assembling / disassembling unit 501. The ATM cell assembling / disassembling unit 501 converts a binary value corresponding to the sample value RSA611 into a control signal trigger field (SIG TRG).
Stored in the unit 804. When the change point detection unit 502 detects a change point, the calculation unit 503 calculates the time from the start of storing the data signal 201 in the payload field unit 801 to the detection of the change point, and disassembles the ATM cell assembly unit. Output to the unit 501. The ATM cell assembling / disassembling unit 501 stores the time until detection in the time information field (TIME STAMP) unit 802 as a binary value. Further, the ATM cell assembling / disassembling section 501 includes a sequence number field (SN) section 805 indicating the order in which the ATM cells 211 are assembled, a sequence number protection field (SNP) section 806 for protecting the sequence number, and an ATM header. Assemble the ATM cell format 808 with the part 807 inserted. When the ATM cell is assembled, the ATM cell converter 209
Is the ATM cell output interface 21
Output to 0. The ATM output interface 210 sends the ATM cellized data signal and control signal to the ATM network.

When the cell assembly is captured, the ATM cell conversion unit receives the data signal and the sample value from the data signal storage buffer area and the sample value storage buffer area of the reception buffer memory in a form synchronized with each other. However, at this time, the ATM cell conversion unit does not immediately start assembling the ATM cell, but starts assembling the ATM cell when data for one cell is accumulated. That is, if there is no change in the state of the sample value (at each control signal) received at that time, the state is displayed in the STATUS field of the 1-bit ATM cell format for each control signal. For example, if there are five types of control signals (ER, RS, DR, CS, and CD) as in the embodiment, the STATUS field has 5 bits. here,
Focusing only on the sample value RSA, when data for one cell accumulates and the ATM cell starts to be assembled, if there is no change in all bits in the received sample value RSA (all bits have the same value), only that value is displayed in the STATUS field part. I do. At this time, an identifier “time stamp invalid” defined by the signal definition unit is displayed in the SIG TRG field. (The TIME STAMP field is don't care). on the other hand,
If the state of the sample value RSA has changed, the value after the change is displayed in the STATUS field. Also, SIG TR
In the G field, the identifier of 'RS change' defined by the signal definition unit is displayed, and in the TIME STAMP field, the time at which the change is detected after the data signal is started to be stored in the payload is calculated by the arithmetic unit. Display as information.

An example of the SIG TRG field is shown below.

Bit2 bit1 bit0 0 0 0 Undefined 0 0 1 No change (time stamp invalid) 0 1 0 ER change 0 1 1 DR change 1 0 0 RS change 1 0 1 CD change 1 1 1 1 cell Next, the operation of the communication terminal 111 which is the partner of the communication terminal 101 will be described. Control signals ER610, R input from ATM network 106
When the connection device 110 receives the ATM cell 220 including S611, the ATM
The ATM cell assembling / disassembling unit 501 of the cell conversion unit 209 converts the data signal 221 from the payload field 801 into the STATUS field.
From 803, control signals such as sample values ERA901 and RSA902
The identifier of the control signal whose level has changed from the TRG field and the time from when the data is started to be stored in the payload field portion from the TIME STAMP 802 field until the level of the control signal changes are extracted and decomposed.

The write control unit 505 transmits the data signal 221 at the timing synchronized with the transmission buffer memory 207 in order to match the timing of sending the data signal to the communication terminal 111 with the timing of reproducing the sample value. And sample values ERA901 and RSA902 respectively in the transmission buffer memory 207.
To the data signal storage buffer area 404 and the sample value storage buffer area 405. Note that the ATM cell disassembly / assembly unit 501 outputs SIG TRG 804 and TIME STAMP 802 to the determination unit 506.

The determination unit 506 constantly monitors the SIG TRG 804, and when the SIG TRG 804 becomes an identifier indicating a change in the control signal, specifies the control signal that has changed from the identifier and further determines the time when the change has occurred. From the STAMP 802, the time point of the change is calculated by calculation. TIME STAMP80
2 is the time difference between the time when the data signal was stored in the payload of the ATM cell and the time of the change, so that the time difference is used together with the identifier of the control signal that has changed and the write control unit 50.
5, the write control unit 505 identifies the control signal that has changed from the identifier, and reproduces the correct control signal by inverting the state of the control signal at the change time of the control signal.

The read control unit 208 stores the data signal 221 and the sample values ERA901 and RSA902 in the data signal storage buffer area.
404, read from the same surface of the sample value storage buffer area 405, output the read data signal 221 to the FIFO memory 902, and output the sample values ERA 901 and RSA 902 to the signal reproducing unit 904. The signal reproducing unit 904 outputs the sample values ERA901, RSA90
The status of 2 is monitored by the timer 905, and the original control signals ER7603 and RS604 are reproduced at a constant reproduction timing.

The data signal 221 and the reproduced control signal ER6
03, RS 604 is read out at a synchronized timing by the timing generation unit 902, and the data signal 201 is read by the P / S conversion unit 90.
The P / S conversion is performed at 1, and the control signals ER603 and RS604 are output to the communication terminal B111 via the parallel I / O port 903.

FIG. 10 shows the timing relationship when the data signal 221 and the sample value 222 written in the data signal storage buffer area 404 and the sample value storage buffer area 405 are restored to the original data signal 221 and the control signal 223. Show.

The ATM cell assembling / disassembling unit 501 controls the data signal storage buffer area 404 and the sample value storage buffer area 4 of the transmission buffer memory in order to match the transmission timing of the data signal to the line with the reproduction timing of the sample value.
The data signal and the reproduced sample value are written to the data signal storage buffer area and the sample value storage buffer area, respectively, in a format synchronized in the plane 05.

When reproducing the sample value, the signal control unit 203B reproduces the sample value of the sample value storage buffer area 405 on the same plane as the data signal storage surface of the data signal storage buffer area 404, and reproduces the data signal and the sample value. Match the playback timing.

For example, in the example of FIG. 10, since the sample value changes from 0 to 1 on the surface 0 and the sample value changes from 1 to 0 on the surface 2, the data signal is changed for each surface by the reproduction timing 801. 513 and the control signal 508 are restored. As described above, the data signal and the sample value are sequentially read for each plane from the data signal storage buffer area 404 and the sample value storage buffer area 405, and the signal reproduction unit 904 described above is read.
Reproduces the data signal and the control signal.

Thus, the control signals ER601 and R
When the communication terminal 111 that has received S602 recognizes, for example, that the ER 601 is on and the level of the RS 602 has changed from off to on, the communication terminal 111 transmits a CS (transmittable signal) 604 together with a valid data signal.
And the level of a CD (carrier detection signal) 605 is changed from off to on and transmitted to the communication terminal 101. The connection device 110 according to the present invention is assembled into an ATM cell in the same manner as described above,
Send to ATM network. As described above, data communication is performed between the communication terminal A101 and the communication terminal B111.

FIG. 8 shows another embodiment in which the control signal is transferred. In this case, the data signal 201, the CS (control signal) 801 and the I (indication signal) 802 are transmitted in the same manner as in the embodiment shown in FIG.
Assembled into the M cell format 908, and data communication is performed between communication terminals. FIG. 11 shows another embodiment in which the control signal is transferred.

For example, when the communication terminal 101 wants to perform data communication with the communication terminal 111, the communication terminal 101 turns on C (control) 1101 to display a call. This C signal 110
1 is transmitted to the connection apparatus 103, and the connection apparatus converts the cell into an ATM cell by the method described above and transmits the cell to the other party. ATM with connecting device 110
The cell is decomposed, the C signal 1101 is reproduced, and output to the communication terminal 111. On the other hand, when the incoming call is possible, the communication terminal 111 turns on the I (indication) 1102 from off to display that the incoming call is ready. Similarly, the connection device 111
Converts the I signal 1102 into an ATM cell and transmits it to the other party based on the method described above. The communication terminal 101 is a communication terminal 111
Confirm that the I signal 1102 from is turned on, and transmit the data signal.

[0046]

As described above, according to the present invention, an existing terminal device can be accommodated in an ATM network. Also,
When a data signal and a control signal received from a terminal device are converted into an ATM cell and transferred to an ATM network, the data signal and the control signal can be transferred simultaneously in the same ATM cell format, so that the delay can be reduced. Furthermore, since the ATM cells containing only the control signal are reduced as much as possible and the data is transmitted in the same ATM cell as the data, the required transmission band can be reduced, and the band can be used effectively. In addition, if the communication partner terminal is disconnected due to a failure or the like before communication between the terminals, the transmission source terminal does not transmit valid data, so that unnecessary data discard can be eliminated.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a communication network when a terminal device is accommodated in an ATM network.

FIG. 2 is a diagram showing a configuration example of a connection device according to the present invention.

FIG. 3 is a diagram illustrating a configuration example of a signal control unit according to the present invention.

FIG. 4 is a diagram illustrating a configuration example of a storage unit according to the present invention.

FIG. 5 is a configuration block diagram of an ATM cell conversion unit according to the present invention.

FIG. 6 is a diagram illustrating an example of a control signal sequence.

FIG. 7 is a diagram showing an example of timing when writing a data signal and a sampling signal to a buffer memory;

FIG. 8 is a diagram showing an ATM cell format according to the present invention.

FIG. 9 is a diagram showing a configuration example of a signal control unit of the connection device according to the present invention.

FIG. 10 is a diagram showing an example of timing when writing a data signal and a sampling signal to a buffer memory.

FIG. 11 is a diagram illustrating an example of a control signal sequence.

FIG. 12 is a diagram showing a sequence example according to a handshake protocol.

FIG. 13 is an explanatory diagram of conversion between CBR data and ATM cells using AAL1.

FIG. 14 is an explanatory diagram of an AAL1 cell format.

[Explanation of symbols]

 101,111 terminal equipment, 102,107 ATM equipment, 103,110 connection equipment, 104,109 switching equipment, 106 ATM network, 201,221 data signal line group, 202,223 control signal line group, 203 signal control unit, 206 buffer memory 207: a transmission buffer memory; 209: an ATM cell conversion unit; 208: a read control unit; 210: an ATM output interface.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Toshiyuki Tajima 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Communication Systems Division of Hitachi, Ltd. (72) Inventor Makoto Tezuka 180 Totsukacho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Address: Hitachi Communication Systems Co., Ltd. (72) Koji Iino 2-6-2 Otemachi, Chiyoda-ku, Tokyo Within Hitachi Information Network Inc. (72) Shigeo Arai 216 Totsukacho, Totsuka-ku, Yokohama-shi, Kanagawa Address F-term (Reference) 5K018 AA01 BA03 CA01 5K030 GA01 GA04 HA10 HB11 HB29 JA06 JT02 KA02 KA13 KA21 KX11 9A001 BB03 BB04 CC07 CZ04 JJ18 KK56

Claims (5)

[Claims] An ATM connection device for connecting a communication terminal performing communication by handshake to an ATM network, a first interface for receiving a data signal from the communication terminal, and receiving a control signal from the communication terminal. A second interface that samples the control signal received by the second interface and outputs a sample value of the control signal; and a sample value of the control signal output by the sampling unit and the second unit. A synchronization unit that synchronizes the data signal received by the interface unit, a storage unit that stores the sample value of the control signal and the data signal that are synchronized by the synchronization unit, and a storage unit that stores the data signal. A reading unit that reads out the sampled value of the control signal and the data signal that have been read out, before reading by the reading unit. A storage unit for storing the sample value of the control signal and the data signal in the same ATM cell; and storing the sample value of the control signal and the data signal in the storage unit and storing the ATM cell in the ATM network. Output to
A characterized by having an ATM output interface
TM connection device. 2. The ATM connection device according to claim 1, wherein said storage unit comprises a data signal storage buffer area for storing said data signal, and a sample value storage buffer area for storing a sample value of said control signal. 2. The ATM connection device according to claim 1, wherein the data signal storage buffer area and the sample value storage buffer area have buffer areas of the same buffer size divided into the same number of planes. 3. The ATM connection device according to claim 1, wherein the ATM cell comprises an ATM header, a payload field for storing the data signal, and a sequence number field indicating the order in which the ATM cells are assembled. A sequence number protection field section for protecting the sequence number, a control signal state field section indicating a state of the control signal when the data signal is stored in the payload field section, and a plurality of the control signals, A control signal trigger field portion for storing an identifier of a changed level, and a time information field portion for storing a time from when the data signal starts to be stored in the payload field portion until the level of the control signal changes. 2. The ATM connection device according to claim 1, further comprising: 4. The ATM connection device according to claim 1, wherein
A third interface for receiving an ATM cell from the ATM network; an ATM cell disassembly unit for disassembling the ATM cell received on the third interface and outputting a transmission control signal; and an ATM cell disassembly unit. The ATM connection device according to claim 1, further comprising: a control unit that controls output of the data signal from the ATM output interface based on the transmission control signal output by the ATM connection interface. 5. The connection device according to claim 4, wherein the control unit monitors the transmission control signal based on a specific cycle, and when the transmission control signal changes, from the ATM output interface to the ATM network. An ATM connection device for stopping output of the data signal.