JP2000340599A - Wire-bonding device and wire-bonding method using the same - Google Patents

Wire-bonding device and wire-bonding method using the same

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Publication number
JP2000340599A
JP2000340599A JP11146859A JP14685999A JP2000340599A JP 2000340599 A JP2000340599 A JP 2000340599A JP 11146859 A JP11146859 A JP 11146859A JP 14685999 A JP14685999 A JP 14685999A JP 2000340599 A JP2000340599 A JP 2000340599A
Authority
JP
Japan
Prior art keywords
wire bonding
electrode
wire
plasma
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11146859A
Other languages
Japanese (ja)
Inventor
Yasushi Taniguchi
靖 谷口
Masayuki Kono
公志 河野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP11146859A priority Critical patent/JP2000340599A/en
Publication of JP2000340599A publication Critical patent/JP2000340599A/en
Pending legal-status Critical Current

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent decrease in yield due to defective wire bonding in manufacture of a semiconductor package. SOLUTION: This device 12 has a plasma jet section 50 and a wire-bonding section 51. The plasma jet section 50 has a coaxial dual structure composed of an outer dielectric tube 23 and an inner dielectric tube 22. A cone section 23a has a conical electrode 27 and the inner dielectric tube 22 has a high-frequency electrode 26 therein. A plasma gas, generated by the plasma jet section 50, is blown off from a gas jet outlet 25. The wire bonding section 51 has a wire supply section 35 for supplying an Au wire 32 to a capillary 31, a capillary driving section 37 composed of an arm driving mechanism 39 for laterally and vertically supporting the capillary 31 and a stage 40 for driving the arm driving mechanism 39, and a torch electrode 34 electrically connected to a DC power source 41 and driven by a torch electrode driving section 38.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、ワイヤボンディン
グにおける被接続表面をクリーニングしてからワイヤボ
ンディングを行うワイヤボンディング装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wire bonding apparatus for cleaning a surface to be connected in wire bonding and then performing wire bonding.

【０００２】[0002]

【従来の技術】近年、ＬＳＩデバイスの高集積化、高速
化に対応したＬＳＩパッケージとしてＢＧＡ（Ｂａｌｌ
Ｇｒｉｄ Ａｒｒａｙ）パッケージが実用化されてい
る。図５に最も一般的なＢＧＡパッケージ５１１の模式
的断面図を示す。このＢＧＡパッケージ５１１はＯＭＰ
ＡＣ（Ｏｖｅｒ Ｍｏｌｄｅｄ Ｐａｄ ＡｒｒａｙＣ
ａｒｒｉｅｒ）タイプのものである。スルーホール５０
８の形成された基板５０１の表面５２０には、電極５０
４を有する導電部材からなる回路パターン５０２が形成
されており、その上面にはソルダーレジスト５０３が形
成されている。ソルダーレジスト５０３の上面には半導
体チップ５０６が搭載されており、Ａｕワイヤからなる
ボンディング線６３２で回路パターン５０２の電極５０
４とワイヤボンディングにより電気的に接続されてい
る。また、半導体チップ５０６及びワイヤボンディング
部は封止樹脂層５０９により樹脂封止されている。一
方、基板５０１の裏面５２１側に複数のボール状のはん
だバンプ１０が形成されている。2. Description of the Related Art In recent years, BGA (Ball) has been developed as an LSI package corresponding to high integration and high speed of LSI devices.
(Grid Array) package has been put to practical use. FIG. 5 shows a schematic sectional view of the most general BGA package 511. This BGA package 511 is OMP
AC (Over Molded Pad Array C
(arrier) type. Through hole 50
8 is formed on the surface 520 of the substrate 501 on which the electrodes 8 are formed.
A circuit pattern 502 made of a conductive member having a pattern No. 4 is formed, and a solder resist 503 is formed on an upper surface thereof. A semiconductor chip 506 is mounted on the upper surface of the solder resist 503, and the electrodes 50 of the circuit pattern 502 are bonded by bonding wires 632 made of Au wires.
4 is electrically connected by wire bonding. The semiconductor chip 506 and the wire bonding portion are resin-sealed by a sealing resin layer 509. On the other hand, a plurality of ball-shaped solder bumps 10 are formed on the back surface 521 side of the substrate 501.

【０００３】以上のような構成のＢＧＡパッケージ５１
１は、構造が簡単であり、かつ、はんだバンプ１０を基
板５０１の裏面５２１に設けることではんだバンプ１０
のボールピッチを広くすることが可能となり、基板実装
が容易になることから高密度実装技術として注目されて
いる。[0003] The BGA package 51 having the above configuration
1 is that the structure is simple and the solder bumps 10 are provided on the back surface 521 of the substrate 501.
Has been attracting attention as a high-density mounting technology because it is possible to increase the ball pitch and to facilitate mounting on a substrate.

【０００４】半導体チップ５０６と基板５０１の電極５
０４とを電気的に接続する従来のワイヤボンディングに
関して以下に説明する。The semiconductor chip 506 and the electrode 5 of the substrate 501
The conventional wire bonding for electrically connecting the wire bonding device 04 is described below.

【０００５】図６に従来のワイヤボンディング装置６０
０の概略構成図を示す。FIG. 6 shows a conventional wire bonding apparatus 60.
0 shows a schematic configuration diagram.

【０００６】ワイヤボンディング装置６００は、キャピ
ラリ６３１にＡｕワイヤ６３２を供給するワイヤ供給部
６３５と、キャピラリ６３１を支持するアーム駆動機構
６３９及びアーム駆動機構６３９を上下左右方向に駆動
させるステージ６４０とからなるキャピラリ駆動部６３
７と、直流電源６４１に電気的に接続され、トーチ電極
駆動部６３８により駆動されるトーチ電極６３４とを有
する。The wire bonding apparatus 600 includes a wire supply section 635 for supplying an Au wire 632 to the capillary 631, an arm driving mechanism 639 for supporting the capillary 631, and a stage 640 for driving the arm driving mechanism 639 in the vertical and horizontal directions. Capillary drive unit 63
7 and a torch electrode 634 electrically connected to the DC power supply 641 and driven by the torch electrode driving unit 638.

【０００７】上述のような構成の従来のワイヤボンディ
ング装置６００において、まず、キャピラリ６３１より
導出されたＡｕワイヤ６３２の先端にトーチ電極６３４
を近付け、両者間の放電スパークでＡｕワイヤ６３２の
先端に溶融塊であるＡｕボール６３３を形成する。これ
は、接地されたＡｕワイヤ６３２に、高電圧の印加され
たトーチ電極６３４を所望の距離まで近付けると、両者
間に放電スパークが発生してＡｕワイヤ６３２の先端部
が溶けてＡｕボール６３３が形成されるものである。次
に、キャピラリ６３１はＡｕワイヤ６３２の先端のＡｕ
ボール６３３を半導体チップ５０６の被接続面に一次ボ
ンディングする。次に、Ａｕワイヤ６３２を繰り出しな
がらキャピラリ６３１が移動して、電極５０４にＡｕワ
イヤ６３２の一部を二次ボンディングする。次に、キャ
ピラリ６３２から導出されたワイヤの一部が切断され
る。切断されたキャピラリ６３１側のＡｕワイヤ６３２
の先端は、再びトーチ電極６３４が近付けられ、放電ス
パークによりＡｕボール６３３が形成されて、次のワイ
ヤボンディングにむけて待機する。[0007] In the conventional wire bonding apparatus 600 having the above-described configuration, first, the torch electrode 634 is attached to the tip of the Au wire 632 led out from the capillary 631.
And an Au ball 633 as a molten mass is formed at the tip of the Au wire 632 by a discharge spark between the two. This is because, when the torch electrode 634 to which a high voltage is applied is brought close to a grounded Au wire 632 to a desired distance, a discharge spark occurs between the two and the tip of the Au wire 632 melts, and the Au ball 633 is melted. Is formed. Next, the capillary 631 is connected to the Au wire 632 at the distal end of the Au wire 632.
The ball 633 is primarily bonded to the connection surface of the semiconductor chip 506. Next, the capillary 631 moves while feeding out the Au wire 632, and a part of the Au wire 632 is secondarily bonded to the electrode 504. Next, a part of the wire led out of the capillary 632 is cut. Au wire 632 on cut capillary 631 side
The torch electrode 634 is approached again at the tip of, and the Au ball 633 is formed by the discharge spark, and waits for the next wire bonding.

【０００８】以上のようにしてワイヤボンディングがな
される際、ワイヤボンディングされる被接続面である電
極５０４にフラックスやレジストのような有機物や銅な
どの金属あるいはそれらの酸化物が存在するとワイヤボ
ンディングがされなかったりワイヤボンディング強度の
劣る接合が行われる恐れがあった。[0008] When wire bonding is performed as described above, if there is an organic substance such as flux or resist, or a metal such as copper, or an oxide thereof, on the electrode 504 to be connected, the wire bonding is performed. There is a possibility that bonding with poor wire bonding strength may be performed.

【０００９】このような有機物を除去する方法として、
ウエット法やオゾン照射や紫外線照射によるドライ洗浄
法が知られている。ウエット法は有機物洗浄後に洗浄剤
を除去するリンス工程と基板乾燥工程が必要で大がかり
な設備を必要とする。一方、ドライ法では分子量の大き
な有機物の除去能力が低く十分な洗浄効果が期待できな
い。As a method for removing such organic matter,
A wet cleaning method and a dry cleaning method using ozone irradiation or ultraviolet irradiation are known. The wet method requires a rinsing step and a substrate drying step for removing the cleaning agent after the organic substance cleaning, and requires extensive equipment. On the other hand, in the dry method, the ability to remove organic substances having a large molecular weight is low, and a sufficient cleaning effect cannot be expected.

【００１０】このため、プラズマを用いて有機物、無機
物を除去する方法が提案されている。例えば、特開昭５
８−１４７１４３号公報には、ＩＣチップをパッケージ
ングする際、減圧下でマイクロ波放電による酸素プラズ
マで、リードフレーム面を処理することによりリードフ
レームと樹脂の密着性を改善する方法が開示されてい
る。また、特開平４−１１６８３７号公報には、プラズ
マエッチング装置に１〜１０［Ｔｏｒｒ］の水素ガスを
導入し放電することにより酸化物を除去することが開示
されている。特開平５−１６０１７０号公報には、減圧
した処理室内で電極に高周波電圧を印加し、アルゴン酸
素プラズマあるいは水素還元プラズマによりリードフレ
ームをエッチングする方法が開示されている。一方、減
圧下ではなく大気圧下でプラズマを発生させることを利
用して、特開平３−１３３１２５号公報には、フッ素ガ
スを含有したガスを大気圧放電させて基板に照射しアッ
シングする方法が開示されており、また、特開平９−２
３５６８６号公報にはフッ素含有ガスを用いた低温大気
圧プラズマをはんだ接合する面に照射することにより、
接合面の清浄化とはんだ含有層の形成によりはんだ接合
性を改善する方法が開示されている。For this reason, there has been proposed a method of removing organic and inorganic substances using plasma. For example, JP
Japanese Patent Application Laid-Open No. 8-147143 discloses a method for improving the adhesion between a lead frame and a resin by packaging a lead frame with oxygen plasma generated by microwave discharge under reduced pressure when packaging an IC chip. I have. Further, Japanese Patent Application Laid-Open No. 4-16837 discloses that oxides are removed by introducing and discharging hydrogen gas of 1 to 10 [Torr] into a plasma etching apparatus. Japanese Patent Application Laid-Open No. 5-160170 discloses a method in which a high-frequency voltage is applied to an electrode in a decompressed processing chamber, and a lead frame is etched by argon oxygen plasma or hydrogen reduction plasma. On the other hand, by utilizing the fact that plasma is generated under atmospheric pressure instead of under reduced pressure, Japanese Patent Application Laid-Open No. 3-133125 discloses a method in which a gas containing fluorine gas is discharged at atmospheric pressure to irradiate a substrate and ash the substrate. And JP-A-9-2
Japanese Patent No. 35686 discloses that low-temperature atmospheric pressure plasma using a fluorine-containing gas is applied to a surface to be soldered,
There is disclosed a method for improving solder jointability by cleaning a joint surface and forming a solder-containing layer.

【００１１】[0011]

【発明が解決しようとする課題】しかしながら、従来の
プラズマ放電を用いた表面処理方法では、特開昭５８−
１４７１４３号公報や特開平４−１１６８３７号公報に
開示されているように減圧された環境下で放電を形成す
るために、真空装置が必要となり装置の大型化に伴う半
導体パッケージのコストアップの問題がある。また、真
空中あるいは減圧下のプラズマ放電では、励起種に対し
て電子とイオンが多いために、半導体素子の表面処理に
用いる場合には、素子へのダメージの問題も無視できな
い。一方、大気圧プラズマを用いる場合は、設備的に大
がかりなものを必要とせず有利である。しかしながら、
電極と被処理材との間で放電を発生させるものは、放電
状態が不均一になりやすく、電極と被処理材間の距離や
被処理材の材質に制限が加えられる。電極間で放電を形
成させる場合でも、特開平３−１３３１２５号公報の方
法では、本発明が対象とする局所的、微小な領域のエッ
チングやアッシングには適していない。However, the conventional surface treatment method using plasma discharge is disclosed in
As disclosed in Japanese Patent Application Laid-Open No. 147143/1992 and Japanese Patent Application Laid-Open No. 4-116837, a vacuum device is required to form a discharge under a reduced pressure environment. is there. In a plasma discharge under vacuum or reduced pressure, electrons and ions are more than excited species. Therefore, when used for surface treatment of a semiconductor element, the problem of damage to the element cannot be ignored. On the other hand, the use of atmospheric pressure plasma is advantageous because no large-scale equipment is required. However,
When a discharge is generated between the electrode and the material to be processed, the discharge state is likely to be non-uniform, and the distance between the electrode and the material to be processed and the material of the material to be processed are limited. Even when a discharge is formed between the electrodes, the method disclosed in Japanese Patent Application Laid-Open No. 3-133125 is not suitable for etching or ashing of a local or minute area targeted by the present invention.

【００１２】さらに、従来のいずれの表面処理方法にし
ても、プラズマ処理を行ってからワイヤボンディングま
でに時間間隔がある場合には、被接合面への不純物の再
付着や酸化膜の形成によりプラズマ処理の効果が低下し
てしまい、ワイヤボンディングの不良に起因する半導体
パッケージの歩留りの低さが問題となる場合があった。Further, in any of the conventional surface treatment methods, if there is a time interval between the time when the plasma treatment is performed and the time when the wire bonding is performed, the plasma is formed by re-adhering impurities to the surface to be joined or forming an oxide film. In some cases, the effect of the processing is reduced, and the yield of the semiconductor package is low due to the defective wire bonding.

【００１３】そこで本発明は、上記課題を解決するた
め、半導体パッケージの歩留りを高めるワイヤボンディ
ングを行うワイヤボンディング装置及び該ワイヤボンデ
ィング装置によるワイヤボンディング方法を提供するこ
とを目的とする。Accordingly, an object of the present invention is to provide a wire bonding apparatus for performing wire bonding for improving the yield of a semiconductor package and a wire bonding method using the wire bonding apparatus.

【００１４】[0014]

【課題を解決するための手段】上記目的を達成するため
本発明のワイヤボンディング装置は、半導体チップの電
極と、前記半導体チップを搭載した基板の電極とをボン
ディングワイヤにより電気的に接続するワイヤボンディ
ング手段と、前記ワイヤボンディング手段による接続の
前に、前記各電極の表面を清浄するための、外部より供
給されたガスをプラズマの状態に励起させるとともに、
前記プラズマを前記各電極に照射させるプラズマ発生手
段とを有する。In order to achieve the above object, a wire bonding apparatus according to the present invention provides a wire bonding apparatus for electrically connecting an electrode of a semiconductor chip and an electrode of a substrate on which the semiconductor chip is mounted by bonding wires. Means, and before connection by the wire bonding means, for cleaning the surface of each electrode, while exciting a gas supplied from the outside to a plasma state,
Plasma generating means for irradiating each of the electrodes with the plasma.

【００１５】また、本発明のワイヤボンディング方法
は、本発明のワイヤボンディング装置を用いたワイヤボ
ンディング方法であって、前記プラズマ発生手段により
放射される前記プラズマにより前記半導体チップの電極
と前記基板の電極とのうちの少なくとも前記基板の電極
の１つのみの表面を清浄する清浄工程と、前記清浄工程
により清浄された前記各電極及び前記清浄された電極と
電気的に接続されるべき電極とにワイヤボンディングを
行うワイヤボンディング工程とを有し、前記清浄工程と
前記ワイヤボンディング工程とを交互に繰り返して、全
ての前記各電極のワイヤボンディングを行う。Further, the wire bonding method of the present invention is a wire bonding method using the wire bonding apparatus of the present invention, wherein the electrode of the semiconductor chip and the electrode of the substrate are formed by the plasma radiated by the plasma generating means. A cleaning step of cleaning at least one surface of at least one of the electrodes of the substrate; and a wire connected to each of the electrodes cleaned by the cleaning step and an electrode to be electrically connected to the cleaned electrode. And a wire bonding step of performing bonding. The cleaning step and the wire bonding step are alternately repeated to perform wire bonding of all the electrodes.

【００１６】また、本発明のワイヤボンディング方法
は、本発明のワイヤボンディング装置を用いたワイヤボ
ンディング方法であって、前記プラズマ発生手段により
放射される前記プラズマにより複数の前記電極の表面を
清浄する清浄工程と、前記清浄工程により清浄された前
記各電極及び前記清浄された各電極と電気的に接続され
るべき各電極とにワイヤボンディングを行うワイヤボン
ディング工程とを有する。The wire bonding method according to the present invention is a wire bonding method using the wire bonding apparatus according to the present invention, wherein the surface of the plurality of electrodes is cleaned by the plasma emitted by the plasma generating means. And a wire bonding step of performing wire bonding to each of the electrodes cleaned by the cleaning step and each of the electrodes to be electrically connected to the cleaned electrodes.

【００１７】上記の通りの本発明のワイヤボンディング
装置及び該ワイヤボンディング装置によるワイヤボンデ
ィング方法は、ワイヤボンディング装置自身が半導体チ
ップ及び基板の電極の表面を清浄するための、プラズマ
を電極の表面に照射するプラズマ発生手段を有している
ため、電極の表面の清浄とワイヤボンディングとを連続
して行える。よって、プラズマ発生手段で電極の表面を
清浄してからワイヤボンディング手段でワイヤボンディ
ングを行うまでの時間間隔を短縮することができる。As described above, in the wire bonding apparatus and the wire bonding method using the wire bonding apparatus according to the present invention, the wire bonding apparatus itself irradiates the surface of the electrode with the plasma for cleaning the surface of the electrode of the semiconductor chip and the substrate. Therefore, cleaning of the electrode surface and wire bonding can be performed continuously. Therefore, it is possible to reduce the time interval from cleaning the surface of the electrode by the plasma generating means to performing wire bonding by the wire bonding means.

【００１８】[0018]

【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.

【００１９】図１に本発明の一実施形態のワイヤボンデ
ィング装置１２の概略構成図を示す。FIG. 1 is a schematic configuration diagram of a wire bonding apparatus 12 according to one embodiment of the present invention.

【００２０】本実施形態のワイヤボンディング装置１２
は、プラズマジェット部５０とワイヤボンディング部５
１とから概略構成される。The wire bonding apparatus 12 of the present embodiment
Are the plasma jet unit 50 and the wire bonding unit 5
And 1.

【００２１】プラズマジェット部５０は、後述のＢＧＡ
パッケージ１１のワイヤボンディングがなされる被接合
面をプラズマエッチングにより清浄するためのものであ
る。このプラズマジェット部５０は、蓋２１にそれぞれ
の上部が接合された、外側誘電体管２３と内側誘電体管
２２とからなる同軸の二重構造のものであり、外側誘電
体管２３の円錐部２３ａには、接地された電極である円
錐状電極２７が備えられ、内側誘電体管２２の内部には
丸棒状の高周波電極２６が備えられている。また、蓋２
１にはガス導入路２８が備えられている。外側誘電体管
２３は、その上端が蓋２１により閉鎖されており、内側
誘電体管２２との間に環状空室２４が形成されており、
円錐状をなす下端の円錐部２３ａの先端は、プラズマを
噴出するためのガス噴出口２５が形成されている。な
お、ガス噴出口２５の口径は、後述の各電極のうちの１
つにのみプラズマを照射できる大きさのものである。内
側誘電体管２２は、その上端が開放されかつ下端は閉鎖
されている。高周波電極２６は、内側誘電体管２２内に
移動可能な状態で挿入されており、同軸ケーブルにより
不図示のインピーダンスマッチング回路を介して不図示
の高周波電源に接続されている。The plasma jet unit 50 includes a BGA
This is for cleaning the bonding surface of the package 11 where the wire bonding is performed by plasma etching. The plasma jet unit 50 has a coaxial double structure composed of an outer dielectric tube 23 and an inner dielectric tube 22 each having an upper portion joined to the lid 21. 23 a is provided with a conical electrode 27 which is a grounded electrode, and a round rod-shaped high-frequency electrode 26 is provided inside the inner dielectric tube 22. In addition, lid 2
1 is provided with a gas introduction path 28. The outer dielectric tube 23 has an upper end closed by a lid 21, and an annular cavity 24 is formed between the outer dielectric tube 23 and the inner dielectric tube 22.
A gas outlet 25 for ejecting plasma is formed at the tip of the conical lower portion 23a having a conical shape. The diameter of the gas ejection port 25 is one of the electrodes described later.
Only one can be irradiated with plasma. The inner dielectric tube 22 has an open upper end and a closed lower end. The high-frequency electrode 26 is movably inserted into the inner dielectric tube 22, and is connected to a high-frequency power source (not shown) by a coaxial cable via an impedance matching circuit (not shown).

【００２２】ワイヤボンディング部５１は、プラズマジ
ェット部５０により、清浄され被接合面にＡｕワイヤ３
２をワイヤボンディングするためのものである。このワ
イヤボンディング部５１は、キャピラリ３１に、接地さ
れたＡｕワイヤ３２を供給するワイヤ供給部３５と、キ
ャピラリ３１を支持するアーム駆動機構３９及びアーム
駆動機構３９を上下左右方向に駆動させるステージ４０
とからなるキャピラリ駆動部３７と、直流電源４１に電
気的に接続され、トーチ電極駆動部３８により駆動され
るトーチ電極３４とを有する。The wire bonding section 51 is cleaned by the plasma jet section 50 and the Au wire 3
2 for wire bonding. The wire bonding unit 51 includes a wire supply unit 35 that supplies the grounded Au wire 32 to the capillary 31, an arm driving mechanism 39 that supports the capillary 31, and a stage 40 that drives the arm driving mechanism 39 in the vertical and horizontal directions.
And a torch electrode 34 electrically connected to the DC power supply 41 and driven by the torch electrode driving unit 38.

【００２３】以下に、本発明のワイヤボンディング装置
１２による、ＯＭＰＡＣタイプのＢＧＡパッケージ１１
の製造工程におけるワイヤボンディングに関して詳細に
説明する。An OMPAC type BGA package 11 using the wire bonding apparatus 12 of the present invention will be described below.
A detailed description will be given of the wire bonding in the manufacturing process.

【００２４】図２（ａ）〜図２（ｃ）に本発明のワイヤ
ボンディング装置１２によるワイヤボンディング工程を
含む、各製造工程におけるＢＧＡパッケージ１１の模式
的断面図を示す。FIGS. 2A to 2C are schematic cross-sectional views of the BGA package 11 in respective manufacturing steps including a wire bonding step by the wire bonding apparatus 12 of the present invention.

【００２５】図２（ａ）は、本発明のワイヤボンディン
グ装置１２により処理がなされる状態にまで作製された
第１段階のＢＧＡパッケージ１１ａの模式的断面図であ
る。FIG. 2A is a schematic cross-sectional view of a first-stage BGA package 11a manufactured up to a state where processing is performed by the wire bonding apparatus 12 of the present invention.

【００２６】以下に第１段階のＢＧＡパッケージ１１ａ
の製造工程の概略を説明する。The first stage BGA package 11a
An outline of the manufacturing process will be described.

【００２７】回路パターン２ａは、銅箔の膜が両面に形
成されたガラスエポキシ製の基板１に、スルーホール孔
あけとスルーホールメッキ工程によってスルーホール８
が形成された後、フォトリソグラフィ手法によって、表
面１ａに信号用電極２、パワー用電極４及びグランド用
電極５を有する回路パターン２ａのパターニングが行わ
れることで形成されたものである。表面１ａ側の回路パ
ターン２ａと裏面１ｂ側の不図示の導体回路とはスルー
ホール８により接続されている。また、表面１ａの回路
パターン２ａ上にはソルダーレジスト３の層が形成され
ているとともに、裏面１ｂ側の導体回路上にも不図示の
ソルダーレジスト層が形成されている。ソルダーレジス
ト３は、半導体チップ６と第１段階のＢＧＡパッケージ
１１ａとを電気的に接続するためのはんだ接合工程にお
いて、第１段階のＢＧＡパッケージ１１ａの回路自体を
はんだメッキの熱からの保護あるいは腐食から保護する
目的を有する。また、近年、電極間の狭ピッチ化に伴う
はんだブリッジの問題を解決する目的からソルダーレジ
ストダムとしても利用されている。さらに、ソルダーレ
ジスト３は、例えば基板１が吸湿性の高い基板材料の場
合はその耐湿性を向上させることや、Ｃｕからなる導体
回路の化学的安定性を向上させることを目的として形成
される他、特に基板１の表面１ａ側に形成されるソルダ
ーレジスト３は、ワイヤボンディングされる金メッキ領
域を制限し低コスト化を図ることを目的として形成され
る。ソルダーレジスト３の材料特性としては、光照射に
よりレジスト被膜の露光部分に生じた化学反応を利用し
てパターンを形成するフォトレジストの内、解像性及び
被膜性能に優れたものが使用される。一般には、カルボ
ン酸を分子中に有する不飽和樹脂とポリエポキシ化合物
を主成分とする二液型の光硬化型の材料が用いられてい
る。回路パターン２ａの形成された基板１上にレジスト
を塗布した後、必要箇所にネガ型のフォトマスクを介し
て、感光するに十分の光エネルギをレジストに照射す
る。その後、炭酸ソーダ水溶液等のアルカリ性の現像液
で未露光部分を溶解除去し回路パターン２ａを形成した
後、加熱してカルボキシル基とエポキシ基とを反応させ
架橋度を高めると共にイオン形成基であるカルボキシル
基をエステル基に転換することにより硬化被膜の耐熱
性、耐薬品性の被膜を形成する。第１段階のＢＧＡパッ
ケージ１１ａは、基板１の表面１ａに回路パターン２ａ
を、また裏面１ｂに導体回路をそれぞれパターニングし
た後、ソルダーレジスト３が約６０μｍ全面に塗布され
る。次に、半導体チップ６からワイヤボンディング配線
される部分のソルダーレジスト３を前述のフォトリソグ
ラフィ工程によりパターニング、除去する。次に、ソル
ダーレジスト３を除去した回路パターン２ａにＮｉ／Ａ
ｕメッキを施した後、基板に半導体チップ６をマウント
し、第１段階のＢＧＡパッケージ１１ａが作製されるこ
ととなる。The circuit pattern 2a is formed on a substrate 1 made of glass epoxy having a copper foil film formed on both sides by a through-hole drilling and a through-hole plating process.
Is formed, the circuit pattern 2a having the signal electrode 2, the power electrode 4 and the ground electrode 5 on the surface 1a is patterned by photolithography. The circuit pattern 2a on the front surface 1a side and the conductor circuit (not shown) on the back surface 1b side are connected by through holes 8. Further, a layer of solder resist 3 is formed on the circuit pattern 2a on the front surface 1a, and a solder resist layer (not shown) is formed on the conductor circuit on the back surface 1b. The solder resist 3 protects or corrodes the circuit itself of the first-stage BGA package 11a from the heat of solder plating in a soldering process for electrically connecting the semiconductor chip 6 and the first-stage BGA package 11a. With the purpose of protecting from In recent years, it has also been used as a solder resist dam for the purpose of solving the problem of a solder bridge caused by a narrow pitch between electrodes. Furthermore, the solder resist 3 is formed for the purpose of, for example, improving the moisture resistance when the substrate 1 is a substrate material having high hygroscopicity, or improving the chemical stability of a conductor circuit made of Cu. In particular, the solder resist 3 formed on the surface 1a side of the substrate 1 is formed for the purpose of limiting the gold-plated region to be wire-bonded and reducing the cost. As a material characteristic of the solder resist 3, a photoresist which forms a pattern by using a chemical reaction generated in an exposed portion of the resist film by light irradiation and has excellent resolution and film performance is used. In general, a two-part photocurable material mainly containing an unsaturated resin having a carboxylic acid in a molecule and a polyepoxy compound is used. After a resist is applied on the substrate 1 on which the circuit pattern 2a is formed, light energy sufficient to expose the resist is irradiated to a necessary portion through a negative photomask. Thereafter, an unexposed portion is dissolved and removed with an alkaline developing solution such as an aqueous sodium carbonate solution to form a circuit pattern 2a, and then heated to react the carboxyl group and the epoxy group to increase the degree of crosslinking and to form a carboxyl ion as an ion-forming group. By converting the group into an ester group, a cured film having heat resistance and chemical resistance is formed. The first-stage BGA package 11a includes a circuit pattern 2a on the surface 1a of the substrate 1.
After patterning the conductor circuit on the back surface 1b, a solder resist 3 is applied to the entire surface of about 60 μm. Next, the portion of the solder resist 3 to be wire-bonded from the semiconductor chip 6 is patterned and removed by the photolithography process described above. Next, Ni / A is applied to the circuit pattern 2a from which the solder resist 3 is removed.
After u plating, the semiconductor chip 6 is mounted on the substrate, and the first stage BGA package 11a is manufactured.

【００２８】図２（ｂ）は、本発明のワイヤボンディン
グ装置１２により、ワイヤボンディングがなされた状態
の第２段階のＢＧＡパッケージ１１ｂの模式的断面図で
ある。FIG. 2B is a schematic sectional view of the BGA package 11b at the second stage in a state where wire bonding has been performed by the wire bonding apparatus 12 of the present invention.

【００２９】ところで、各電極の表面上にはレジストの
残査やＡｕ表面の酸洗浄時にメッキ浴に溶出したＣｕの
析出やその酸化物等がコンタミネーションとして存在し
ている。このようなコンタミネーションが存在するとワ
イヤボンディング時にボンディング不良が生じる。Incidentally, on the surface of each electrode, residues of resist and precipitation of Cu eluted into the plating bath at the time of acid cleaning of the Au surface and oxides thereof are present as contamination. The presence of such contamination causes bonding failure during wire bonding.

【００３０】各電極上のコンタミネーションを除去する
ために、プラズマジェット部５０によるプラズマエッチ
ングによりワイヤボンディングがなされる被接合面であ
る各電極の表面を清浄する。In order to remove the contamination on each electrode, the surface of each electrode, which is the surface to be bonded, is cleaned by plasma etching by the plasma jet unit 50.

【００３１】以下に一般的なエッチング及び大気圧下で
のプラズマエッチングに関して説明する。Hereinafter, general etching and plasma etching under atmospheric pressure will be described.

【００３２】大気圧下でプラズマを形成するための励起
源としては、高周波（ＲＦ）、マイクロ波等が用いられ
る。As an excitation source for forming plasma under atmospheric pressure, a radio frequency (RF), a microwave or the like is used.

【００３３】また、エッチングの方法としては、化学的
な反応性によるものと物理的に除去するもの、化学的な
反応と物理的な除去を組み合わせたものがある。化学的
な反応を利用するものとして、大気圧下では高周（Ｒ
Ｆ）プラズマによるエッチング、マイクロ波プラズマに
よるエッチング等がある。運動エネルギを持った粒子に
より物理的に除去する方法としては、プラズマスパッ
タ、イオンビームスパッタ法等がある。化学的反応性と
物理的除去を合わせた手法としては、反応性イオンエッ
チング法がある。エッチングガスとしては、Ａｒ、
Ｈ2、Ｎ2、ＣＦ4、Ｃ2Ｆ 6、Ｃ3Ｆ8、ＣＣｌ2Ｆ2、ＰＣ
ｌ3、ＣＢｒＦ3、ＣＣｌ4、Ｃｌ2、ＳＦ6等を主反応ガ
スとし、これに微量のＯ2、Ｎ2、Ｈ2Ｏ、Ａｉｒ等を添
加しても良い。微量ガスを添加すると、反応の活性化エ
ネルギを大幅に変化することができ、エッチング速度を
改善することができる。なお、エッチングガスはエッチ
ングする対象物質を化学的もしくは物理的に除去するの
に最適なものを選択すればよい。エッチング状態は、エ
ッチング時のプラズマもしくはイオンビームを発光分光
法にてモニターすることにより、その終点を決定するこ
とができる。例えば、Ａｕ上に存在するＣｕ量をＸＭＡ
（Ｘ−ｒａｙ Ｍｉｃｒｏ Ａｎａｌｙｚｅｒ）などの
表面分析装置により分析し、エッチング時間とＣｕ存在
量（除去量）及びワイヤボンディング強度の関係を予め
求めておき、最適なエッチング時間を設定する。As for the etching method, a chemical
Reactivity, physical removal, chemical
Some combine reaction and physical removal. scientific
In order to make use of a simple reaction, under an atmospheric pressure, a high circumference (R
F) Plasma etching, microwave plasma
Etching. Into particles with kinetic energy
A more physical removal method is plasma sputtering.
And an ion beam sputtering method. Chemical reactivity and
Physical removal combined with reactive ion etching
There is a ching method. As an etching gas, Ar,
HTwo, NTwo, CFFour, CTwoF 6, CThreeF8, CClTwoFTwo, PC
lThree, CBrFThree, CClFour, ClTwo, SF6Etc. the main reaction gas
And a small amount of OTwo, NTwo, HTwoAdd O, Air, etc.
May be added. Addition of a trace gas can cause activation of the reaction.
Energy can be changed drastically, and the etching rate can be increased.
Can be improved. The etching gas is etch
Chemical or physical removal of target substances
What is best is to select the best one. The etching state is
Emission spectroscopy of plasma or ion beam during etching
To determine the end point
Can be. For example, the amount of Cu existing on Au
(X-ray Micro Analyzer)
Analysis by surface analyzer, etching time and presence of Cu
Amount (removal amount) and wire bonding strength
The optimum etching time is set beforehand.

【００３４】大気圧下でのプラズマエッチングは、大気
圧下でプラズマ励起してグロー放電を形成して行われる
ので、減圧状態で行われる場合に比べて装置の構成が極
めて簡単であるという利点を有している。大気圧状態は
低電界で絶縁体であるが、直流、交流、インパルス等の
高電界を印加すると絶縁破壊を起こし電流が流れる。こ
の自続放電はコロナ放電、グロー放電、アーク放電に分
類する。平等電界の時には自続放電に移ると直ちに全路
破壊し、グロー放電もしくはアーク放電に移行する。し
かしながら、不平等電界の場合には、電界の強い局部の
み絶縁破壊され、コロナ放電が起こる。さらに強電界に
なると、全路破壊に発展する。通常、大気圧空気中では
全路破壊に移行するとき、グロー放電を経ずにアーク放
電に速やかに移行することが多い。このアーク放電の状
態では対象物が数千度の高温になるため低温プロセスと
ならない。Since plasma etching under atmospheric pressure is performed by exciting plasma under atmospheric pressure to form a glow discharge, the advantage that the structure of the apparatus is extremely simple as compared with the case where the plasma etching is performed under reduced pressure is provided. Have. Atmospheric pressure is an insulator at a low electric field, but when a high electric field such as direct current, alternating current, or impulse is applied, dielectric breakdown occurs and current flows. This self-sustaining discharge is classified into corona discharge, glow discharge, and arc discharge. In the case of a uniform electric field, the entire path is destroyed immediately after the transition to the self-sustaining discharge, and the transition to a glow discharge or an arc discharge is made. However, in the case of an unequal electric field, only a local part where the electric field is strong is broken down, and corona discharge occurs. When the electric field is further increased, the entire road is destroyed. Normally, in the atmospheric pressure air, when a transition to all-road breakdown occurs, the transition to an arc discharge is often made quickly without going through a glow discharge. In this state of arc discharge, the temperature of the target object is several thousand degrees, so that a low-temperature process is not performed.

【００３５】このため、大気圧下でグロー放電を安定に
形成させるためには、放電空間をＨｅで充満するこ
と、電極間（放電経路）に絶縁体を挿入すること、
少なくとも一方の電極はブラシ状とすること、印加電
界の周波数を３ｋＨｚ以上とすることが必要条件として
知られている。これらの理由は、は放電がアーク放電
に移行しないようにするため、は電界を不均一にし放
電しやすいようにするため、は絶縁体を通して電流を
流すためである。Therefore, in order to stably form a glow discharge under atmospheric pressure, the discharge space must be filled with He, and an insulator must be inserted between the electrodes (discharge path).
It is known that at least one electrode has a brush shape and the frequency of the applied electric field is 3 kHz or more. These reasons are to prevent the discharge from shifting to arc discharge, to make the electric field nonuniform and to facilitate the discharge, and to flow the current through the insulator.

【００３６】次に、本発明のワイヤボンディング装置１
２による、電極の清浄工程におけるプラズマエッチング
及びワイヤボンディング工程におけるワイヤボンディン
グに関して説明する。Next, the wire bonding apparatus 1 of the present invention
No. 2, plasma etching in the electrode cleaning step and wire bonding in the wire bonding step will be described.

【００３７】まず、清浄工程に関して説明する。First, the cleaning step will be described.

【００３８】半導体チップ６を搭載した第１段階のＢＧ
Ａパッケージ１１ａが、プラズマジェット部５０のガス
噴出口２５の下方にセットされる。First-stage BG mounting semiconductor chip 6
The A package 11a is set below the gas ejection port 25 of the plasma jet unit 50.

【００３９】次に、ガス導入路２８から環状空室２４
に、例えば不活性ガスとしてＡｒガスを、また反応ガス
としてＯ2を不活性ガスの流量比（不活性ガスの流量／
（不活性ガスの流量＋反応ガスの流量））で０．７以上
になる条件で導入し、高周波電極２６に３［ｋＨｚ］以
上の高周波電圧を印加すると、環状空室２４内の高周波
電極２６と接地された円錐状電極２７との間でグロー放
電が発生し、Ａｒプラズマが形成される。このとき高周
波電極２６の位置を上下に移動させることにより、プラ
ズマの放電領域を調整することができる。このようにし
て発生したプラズマをガス噴出口２５から噴出させて、
第１段階のＢＧＡパッケージ１１ａの信号用電極２、パ
ワー用電極４及びグランド用電極５のうちのワイヤボン
ディングすべき電極の１つを曝露する。これにより、曝
露された、ワイヤボンディングすべき１つの電極の表面
に存在するコンタミネーションが除去されることとな
る。Next, the annular space 24
In addition, for example, Ar gas as an inert gas and O 2 as a reactant gas are mixed at a flow rate ratio of the inert gas (flow rate of the inert gas / flow rate of the inert gas).
(The flow rate of the inert gas + the flow rate of the reaction gas)) and 0.7 or more, and when a high-frequency voltage of 3 kHz or more is applied to the high-frequency electrode 26, the high-frequency electrode 26 A glow discharge is generated between the electrode and the grounded conical electrode 27, and an Ar plasma is formed. At this time, by moving the position of the high-frequency electrode 26 up and down, the discharge region of the plasma can be adjusted. The plasma generated in this way is ejected from the gas ejection port 25,
One of the electrodes to be wire-bonded among the signal electrode 2, the power electrode 4, and the ground electrode 5 of the first stage BGA package 11a is exposed. As a result, the contamination present on the exposed surface of one electrode to be wire-bonded is removed.

【００４０】次にワイヤボンディング工程に関して説明
する。Next, the wire bonding step will be described.

【００４１】上述のようにして、ワイヤボンディングす
べき１つの電極の表面に存在するコンタミネーションが
除去された第１段階のＢＧＡパッケージ１１ａは、次
に、ワイヤボンディング部５１により半導体チップ６の
被接続面と清浄された電極との電気的接続を行うための
ボンディング線７のワイヤボンディングが行われる。As described above, the first stage BGA package 11a from which the contamination present on the surface of one electrode to be wire-bonded has been removed is then connected to the semiconductor chip 6 by the wire bonding unit 51. Wire bonding of the bonding wire 7 for making electrical connection between the surface and the cleaned electrode is performed.

【００４２】まず、キャピラリ３１より導出されたＡｕ
ワイヤ３２の先端にトーチ電極３４を近付け、Ａｕワイ
ヤ３２とトーチ電極３４との間で発生した放電スパーク
でＡｕワイヤ３２の先端に溶融塊であるＡｕボール３３
を形成する。これは、接地されたＡｕワイヤ３２に、高
電圧の印加されたトーチ電極３４を所望の距離まで近付
けると、Ａｕワイヤ３２とトーチ電極３４との間で放電
スパークが発生してＡｕワイヤ３２の先端部が溶けてＡ
ｕボール３３が形成されるものである。なお、このＡｕ
ボール３３を形成する工程は、上述のプラズマジェット
部５０によるプラズマエッチングが行われている際にな
されているものであってもよい。First, Au derived from the capillary 31
The torch electrode 34 is brought close to the tip of the wire 32, and the discharge ball generated between the Au wire 32 and the torch electrode 34 causes the Au ball 33, which is a molten mass, to be attached to the tip of the Au wire 32.
To form This is because, when the torch electrode 34 to which a high voltage is applied is brought close to a desired distance to the grounded Au wire 32, a discharge spark occurs between the Au wire 32 and the torch electrode 34, and the tip of the Au wire 32 A melts
The u-ball 33 is formed. In addition, this Au
The step of forming the ball 33 may be performed during the plasma etching by the plasma jet unit 50 described above.

【００４３】次に、キャピラリ３１はＡｕワイヤ３２の
先端のＡｕボール３３を半導体チップ６の被接続面に一
次ボンディングする。次に、キャピラリ３１は、Ａｕワ
イヤ３２を繰り出しながら、駆動制御部３６からの制御
信号を基に駆動するステージ４０により移動させられ、
清浄された電極にＡｕワイヤ３２の一部を二次ボンディ
ングする。次に、キャピラリ３２から導出されたＡｕワ
イヤ３２の一部が切断される。切断されたキャピラリ３
１側のＡｕワイヤ３２の先端は、再びトーチ電極３４が
近付けられ、放電スパークによりＡｕボール３３が形成
されて、次のワイヤボンディングにむけて待機する。Next, the capillary 31 performs primary bonding of the Au ball 33 at the tip of the Au wire 32 to the connection surface of the semiconductor chip 6. Next, the capillary 31 is moved by the stage 40 driven based on a control signal from the drive control unit 36 while feeding out the Au wire 32,
A part of the Au wire 32 is secondarily bonded to the cleaned electrode. Next, a part of the Au wire 32 led out from the capillary 32 is cut. Cut Capillary 3
The torch electrode 34 is again approached to the tip of the Au wire 32 on one side, and the Au ball 33 is formed by the discharge spark, and waits for the next wire bonding.

【００４４】１組の半導体チップ６の被接続面と清浄さ
れた電極とのワイヤボンディングが終了後、再び、プラ
ズマジェット部５０により、次にワイヤボンディングが
なされる各電極のうちの１つの電極を清浄した後、次の
ワイヤボンディングが行われる。After the wire bonding between the connected surfaces of the set of semiconductor chips 6 and the cleaned electrodes is completed, one of the electrodes to be wire-bonded next by the plasma jet unit 50 again. After cleaning, the next wire bonding is performed.

【００４５】以上の清浄工程とワイヤボンディング工程
とが交互に行われることで、ワイヤボンディングの直前
にワイヤボンディングがなされる電極の表面が清浄され
ることとなる。By performing the above-described cleaning step and wire bonding step alternately, the surface of the electrode on which wire bonding is performed immediately before wire bonding is cleaned.

【００４６】以上の各工程が順次繰り返されて行われ、
ワイヤボンディングすべき全ての、半導体チップの被接
合面と回路パターン２ａの信号用電極２、パワー用電極
４及びグランド用電極５とがワイヤボンディングされる
ことで、図２（ｂ）に示す第２段階のＢＧＡパッケージ
１１ｂが作製される。The above steps are sequentially repeated and performed.
All the surfaces to be bonded of the semiconductor chip to be wire-bonded to the signal electrode 2, the power electrode 4, and the ground electrode 5 of the circuit pattern 2a are wire-bonded, thereby forming the second electrode shown in FIG. The stage BGA package 11b is manufactured.

【００４７】図２（ｃ）は、本発明のワイヤボンディン
グ装置１２によりワイヤボンディングがなされた後、封
止樹脂層９により樹脂封止がなされたＢＧＡパッケージ
１１の模式的断面図である。FIG. 2C is a schematic cross-sectional view of the BGA package 11 in which the wire bonding is performed by the wire bonding apparatus 12 of the present invention and then the resin is sealed by the sealing resin layer 9.

【００４８】第２段階のＢＧＡパッケージ１１ｂは、不
図示の樹脂封止金型にセットされた後、樹脂封止金型の
ゲート部から封止用樹脂を流入させ封止樹脂層９を形成
して封止を行う。一般的な封止材料の組成は、エポキシ
樹脂と、例えば、フェノールノボラック樹脂などの硬化
剤と、無機充填剤（シリカ）と、各種添加剤とによって
構成されている。ＢＧＡパッケージ１１は、基板１の表
面１ａ側のみの片面封止になるため、反りの小さい材料
が求められる。反りを小さくするためには、低膨張係数
化と、成形後の冷却収縮をガラス領域で行うための高Ｔ
ｇ化とに対応できるエポキシ材料が必要である。After the BGA package 11b in the second stage is set in a resin sealing mold (not shown), a sealing resin flows from a gate portion of the resin sealing mold to form a sealing resin layer 9. Sealing. A general composition of a sealing material is composed of an epoxy resin, a curing agent such as a phenol novolak resin, an inorganic filler (silica), and various additives. Since the BGA package 11 is sealed on one side only on the surface 1a side of the substrate 1, a material having a small warpage is required. In order to reduce the warpage, a low expansion coefficient and a high T for performing cooling and shrinkage after molding in the glass region are used.
An epoxy material that can cope with g-gating is required.

【００４９】この封止工程において、封止樹脂が流入さ
れるゲート部分となる不図示の電極以外の部分は、ソル
ダーレジスト３上に封止樹脂９が形成される。In this sealing step, the sealing resin 9 is formed on the solder resist 3 in portions other than the electrodes (not shown) which are gate portions into which the sealing resin flows.

【００５０】樹脂封止がなされた後、裏面１ｂ側にボー
ル状のバンプ１０が形成される。After resin sealing, a ball-shaped bump 10 is formed on the back surface 1b side.

【００５１】なお、本発明のワイヤボンディング装置１
２はＢＧＡパッケージ１１の製造を例に説明してきた
が、これに限定されるものではなく、半導体チップを搭
載する基板と半導体チップとの電気的接続をワイヤボン
ディングにより行う、ＢＧＡパッケージ以外の半導体パ
ッケージの製造に適用するものであってもよい。The wire bonding apparatus 1 of the present invention
2 has been described by taking the manufacture of the BGA package 11 as an example, but the present invention is not limited to this, and a semiconductor package other than the BGA package, in which an electrical connection between the substrate on which the semiconductor chip is mounted and the semiconductor chip is made by wire bonding. May be applied to the production of

【００５２】また、本発明のワイヤボンディング装置１
２は、半導体チップ６周辺の各電極のうち、ワイヤボン
ディングすべき１つの電極のみをプラズマエッチングに
より清浄しながらワイヤボンディングを行う例を挙げて
説明したが、これに限定されるものでなく、プラズマエ
ッチングとワイヤボンディングとの時間間隔が十分短け
れば、例えば矩形形状の半導体チップの４辺周りに配置
されている各電極を１辺ずつ清浄した後に、ワイヤボン
ディングが行われるものであってもよいし、あるいは、
４辺同時に清浄した後に、ワイヤボンディングが行われ
るものであってもよい。The wire bonding apparatus 1 of the present invention
2 describes an example of performing wire bonding while cleaning only one electrode to be wire-bonded among the electrodes around the semiconductor chip 6 by plasma etching, but is not limited thereto. If the time interval between the etching and the wire bonding is sufficiently short, for example, the wire bonding may be performed after each electrode disposed around the four sides of the rectangular semiconductor chip is cleaned one by one. Or
After the four sides are simultaneously cleaned, wire bonding may be performed.

【００５３】以上説明したように、本発明のワイヤボン
ディング装置１２は、プラズマジェット部５０とワイヤ
ボンディング部５１とが一体的に構成されているため、
Ａｕワイヤ３２をボンディングする直前毎にワイヤボン
ディングすべき電極のプラズマエッチングを行うことが
できるので、清浄された直後の電極にワイヤボンディン
グがなされることとなり、高い接続信頼性のあるワイヤ
ボンディングが可能となる。これにより、ワイヤボンデ
ィング不良が抑制されるため、ＢＧＡパッケージ１１の
生産における歩留りが高まる。また、本発明のワイヤボ
ンディング装置１２は、減圧装置等が不要な大気圧下で
プラズマエッチングを行うタイプのワイヤボンディング
装置１２であるため、ワイヤボンディング装置１２の構
成が簡単となり、ＢＧＡパッケージ１１の製造コストを
下げることができる。As described above, in the wire bonding apparatus 12 of the present invention, since the plasma jet unit 50 and the wire bonding unit 51 are integrally formed,
Since the electrode to be wire-bonded can be plasma-etched immediately before bonding the Au wire 32, wire bonding is performed on the electrode immediately after cleaning, and wire bonding with high connection reliability can be performed. Become. As a result, wire bonding defects are suppressed, and the yield in the production of the BGA package 11 is increased. Further, since the wire bonding apparatus 12 of the present invention is of a type that performs plasma etching under atmospheric pressure, which does not require a decompression device or the like, the configuration of the wire bonding apparatus 12 is simplified, and the production of the BGA package 11 is simplified. Costs can be reduced.

【００５４】[0054]

【実施例】以下に、上述した本発明の実施の形態の実施
例に関して説明する。[Embodiment] An embodiment of the above-described embodiment of the present invention will be described below.

【００５５】（第１の実施例）本実施例ではワイヤボン
ディングを行う装置として図１に示したワイヤボンディ
ング装置１２を用いた。このワイヤボンディング装置１
２によりワイヤボンディングがなされた、完成状態のＢ
ＧＡパッケージ２１１の模式的断面図を図３に示す。(First Embodiment) In this embodiment, the wire bonding apparatus 12 shown in FIG. 1 was used as an apparatus for performing wire bonding. This wire bonding apparatus 1
2 after completion of wire bonding by B
FIG. 3 shows a schematic cross-sectional view of the GA package 211.

【００５６】基板２０１としては表面２０１ａ及び裏面
２０１ｂに厚さ１８［μｍ］のＣｕ箔が形成された両面
銅張りガラスエポキシ板を用いた。ドリルもしくはＣＯ
2レーザを用いて所望の位置にφ０．３［ｍｍ］のスル
ーホール８を形成し、アルカリ金属化合物水溶液または
酸溶液で表面処理した後、無電解Ｃｕメッキで１５［μ
ｍ］厚のＣｕ膜２１２を形成した。これにより、表面２
０１ａ及び裏面２０１ｂには厚さ３３［μｍ］のＣｕ膜
が形成されたこととなる。このＣｕ膜２１２上にネガ型
感光性樹脂性のレジストフィルムをラミネートし熱圧着
した。所望の導体パターンを開口したマスクパターンに
よりレジストフィルムを光硬化した後、塩化第２銅溶液
などにより未露光部分を溶解除去し、銅のエッチャント
である塩化第二鉄により、Ｃｕ膜２１２をエッチング
し、所望の導体パターンを得た。As the substrate 201, a double-sided copper-clad glass epoxy plate having a 18 μm thick Cu foil formed on the front surface 201a and the back surface 201b was used. Drill or CO
(2 ) A through hole 8 having a diameter of 0.3 [mm] is formed at a desired position using a laser, and the surface is treated with an aqueous solution of an alkali metal compound or an acid solution.
m] thick Cu film 212 was formed. Thereby, the surface 2
This means that a Cu film having a thickness of 33 [μm] is formed on the back surface 201a and the back surface 201b. A negative photosensitive resin resist film was laminated on the Cu film 212 and thermocompression-bonded. After the resist film is photo-cured with a mask pattern having an opening of a desired conductor pattern, the unexposed portion is dissolved and removed with a cupric chloride solution or the like, and the Cu film 212 is etched with ferric chloride which is a copper etchant. Thus, a desired conductor pattern was obtained.

【００５７】次に、カルボン酸を分子中に有する不飽和
樹脂とポリエポキシ化合物を主成分とする二液型の光硬
化型の材料からなる厚さ６０［μｍ］（但し、Ｃｕ膜２
１２の導体パターン上は２７［μｍ］）のソルダーレジ
スト２０３をスクリーン印刷により一様に形成し、８０
［℃］程度でプレベイクした。Next, a thickness of 60 [μm] made of a two-part type photocurable material mainly composed of an unsaturated resin having a carboxylic acid in the molecule and a polyepoxy compound (however, the Cu film 2
A solder resist 203 of 27 [μm] is uniformly formed on the 12 conductor patterns by screen printing.
Prebaked at about [° C].

【００５８】次に、ボールグリッドに対応した部分のソ
ルダーレジスト２０３に対し、不図示のパルス幅２０
［μｓ］、繰り返し周波数３００［Ｈｚ］のＣＯ2レー
ザ装置を用い、エネルギ密度３５［Ｊ／ｃｍ2］、ビー
ム形状が３０×３０［ｍｍ］となるように光学系を調整
した後、２ショット照射し、φ２００［μｍ］のオープ
ニングを行った。この状態で、ソルダーレジスト２０３
が除去された信号用電極２０２、パワー用電極２０４及
びグランド用電極２０５にＮｉ／Ａｕメッキを施した。Next, the pulse width 20 (not shown) is applied to the solder resist 203 corresponding to the ball grid.
After adjusting the optical system using a CO 2 laser device having a repetition frequency of 300 [Hz] and an energy density of 35 [J / cm 2 ] and a beam shape of 30 × 30 [mm], two shots were taken. Irradiation was performed to open φ200 [μm]. In this state, the solder resist 203
The Ni / Au plating was applied to the signal electrode 202, the power electrode 204, and the ground electrode 205 from which was removed.

【００５９】このような状態の基板２０１上に半導体チ
ップ２０６をマウント接着した後、図１に示したワイヤ
ボンディング装置１２を用い、ワイヤボンディングがな
される各電極のうちの１つの電極をプラズマジェット部
５０により清浄した後、ワイヤボンディング部５１によ
りＡｕ線からなるボンディング線２０７のワイヤボンデ
ィングを行った。After the semiconductor chip 206 is mounted and bonded on the substrate 201 in such a state, one of the electrodes to be wire-bonded is connected to the plasma jet unit using the wire bonding apparatus 12 shown in FIG. After cleaning by 50, wire bonding of the bonding wire 207 made of Au wire was performed by the wire bonding part 51.

【００６０】以下に本実施例のワイヤボンディングの前
処理である各電極表面のプラズマエッチングに関して説
明する。Hereinafter, plasma etching of each electrode surface which is a pretreatment for wire bonding of the present embodiment will be described.

【００６１】プラズマジェット部５０の内側誘電体管２
２は、絶縁体であるガラス、石英、アルミナ、テフロ
ン、ポリイミド、ポリエチレン、ポリエチレンテレフタ
レート等を使用した。励起ガスとしてＡｒ：２０［ｓｃ
ｃｍ］、反応ガスとしてＯ2：５［ｓｃｃｍ］をガス導
入路２８から環状空室２４へと導入し、周波数が１３．
５６［ＭＨｚ］で、出力が１００［Ｗ］の高周波電力を
高周波電極２６に投入して安定なグロー放電を形成し、
プラズマを発生させた。このプラズマが十分に各電極に
到達するように高周波電極２６の上下方向の位置を設定
した。The inner dielectric tube 2 of the plasma jet unit 50
For 2, glass, quartz, alumina, Teflon, polyimide, polyethylene, polyethylene terephthalate, etc., which are insulators, were used. Ar: 20 [sc] as the excitation gas
cm], and O 2 : 5 [sccm] as a reaction gas is introduced from the gas introduction passage 28 into the annular vacant space 24, and the frequency is 13.
High frequency power of 56 [MHz] and output of 100 [W] is applied to the high frequency electrode 26 to form a stable glow discharge,
A plasma was generated. The vertical position of the high-frequency electrode 26 was set so that this plasma could reach each electrode sufficiently.

【００６２】なお、ガス噴出口２５の開口径はφ０．２
［ｍｍ］であり、各電極とガス噴出口２５との間の距離
を１０［ｍｍ］である。このため、噴出されたプラズマ
は、ワイヤボンディングがなされる各電極のうちの１つ
の電極にのみ照射される。The opening diameter of the gas ejection port 25 is φ0.2.
[Mm], and the distance between each electrode and the gas outlet 25 is 10 [mm]. Therefore, the ejected plasma is applied to only one of the electrodes to be wire-bonded.

【００６３】このような条件で、大気圧下において、ガ
ス噴出口２５からプラズマを噴出させ、各電極の清浄を
行った。Under these conditions, plasma was ejected from the gas ejection port 25 under atmospheric pressure to clean each electrode.

【００６４】ここで、プラズマを照射する前後での各電
極の表面をＸＭＡで表面分析を行ったところ、プラズマ
を照射する前ではレジストに起因する僅かな有機物とＣ
ｕが観測されたが、プラズマ照射後には各電極の表面の
Ａｕメッキ以外の信号は観測されず、大気圧下でのプラ
ズマ照射の効果を確認した。Here, the surface of each electrode before and after plasma irradiation was subjected to surface analysis by XMA. Before the plasma irradiation, slight organic matter and C
Although u was observed, no signal other than Au plating on the surface of each electrode was observed after plasma irradiation, confirming the effect of plasma irradiation under atmospheric pressure.

【００６５】次に、ワイヤボンディング部５１により、
上記のようにして清浄された電極へφ３０μｍのＡｕワ
イヤ３２をワイヤボンディングし、ボンディング線２０
７を形成した。Next, the wire bonding section 51
The Au wire 32 having a diameter of 30 μm is wire-bonded to the electrode cleaned as described above, and the bonding wire 20 is formed.
7 was formed.

【００６６】以上のプラズマエッチング及びワイヤボン
ディングを繰り返して行うことで、半導体チップ２０６
と基板２０１の回路パターン２０２ａとを電気的に接続
した。By repeatedly performing the above-described plasma etching and wire bonding, the semiconductor chip 206 is formed.
And the circuit pattern 202a of the substrate 201 were electrically connected.

【００６７】封止樹脂層２０９を形成する前に、ボンデ
ィング線２０７のボンディング強度の測定を行ったとこ
ろ、ワイヤボンディングされた全てのボンディング線２
０７がボンディング強度が５［ｇ］以上であった。Before the formation of the sealing resin layer 209, the bonding strength of the bonding wire 207 was measured.
07 had a bonding strength of 5 [g] or more.

【００６８】次に、半導体チップ２０６及びワイヤボン
ディングがなされた部分の樹脂封止を行う。Next, resin sealing is performed on the semiconductor chip 206 and the portion where the wire bonding has been performed.

【００６９】ＢＧＡパッケージ２１１の封止樹脂層２０
９の形成は、不図示の樹脂封止金型にセットされた後、
樹脂封止金型のゲート部から封止用樹脂を流入させて樹
脂封止が行われた。The sealing resin layer 20 of the BGA package 211
9 is set in a resin sealing mold (not shown),
Resin sealing was performed by flowing sealing resin from the gate of the resin sealing mold.

【００７０】封止樹脂にはシリカ粉末を充填剤、フェノ
ールノボラック樹脂を硬化剤として含有する熱硬化性エ
ポキシ樹脂を用い、脂封止金型のゲート部の毛細管現象
を利用して流入、充填した。このとき、基板２０１を６
０〜８０［℃］程度に加熱し封止樹脂の粘度を低減する
ことにより樹脂の充填性を改善した。充填した樹脂を１
００［℃］／４［ｈｒ］、１５０［℃］／２［ｈｒ］の
ステップキュアにより硬化させた。A thermosetting epoxy resin containing a silica powder as a filler and a phenol novolak resin as a curing agent was used as the sealing resin, and the resin was flowed in and filled by utilizing the capillary phenomenon at the gate of the oil sealing mold. . At this time, the substrate 201 is
The resin filling property was improved by heating to about 0 to 80 ° C. to reduce the viscosity of the sealing resin. 1 filled resin
It was cured by a step cure of 00 [° C.] / 4 [hr] and 150 [° C.] / 2 [hr].

【００７１】次に、ボールグリッドの所定位置の既存の
方法によりはんだバンプ２１０を形成し、ＢＧＡパッケ
ージ２１１を完成させた。Next, a solder bump 210 was formed at a predetermined position of the ball grid by an existing method, and a BGA package 211 was completed.

【００７２】以上のようにして３０個のＢＧＡパッケー
ジ２１１を作製し、その品質評価を以下の方法で行っ
た。As described above, 30 BGA packages 211 were manufactured, and their quality was evaluated by the following method.

【００７３】ＢＧＡパッケージ２１１の反りをＢＧＡパ
ッケージ２１１の表面の平坦な部分から最大変位してい
る部分のズレ量として測定した。その結果、変位量は４
０［μｍ］で問題となるレベルではなかった。The warpage of the BGA package 211 was measured as the amount of displacement of the portion of the BGA package 211 that was maximally displaced from a flat surface. As a result, the displacement amount is 4
0 [μm] was not a problematic level.

【００７４】温度８５［℃］、湿度８５［％］の雰囲気
中に１５０時間放置して吸湿処理を行った後、２４０
［℃］のはんだ浴に３０秒間浸漬し、クラック発生率と
耐はんだ性とを調べた。その結果、クラック発生率はゼ
ロであったとともに、十分な耐はんだ性とを確認した。After being left in an atmosphere of a temperature of 85 ° C. and a humidity of 85% for 150 hours to perform a moisture absorption process,
It was immersed in a solder bath of [° C.] for 30 seconds, and the crack generation rate and the solder resistance were examined. As a result, the crack occurrence rate was zero, and sufficient solder resistance was confirmed.

【００７５】耐熱衝撃性試験として、−６５［℃］〜室
温〜１５０［℃］を１サイクルとする冷熱サイクル試験
（ＴＣＴ試験）を５００サイクル繰り返した後、動作特
性をチェックした。その結果、不良発生率はゼロであっ
た。As a thermal shock resistance test, after 500 cycles of a thermal cycle test (TCT test) in which one cycle was from -65 [° C.] to room temperature to 150 [° C.], the operating characteristics were checked. As a result, the failure rate was zero.

【００７６】耐湿信頼性を評価するために、１２７
［℃］、２．５気圧の飽和水蒸気圧雰囲気中に５００時
間放置するプレッシャクッカ試験（ＰＣＴ）を行った。
その結果、リーク及びオープン不良率はゼロであった。In order to evaluate the humidity resistance reliability, 127
[° C.], a pressure cooker test (PCT) in which the sample was left for 500 hours in a saturated steam pressure atmosphere of 2.5 atm.
As a result, the leak and open defect rates were zero.

【００７７】（第２の実施例）本実施例でも第1の実施
例と同様に、ワイヤボンディングを行う装置として第１
の実施形態のワイヤボンディング装置１２を用いた。(Second Embodiment) In this embodiment, as in the first embodiment, the first device is used as an apparatus for performing wire bonding.
The wire bonding apparatus 12 of the embodiment was used.

【００７８】励起ガスとしてＡｒ：３０［ｓｃｃｍ］、
反応ガスとしてＨ2：２０［ｓｃｃｍ］をガス導入路２
８から環状空室２４へと導入し、周波数が１３．５６
［ＭＨｚ］で出力が１５０［Ｗ］の高周波電力を高周波
電極２６にを投入した以外は、全て上述の第1の実施例
と同様であるため、詳細の説明は省略する。Ar: 30 [sccm] as the excitation gas,
H 2 : 20 [sccm] as a reaction gas is introduced into the gas introduction path 2.
8 into the annular vacancy 24, and the frequency is 13.56.
Except that high-frequency power with an output of 150 [W] at [MHz] is applied to the high-frequency electrode 26, all are the same as the above-described first embodiment, and thus detailed description is omitted.

【００７９】本実施例において作製されたＢＧＡパッケ
ージを第1の実施例と同様の方法で信頼性試験をした結
果、第1の実施例と同様の良好な結果が得られた。As a result of performing a reliability test on the BGA package manufactured in this embodiment in the same manner as in the first embodiment, good results similar to those in the first embodiment were obtained.

【００８０】（第３の実施例）本実施例ではガス噴出口
２５の開口形状が幅０．１［ｍｍ］、長さ２５［ｍｍ］
の矩形である以外は第1の実施例と同様の、第１の実施
形態のワイヤボンディング装置１２を用いた。(Third Embodiment) In this embodiment, the opening shape of the gas ejection port 25 is 0.1 [mm] in width and 25 [mm] in length.
A wire bonding apparatus 12 according to the first embodiment was used, which was the same as the first example except that it was rectangular.

【００８１】本実施例は、半導体チップ２０６の４辺周
りに配置されている各電極を１個ずつ清浄するのではな
く、１辺ずつ清浄するために開口形状を矩形としたもの
である。In the present embodiment, the electrodes arranged around the four sides of the semiconductor chip 206 are not cleaned one by one, but the opening shape is made rectangular to clean one side at a time.

【００８２】なお、それ以外は全て第1の実施例と同様
であるため、詳細の説明は省略する。The rest of the configuration is the same as that of the first embodiment, and a detailed description thereof will be omitted.

【００８３】本実施例において作製されたＢＧＡパッケ
ージを第1の実施例と同様の方法で信頼性試験をした結
果、第1の実施例と同様の良好な結果が得られた。As a result of performing a reliability test on the BGA package manufactured in this embodiment in the same manner as in the first embodiment, the same good results as in the first embodiment were obtained.

【００８４】（第４の実施例）本実施例では第１の実施
形態のワイヤボンディング装置１２のプラズマジェット
部５０が、図４（ａ）及び図４（ｂ）に示すプラズマジ
ェット部７０となった以外は第1の実施例と同様の、第
１の実施形態のワイヤボンディング装置１２を用いた。(Fourth Embodiment) In this embodiment, the plasma jet unit 50 of the wire bonding apparatus 12 of the first embodiment is replaced with a plasma jet unit 70 shown in FIGS. 4A and 4B. Except for this, the same wire bonding apparatus 12 of the first embodiment as in the first embodiment was used.

【００８５】図４（ａ）は、プラズマジェット部７０の
側断面図であり、図４（ｂ）は、図４（ａ）のプラズマ
ジェット部７０を図４（ａ）中に示す矢印Ａの方向から
みた平面図である。FIG. 4A is a side sectional view of the plasma jet unit 70, and FIG. 4B is a sectional view of the plasma jet unit 70 shown in FIG. It is the top view seen from the direction.

【００８６】誘電体材料の放電管６３の外周にはコイル
電極６１が巻かれている。放電管６３の上端は不図示の
ガス導入口が設けられ、かつ、下端は開口面積が拡大さ
れた形状であるとともに放電領域６２の直下に遮蔽部材
６４が設けられている。この構成は、半導体チップ２０
６の４辺周りに配置されている各電極を１個ずつ、ある
いは１辺ずつ清浄するのではなく、４辺同時に清浄する
ための開口形状となっている。A coil electrode 61 is wound around the outer circumference of a discharge tube 63 made of a dielectric material. A gas inlet (not shown) is provided at the upper end of the discharge tube 63, and the lower end has an enlarged opening area and a shielding member 64 is provided immediately below the discharge region 62. This configuration corresponds to the semiconductor chip 20
The opening shape is for cleaning the four sides at the same time, instead of cleaning each of the electrodes arranged around the four sides of each one or one by one.

【００８７】また、放電領域６２がガス噴出口６４から
離れた位置に形成されるので、放電がガス噴出口６４か
ら外に飛び出すことによって被処理材に電気的ダメージ
を与えたり、人体に危険を及ぼす恐れを低減させたもの
である。Further, since the discharge region 62 is formed at a position distant from the gas ejection port 64, the discharge jumps out of the gas ejection port 64 to cause electrical damage to the material to be processed and to cause danger to the human body. This is a reduction in the effect.

【００８８】なお、それ以外は全て第1の実施例と同様
であるため、詳細の説明は省略する。Note that the rest of the configuration is the same as that of the first embodiment, and a detailed description thereof will be omitted.

【００８９】本実施例において作製されたＢＧＡパッケ
ージを第1の実施例と同様の方法で信頼性試験をした結
果、第1の実施例と同様の良好な結果が得られた。As a result of performing a reliability test on the BGA package manufactured in this embodiment in the same manner as in the first embodiment, good results similar to those in the first embodiment were obtained.

【００９０】なお、第1ないし第４の実施例ではＢＧＡ
パッケージとしたが、同様の基板構造、製造プロセスを
必要とする半導体パッケージにも同様の効果が得られる
ことを確認した。 （比較例）ワイヤボンディングの直前にプラズマ照射を
行わずにワイヤボンディングを行った、本実施例のＢＧ
Ａパッケージ２１１との比較のためのＢＧＡパッケージ
では、ピン数の１０［％］にボンディング強度が５
［ｇ］よりも低く、十分なボンディング強度が得られな
かったことが確認された。In the first to fourth embodiments, the BGA
Although a package was used, it was confirmed that a similar effect could be obtained for a semiconductor package requiring the same substrate structure and manufacturing process. (Comparative Example) BG of the present example in which wire bonding was performed without performing plasma irradiation immediately before wire bonding
In the BGA package for comparison with the A package 211, the bonding strength is 5% for 10% of the number of pins.
[G], and it was confirmed that sufficient bonding strength could not be obtained.

【００９１】[0091]

【発明の効果】以上説明したように本発明によれば、ワ
イヤボンディング装置自身が、半導体チップ及び基板の
電極の表面を清浄するための、プラズマを電極の表面に
照射するプラズマ発生手段を有しているため、プラズマ
発生手段で電極の表面を清浄してからワイヤボンディン
グ手段でワイヤボンディングを行うまでの時間を短縮す
ることができる。このため、電極の表面に不純物の再付
着や酸化膜が形成されるのを抑制することができるので
ワイヤボンディング強度を高めることとなり、よって、
半導体パッケージの製造の歩留りを高めることができ
る。As described above, according to the present invention, the wire bonding apparatus itself has plasma generating means for irradiating plasma to the surface of the electrode for cleaning the surface of the electrode of the semiconductor chip and the substrate. Therefore, the time from cleaning the surface of the electrode by the plasma generation means to performing wire bonding by the wire bonding means can be reduced. For this reason, it is possible to suppress the redeposition of impurities and the formation of an oxide film on the surface of the electrode, thereby increasing the wire bonding strength.
The yield of semiconductor package manufacturing can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】ワイヤボンディング装置の概略構成図である。FIG. 1 is a schematic configuration diagram of a wire bonding apparatus.

【図２】本発明のワイヤボンディング装置によるワイヤ
ボンディング工程を含む、各製造段階におけるＢＧＡパ
ッケージの模式的断面図である。FIG. 2 is a schematic cross-sectional view of a BGA package at each manufacturing stage including a wire bonding step by a wire bonding apparatus of the present invention.

【図３】本発明の第1の実施例により作製されたＢＧＡ
パッケージの模式的断面図である。FIG. 3 shows a BGA manufactured according to the first embodiment of the present invention.
FIG. 3 is a schematic sectional view of a package.

【図４】本発明の第４の実施例で用いられたプラズマジ
ェット部の側断面図及び平面図である。FIG. 4 is a side sectional view and a plan view of a plasma jet unit used in a fourth embodiment of the present invention.

【図５】ＢＧＡパッケージの一例の模式的断面図であ
る。FIG. 5 is a schematic cross-sectional view of an example of a BGA package.

【図６】従来のワイヤボンディング装置の概略構成図で
ある。FIG. 6 is a schematic configuration diagram of a conventional wire bonding apparatus.

【符号の説明】[Explanation of symbols]

１、２０１ 基板 １ａ、２０１ａ 表面 １ｂ、２０１ｂ 裏面 ２、２０２ 信号用配線 ２ａ、２０２ａ 回路パターン ３、２０３ ソルダーレジスト ４、２０４ パワー用配線 ５、２０５ グランド用配線 ６、２０６ 半導体チップ ７、２０７ ボンディング線 ８、２０８ スルーホール配線 ９、２０９ 封止樹脂層 １０、２１０ バンプ １１、２１１ ＢＧＡパッケージ １１ａ 第１段階のＢＧＡパッケージ １１ｂ 第２段階のＢＧＡパッケージ １２ ワイヤボンディング装置 ２１ 蓋 ２２ 内側誘電体管 ２３ 外側誘電体管 ２３ａ 円錐部 ２４ 環状空室 ２５、６０ ガス噴出口 ２６ 高周波電極 ２７ 円錐状電極 ３１ キャピラリ ３２ Ａｕワイヤ ３３ Ａｕボール ３４ トーチ電極 ３５ ワイヤ供給部 ３６ 駆動制御部 ３７ キャピラリ駆動部 ３８ トーチ電極駆動部 ３９ アーム駆動機構 ４０ ステージ ４１ 直流電源 ５０ プラズマジェット部 ５１ ワイヤボンディング部 ６１ コイル電極 ６２ 放電領域 ６３ 放電管 ２１２ Ｃｕ膜 1, 201 Substrate 1a, 201a Front surface 1b, 201b Back surface 2, 202 Signal wiring 2a, 202a Circuit pattern 3, 203 Solder resist 4, 204 Power wiring 5, 205 Ground wiring 6, 206 Semiconductor chip 7, 207 Bonding line 8, 208 Through-hole wiring 9, 209 Sealing resin layer 10, 210 Bump 11, 211 BGA package 11a First-stage BGA package 11b Second-stage BGA package 12 Wire bonding device 21 Cover 22 Inner dielectric tube 23 Outer dielectric Body tube 23a Conical part 24 Annular chamber 25, 60 Gas outlet 26 High frequency electrode 27 Conical electrode 31 Capillary 32 Au wire 33 Au ball 34 Torch electrode 35 Wire supply unit 36 Drive control unit 37 Capillary drive unit 38 Torch Electrode driving portion 39 arm driving mechanism 40 stage 41 DC power supply 50 plasma jet 51 wire bonding portion 61 coil electrode 62 discharge region 63 discharge tube 212 Cu film

Claims (7)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップの電極と前記半導体チップ
を搭載した基板の電極とをボンディングワイヤにより電
気的に接続するワイヤボンディング手段と、 前記ワイヤボンディング手段による接続の前に前記各電
極の表面を清浄するための、外部より供給されたガスを
プラズマの状態に励起させるとともに、前記プラズマを
前記各電極に照射させるプラズマ発生手段とを有するこ
とを特徴とするワイヤボンディング装置。1. A wire bonding means for electrically connecting an electrode of a semiconductor chip and an electrode of a substrate on which the semiconductor chip is mounted by a bonding wire; and cleaning a surface of each electrode before the connection by the wire bonding means. And a plasma generating means for exciting the gas supplied from the outside into a plasma state and irradiating the plasma to each of the electrodes. 【請求項２】 前記プラズマ発生手段は、略大気圧下で
前記プラズマを励起させる請求項１に記載のワイヤボン
ディング装置。2. The wire bonding apparatus according to claim 1, wherein said plasma generating means excites said plasma under substantially atmospheric pressure. 【請求項３】 前記プラズマ発生手段は、前記各電極の
うちの１つのみに前記プラズマの照射を行う請求項１ま
たは２に記載のワイヤボンディング装置。3. The wire bonding apparatus according to claim 1, wherein the plasma generating means irradiates only one of the electrodes with the plasma. 【請求項４】 前記プラズマ発生手段は、複数の前記電
極に同時に前記プラズマの照射を行う請求項１または２
に記載のワイヤボンディング装置。4. The plasma generating means according to claim 1, wherein said plasma generating means simultaneously irradiates said plurality of electrodes with said plasma.
3. The wire bonding apparatus according to claim 1. 【請求項５】 請求項３に記載のワイヤボンディング装
置を用いたワイヤボンディング方法であって、 前記プラズマ発生手段により放射される前記プラズマに
より前記半導体チップの電極と前記基板の電極とのうち
の少なくとも前記基板の電極の１つのみの表面を清浄す
る清浄工程と、 前記清浄工程により清浄された前記各電極及び前記清浄
された電極と電気的に接続されるべき電極とにワイヤボ
ンディングを行うワイヤボンディング工程とを有し、 前記清浄工程と前記ワイヤボンディング工程とを交互に
繰り返して、全ての前記各電極のワイヤボンディングを
行うことを特徴とするワイヤボンディング方法。5. A wire bonding method using the wire bonding apparatus according to claim 3, wherein at least one of an electrode of the semiconductor chip and an electrode of the substrate by the plasma emitted by the plasma generating means. A cleaning step of cleaning only one surface of the electrode of the substrate; and wire bonding for performing wire bonding to each of the electrodes cleaned by the cleaning step and an electrode to be electrically connected to the cleaned electrode. And a wire bonding process for all the electrodes by alternately repeating the cleaning process and the wire bonding process. 【請求項６】 請求項４に記載のワイヤボンディング装
置を用いたワイヤボンディング方法であって、 前記プラズマ発生手段により放射される前記プラズマに
より複数の前記電極の表面を清浄する清浄工程と、 前記清浄工程により清浄された前記各電極及び前記清浄
された各電極と電気的に接続されるべき各電極とにワイ
ヤボンディングを行うワイヤボンディング工程とを有す
ることを特徴とするワイヤボンディング方法。6. A wire bonding method using the wire bonding apparatus according to claim 4, wherein: a cleaning step of cleaning surfaces of the plurality of electrodes by the plasma emitted by the plasma generating means; A wire bonding step of performing wire bonding to each of the electrodes cleaned by the process and each of the electrodes to be electrically connected to the cleaned electrodes. 【請求項７】 前記清浄工程と前記ワイヤボンディング
工程とを交互に繰り返して、全ての前記各電極のワイヤ
ボンディングを行う請求項６に記載のワイヤボンディン
グ方法。7. The wire bonding method according to claim 6, wherein the cleaning step and the wire bonding step are alternately repeated to perform wire bonding for all the electrodes.
JP11146859A 1999-05-26 1999-05-26 Wire-bonding device and wire-bonding method using the same Pending JP2000340599A (en)

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US20080023525A1 (en) * 2006-07-31 2008-01-31 Kabushiki Kaisha Shinkawa Bonding apparatus
US8283593B2 (en) 2007-02-15 2012-10-09 Kabushiki Kaisha Shinkawa Wire cleaning guide
EP2065115A1 (en) * 2007-11-29 2009-06-03 Linde Aktiengesellschaft Device and method for bonding a wire containing copper with the use of at least a plasma nozzle
CN102800602A (en) * 2011-05-24 2012-11-28 瑞萨电子株式会社 Method of manufacturing semiconductor device
KR20140104451A (en) * 2012-02-07 2014-08-28 가부시키가이샤 신가와 Wire bonding apparatus
KR101718340B1 (en) 2012-02-07 2017-04-04 가부시키가이샤 신가와 Wire bonding apparatus
JP2014170816A (en) * 2013-03-01 2014-09-18 Panasonic Corp Plasma cleaning method
CN105972016A (en) * 2015-03-11 2016-09-28 万润科技股份有限公司 Pressing method and device
CN106935521A (en) * 2015-12-31 2017-07-07 矽品精密工业股份有限公司 Wire bonding device and wire bonding method
US11031254B2 (en) 2018-11-07 2021-06-08 Renesas Electronics Corporation Method for manufacturing a semiconductor device

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