JP2000331805A - Laminated ceramic array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a laminated ceramic array which is made small and stable in electrostatic capacitance without enhancing a ceramic layer in thickness. SOLUTION: First inner electrode layers 3a and second inner electrode layers 3b are alternately laminated by interposing a ceramic layer 2 between them for the formation of a laminate 1, where first outer electrodes 4a and second electrode layers 4b are formed on each edge face of the laminate 1. The first inner electrode layers 3a and the second inner electrode layers 3b are exposed so as to be electrically connected to the first inner electrode layers 3a and the second inner electrode layers 3b, respectively. The first and second inner electrode layers 3a and 3b are each asymmetrical in shape, and the first inner electrode layers 3a and the second inner electrode layers 3b are disposed oppositely to each other at a point by interposing the ceramic layer 3 between them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic array such as a multilayer varistor for protecting an electric circuit from overvoltage.

[0002]

2. Description of the Related Art In a multi-layer varistor array, which is an example of a multi-layer ceramic array, in recent years, the miniaturization of electronic equipment and the promotion of power saving have led to a reduction in the voltage of the equipment. The threat of electric discharge has increased, and measures against static electricity in electronic devices have become an important issue. This is because, as the drive voltage of the circuit decreases, malfunction of the electronic device due to the abnormal voltage and, in the worst case, breakage of the circuit components are more likely to occur. Electronic devices such as mobile phones, notebook computers, and portable information terminal devices have various IO terminals for receiving signals from the outside, so that electrostatic discharge when an interface cable is connected directly damages internal signal circuits. There is a problem that the possibility is high. further,
In the case of a mobile phone, electrostatic discharge from an antenna portion as well as an IO terminal has become a problem.

[0003] Such components for countermeasures against electrostatic discharge, such as signal circuits or antenna circuits, have a capacitance of several pF in order to be able to cope with a low-voltage drive circuit and to minimize the influence on the signal lines. At most a dozen p
It is desirable that it is as small as F.

FIG. 10 is a perspective view of a general laminated varistor, FIG. 11 is a sectional view taken along a line AB in FIG. 10, FIG. 12 is a sectional view taken along a line CD in FIG. 10, and FIG. FIG. 14
FIG. 11 is a sectional view taken along line GH of FIG. 10.

As shown in FIGS. 11 to 14, a conventional laminated varistor array has a laminated body in which a plurality of internal electrode layers 101a and 101b are opposed to each other with a single ceramic layer 100 interposed therebetween. A plurality of external electrodes 102 were formed on both exposed end faces of 101a and 101b. The internal electrode layers 101a and 101b are
It was a rectangular symmetric type.

[0006]

In order to manufacture a stacked varistor array having a small capacitance in the above configuration, a method for reducing the number of the internal electrode layers 101a and 101b and a method for reducing the number of the internal electrode layers 101a and 101b are described. There is a method of increasing the thickness of the ceramic layer 100 (hereinafter, referred to as an effective layer). However, even if the number of the internal electrode layers 101a and 101b is reduced, it is difficult to reduce the capacitance to several pF because the area of the overlapping portion of the internal electrode layers 101a and 101b is large, and the thickness of the effective layer is increased. For example, since the voltage increases in proportion to the effective layer thickness, the varistor voltage increases at the same time, and there is a problem that it is difficult to cope with a low-voltage driving circuit.

Accordingly, an object of the present invention is to provide a multilayer ceramic array having a small capacitance and a stable capacitance without increasing the thickness of the ceramic layer.

[0008]

In order to achieve this object, a multilayer ceramic array according to the present invention comprises a ceramic body in which a plurality of ceramic layers and a plurality of internal electrodes are laminated, and a surface of the ceramic body. A plurality of external electrodes provided so as to face each other via the ceramic body and electrically connected to the internal electrodes, and the internal electrodes facing each other via the ceramic layer are asymmetric and different from each other. Since the electrodes are connected to the electrodes and the overlapping area of the internal electrodes can be reduced, the above object can be achieved.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the first aspect of the present invention, there is provided a ceramic body in which a plurality of ceramic layers and a plurality of internal electrodes are laminated, and the ceramic body is provided on the surface of the ceramic body. A plurality of external electrodes provided so as to face each other and electrically connected to the internal electrode, and the adjacent internal electrodes are connected to the different external electrodes and connected to the external electrodes facing each other. The internal electrodes face only one place via the ceramic layer,
In addition, the laminated ceramic arrays are asymmetrical to each other, and have low capacitance and small variation in capacitance.

According to a second aspect of the present invention, the width of the internal electrode is larger at the portion connected to the external electrode than the maximum width at the portion facing the external electrode via the ceramic layer. This is a type ceramic array, and electrical connection between an internal electrode layer and an external electrode can be ensured.

According to a third aspect of the present invention, there is provided the multilayer ceramic array according to the first or second aspect, wherein adjacent internal electrodes are non-similar types, wherein each terminal has a different capacitance. It is possible.

According to a fourth aspect of the present invention, there is provided the multilayer ceramic array according to any one of the first to third aspects, wherein the internal electrode has a curved corner portion, and prevents concentration of an electric field. Is what you can do.

According to a fifth aspect of the present invention, there is provided the multilayer ceramic array according to any one of the first to fourth aspects, wherein the ceramic layer is a semiconductor ceramic layer exhibiting a voltage non-linear resistance characteristic.

Hereinafter, embodiments of the present invention will be described with reference to the drawings, taking a stacked varistor array as an example. Since the external appearance has the shape shown in FIG.
This will be described with reference to FIG.

(Embodiment 1) FIG. 1 is a perspective view of a multilayer varistor array according to the present invention, FIG. 2 is a sectional view taken along a line AB in FIG. 1, FIG. 3 is a sectional view taken along a line CD, and FIG. FIG. 5 is a cross-sectional view taken along the line GH. FIG. 5 is a cross-sectional view taken along the line GH.
3a is a first internal electrode layer, 3b is a second internal electrode layer, 4
a is a first external electrode, and 4b is a second external electrode.

A method for manufacturing the laminated varistor array will be described below.

First, Bi as a sub-component is added to ZnO as a main component.
_To a raw material to which ₂ O ₃ , Co ₂ O ₃ , Sb ₂ O ₃ , Al ₂ O _3, etc. were added, butyl acetate, an organic binder, and a plasticizer were added and mixed to obtain a slurry. The slurry was formed into a sheet by a doctor blade method and cut into an appropriate size to obtain a ceramic green sheet to be a ceramic layer 2.

Next, as shown in FIGS. 2 and 3, the first and second internal electrode layers 3a and 3b were formed on the green sheets by using an Ag paste. Next, the first internal electrode layer 3a and the second internal electrode layer 3b were alternately laminated so as to face each other with the ceramic layer 2 interposed therebetween, thereby forming a laminate 1.

Next, the laminate 1 is fired at 900 to 950 ° C., and after barrel polishing, the first internal electrode layer 3 of the laminate 1 is formed.
a and the exposed both end surfaces of the second internal electrode layer 3b.
An Ag / Pd paste is applied so as to electrically connect the external electrode 4a of the first electrode layer 3a to the first internal electrode layer 3a and the second external electrode 4b to the second internal electrode layer 3b, and is baked at 700 to 900 ° C. Thus, the first and second external electrodes 4a and 4b were formed to obtain a multilayer varistor array as shown in FIG.

The laminated varistor array is shown in FIGS.
4 and 5, the first and second internal electrode layers 3a and 3b are asymmetric in shape, and a plurality of first internal electrode layers 3a with one ceramic layer 2 interposed therebetween as shown in FIGS. And a plurality of second internal electrode layers 3b each have a portion facing each other.

(Embodiment 2) FIG. 6 is a sectional view taken along a line AB in FIG. 1, and FIG. 7 is a sectional view taken along a line CD in FIG.

The difference from the first embodiment is that the first internal electrode layers 3a present on the same surface are formed so as to be alternately exposed to the opposite end surfaces of the laminate. The second internal electrode layer 3b was formed in the same manner. Therefore, on the same plane, the first and second internal electrode layers 3a and 3b
The end faces different from the adjacent first and second internal electrode layers 3a and 3b are connected to the first and second external electrodes 4a and 4b.

The first and second internal electrode layers 3a, 3b
Is also asymmetric, and has one portion where the first internal electrode layer 3a and the second internal electrode layer 3b face each other with the ceramic layer 2 interposed therebetween.

This stacked varistor array was also manufactured by the method described in the first embodiment except that the shapes of the first and second internal electrode layers 3a and 3b were different.

As described above, the first adjoining parts on the same plane
And the second internal electrode layers 3a, 3b
In addition, since it is connected to the second external electrodes 4a and 4b, the stray capacitance can be reduced.

(Embodiment 3) FIG. 8 is a sectional view taken along line AB of FIG. 1, and FIG. 9 is a sectional view taken along line CD of FIG.

The difference from the first embodiment is that the first and second internal electrode layers 3a and 3b existing on the same plane are all different in shape.

That is, the first internal electrode layer 3a and the second internal electrode layer 3b opposed to each other via the ceramic layer 2 are asymmetric, and the first internal electrode layer 3a and the second internal electrode layer 3b Those adjacent to each other on the same plane are asymmetric with each other, and have one portion where the first internal electrode layer 3a and the second internal electrode layer 3b face each other with the ceramic layer 2 interposed therebetween.

In this laminated varistor array, the first and second internal electrode layers 3a and 3b adjacent to each other on the same plane are made asymmetric, so that a pair of first and The second external electrodes 4a and 4b can have different capacitances.

This stacked varistor array was also manufactured by the method described in the first embodiment, except that the shapes of the first and second internal electrode layers 3a and 3b were different.

The stacked varistor arrays shown in the first to third embodiments have a small capacitance and a pair of external electrodes 4a, The variation in the capacitance between each 4b is small and the varistor voltage is low. In addition, these stacked varistor arrays have a surge withstand capability at 8 × 20 μs of 5 A or more, despite their small capacitance, and are required by the IEC, which is an electrostatic discharge immunity test requirement defined by the International Electrotechnical Commission (IEC). −
This is a practical stacked varistor array that clears all the level 4 ESD tolerance of 1000-4-2.

The point of the present invention will be described below.

(1) Each of the first internal electrode layer 3a and the second internal electrode layer 3b may be a single layer or a plurality of layers. Of course, the first internal electrode layer 3a and the second internal electrode layer 3b may be used. The number of layers may be the same or different. Also,
The number of the first and second internal electrode layers 3a and 3b may be changed for each layer. By changing the number, the capacitance between the first and second external electrodes 4a and 4b can be adjusted.

(2) First and second internal electrode layers 3a, 3
The shape of b is such that the first and second internal electrode layers 3a and 3b facing each other with the ceramic layer 2 interposed therebetween due to a lamination shift when forming the laminate 1 like the shape shown in the above embodiment. It is desirable that the shape be such that the area does not easily change. The portion where the first and second internal electrode layers 3a and 3b overlap with one ceramic layer 2 interposed therebetween may be one or more.

(3) By making the shape of the first internal electrode layer 3a and / or the second internal electrode layer 3b two or more, the capacitance of the multilayer ceramic array can be increased through the multilayer body 1. It can be changed for each pair of first and second external electrodes 4a and 4b opposed to each other.

(4) First internal electrode layer 3a or second internal electrode layer 3a
The electric field concentration can be prevented by making at least a part of the corner portion of the internal electrode layer 3b as curved as possible, and the stacked varistor array is excellent in surge withstand capability. .

(5) In the above embodiment, the first and second
The total number of external electrodes 4a and 4b is eight, and they are all for four circuits. However, if the first and second external electrodes 4a and 4b are four or more even numbers, the required number of circuits is possible. You can increase as much as you like.

(6) First and second external electrodes 4a, 4b
Is not particularly limited, and it is important that the adjacent external electrodes 4a and 4b are not electrically connected. Therefore, the first and second internal electrode layers 3
The electrodes may cover the entire exposed portions of the first and second internal electrode layers 3a and 3b, or may be formed on only a part of the exposed end surfaces of the first and second internal electrode layers 3a and 3b. In consideration of the reliability of the above, it is desirable that the shape be such that the exposed first and second internal electrode layers 3a and 3b are all covered.

(7) In order to enhance the solderability when mounting the multilayer varistor array on the substrate, plating such as nickel-tin plating or nickel-solder plating is applied to the first and second external electrodes 4a and 4b. May be applied.

(8) First and second internal electrode layers 3a, 3
b, the first and second external electrodes 4a and 4b are not particularly limited as long as they are conductive metals.
It is particularly preferable that the material such as gold, platinum, palladium, nickel or an alloy thereof can be co-fired with the ceramic layer 2. Further, the first and second internal electrode layers 3a, 3
b and the first and second external electrodes 4a and 4b may be the same metal or different metals, but the use of the same metal ensures more reliable electrical connection.

(9) The composition of the ceramic layer 2 is not limited, and examples thereof include semiconductor ceramics such as ZnO and SrTiO ₃ and dielectric ceramics such as BaTiO ₃ . The composition of the ceramic layer 2 is not limited to one type, and two or more different types of ceramic layers 2 having different electric characteristics such as a dielectric constant and a varistor voltage may be used. A composite ceramic layer made of a material having different characteristics such as a magnetic ceramic layer may be used.

(10) At least the first and second external electrode surfaces 4a, 4b on the surface of the multilayer ceramic array are formed with glass coating or the like on the non-formed parts.
Strength can be improved, and moisture resistance and plating resistance can be improved.

(11) As shown in the first to third embodiments, the first portion of the portion where the first internal electrode layer 3a and the second internal electrode layer 3b face each other with a single ceramic layer 2 interposed therebetween. When the width of the portion connected to the first external electrode 4a and the second external electrode 4b is larger than that of the first and second internal electrode layers 3a and 3b, the first and second internal electrode layers 3a and 3b are connected to the first and second external electrodes 4a and 4b. Electrical connection with the external electrodes 4a and 4b is ensured.

(12) The size of the multilayer ceramic array of the present invention is not particularly limited, and is generally on the order of several millimeters to several hundreds of microns. However, as far as the construction method allows, it can be smaller or larger. It does not matter. Also,
The external shape of the multilayer ceramic electronic component is usually prismatic,
There are many square pillars or their corners, but any other shape is acceptable as long as the construction method allows.

(13) The multilayer ceramic array of the present invention is suitable for a varistor, but is not particularly limited to a varistor, but may be various types such as a capacitor, a sensor, and a thermistor.

[0046]

As described above, according to the present invention, a multilayer ceramic array having a small capacitance and a stable capacitance can be provided.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a multilayer ceramic array of the present invention.

FIG. 2 is a sectional view of the multilayer varistor array according to the first embodiment of the present invention, taken along the line AB in FIG. 1;

FIG. 3 is a sectional view of the multilayer varistor array according to the first embodiment of the present invention, taken along line CD of FIG. 1;

FIG. 4 is a sectional view of the multilayer varistor array according to the first embodiment of the present invention, taken along the line EF in FIG. 1;

FIG. 5 is a sectional view taken along line GH of FIG. 1 of the multilayer varistor array according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view of the stacked varistor array according to the second embodiment of the present invention, taken along the line AB in FIG. 1;

FIG. 7 is a sectional view of the multilayer varistor array according to the second embodiment of the present invention, taken along line CD of FIG. 1;

FIG. 8 is a cross-sectional view taken along the line AB of FIG. 1 of the multilayer varistor array according to the third embodiment of the present invention.

FIG. 9 is a cross-sectional view of the multilayer varistor array according to the third embodiment of the present invention, taken along line CD of FIG. 1;

FIG. 10 is a perspective view of a general conventional stacked varistor array.

FIG. 11 shows a conventional laminated varistor array in FIG.
B sectional view

FIG. 12 is a cross-sectional view of a conventional laminated varistor array,
D section view

FIG. 13 is a cross-sectional view taken along line E- in FIG.
F sectional view

FIG. 14 is a cross-sectional view of the conventional laminated varistor array,
H sectional view

[Explanation of symbols]

 Reference Signs List 1 laminate 2 ceramic layer 3a first internal electrode layer 3b second internal electrode layer 4a first external electrode 4b second external electrode

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Keiichi Noi 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F-term (reference) 5E034 CA07 CB01 CC03 DA02 DA07 DC01 DC06 DC10 DC07

Claims (5)

[Claims] 1. A ceramic body in which a plurality of ceramic layers and a plurality of internal electrodes are laminated, and provided on a surface of the ceramic body so as to face the ceramic body via the ceramic body, and electrically connect the internal electrodes to the ceramic body. And a plurality of external electrodes connected to the multilayer ceramic array, wherein the internal electrodes facing each other via the ceramic layer are connected to the external electrodes that are asymmetric and different from each other. 2. The multilayer ceramic array according to claim 1, wherein a width of the internal electrode is larger at a portion connected to the external electrode than at a portion facing the ceramic electrode via the ceramic layer. 3. The multilayer ceramic array according to claim 1, wherein adjacent internal electrodes are non-similar. 4. The multilayer ceramic array according to claim 1, wherein the internal electrodes have curved corners. 5. The multilayer ceramic array according to claim 1, wherein the ceramic layer is a semiconductor ceramic layer exhibiting a voltage non-linear resistance characteristic.