JP2000330512A - Method for driving discharge tube for display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for driving a discharge tube to display a highly luminous and highly accurate picture. SOLUTION: In this driving method, when a 4-electrode structure discharge tube for display, which is provided with two pairs of electrodes of a pair of electrodes for display in which respective pixels are covered with a dielectric layer and a pair of electrodes for address and in which at least one address electrode is covered with the dielectric layer is driven and at the time of performing assigning intensity levels by using plural subframes into which one picture signal frame is divided in time, a picture is displayed by addressing the difference of picture information of consecutive two subframes and by moving the discharge on either of the first address electrodes and the electrodes for display to the discharge between the electrodes for display by using wall electric charges formed on the first address electrodes in a preceding subframe.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a display discharge tube, and more particularly to a method for driving a display discharge tube for selecting a pixel by an address operation using plasma discharge.

[0002]

2. Description of the Related Art A display discharge tube for selecting pixels by an address operation using plasma discharge, a so-called plasma display panel (hereinafter abbreviated as PDP) is a direct current (DC) type.
Type), an AC type (AC type), or a hybrid type combining these.

A conventional AC PDP will be described with reference to FIGS. Figure 19 shows the Japanese Patent Publication No. 3-7646.
No. 8 is a schematic perspective view of a conventional AC PDP, and FIG. 20 is a schematic cross-sectional view of the conventional AC PDP.

In FIGS. 19 and 20, 1 is a transparent front glass substrate as a first substrate, 2 is a rear glass substrate as a second substrate, 3 is a partition, 5 is a display electrode (memory electrode), 5a is a mother electrode, 5b is a transparent electrode, 11 is a first address electrode, 11a is a mother electrode, 11b is a transparent electrode, 7 is a second address electrode, 8a is a transparent dielectric layer, and 9 is a protective film (M
gO) and 10 are phosphors of RGB three primary colors. In addition,
In FIG. 20, in order to facilitate understanding of the structure, the second
The substrate is shown rotated by 90 ° with respect to the first substrate.

A plurality of parallel second stripe-shaped second address electrodes 7 are formed on the rear glass substrate 2 by a thick film technique such as a screen printing method or a thin film technique such as vapor deposition or etching. Also, a screen printing method is used such that the stripe-shaped partition walls 3 surround the second address electrodes 7 in parallel with the second address electrodes 7 on the rear glass substrate 2.
It is formed by a sand blast method or the like. Phosphors 10 of three primary colors of RGB are separately applied to the inside of the stripe-shaped partition walls 3 by a screen printing method, a sand blast method, or the like for each color.

A plurality of second address electrodes 7 formed on the back glass substrate 2 are provided on the transparent front glass substrate 1 forming a tube in cooperation with the back glass substrate 2 so as to be orthogonal to the plurality of second address electrodes 7. A first address electrode 11 and a display electrode 5 which are parallel to each other are formed by adhesion. First address electrode 11
A transparent dielectric layer 8a is formed on the display electrode 5 by printing or the like, and a protective film (MgO film) 9 is deposited thereon. In addition, a discharge gas is sealed in the inside of the tube constituted by the front glass substrate 1, the rear glass substrate 2, and the like.

In image display, an address discharge is performed between the second address electrode 7 and the first address electrode 11, and then a display discharge is performed between the first address electrode 11 and the display electrode 5. The phosphor 10 is excited by ultraviolet rays generated by discharge plasma to emit visible light, and this light is displayed on the image through the front glass substrate 1.

[0008]

In the AC type PDP according to the prior art shown in FIG. 19, the control of the presence / absence of discharge between the adjacent first address electrode and the display electrode is performed by controlling the first address electrode of the adjacent display cell. This is performed based on the difference in distance from the display electrode. For this reason, PDPs are required while ensuring the accuracy of electrode dimensions.
However, there is a problem that it is difficult to achieve high definition and high brightness. Generally, by increasing the distance between display electrodes, high brightness and
Although the efficiency can be increased, the discharge voltage increases when the distance between the electrodes is increased. Therefore, there is a problem in that the driving circuit is expensive in the conventional technology, and practical application is difficult.

An object of the present invention is to solve the above-mentioned problems of the conventional PDP and to provide a driving method of a display discharge tube capable of displaying a high-brightness and high-definition image with a simple configuration.

[0010]

The outline of the configuration of the present invention for achieving the above object is as follows.

(1) A display discharge tube to which the driving method of the present invention is applied has two pairs of a display electrode pair covered with a dielectric layer and an address electrode pair in each pixel (display cell). A four-electrode structure including an electrode pair, that is, four electrodes, wherein at least one address electrode is covered with a dielectric layer. In the driving method of the present invention, a main discharge for display is performed between the electrodes of the display electrode pair, and then an address discharge is performed between a first address electrode and a second address electrode according to a display image signal. A wall charge is formed on at least the first address electrode by the address discharge, and the main discharge is continued, and one image signal frame is temporally divided into a plurality of sub-frames to perform image gradation display. . In the display discharge tube driving method according to the present invention, the image information of two consecutive sub-frames are compared, and the difference between the image information of the two sub-frames is addressed, and the difference between the image information of the two sub-frames is applied to the first address electrode in the previous sub-frame A main discharge for displaying an image by transferring a discharge between the first address electrode and the display electrode to a discharge between the display electrodes by using the formed wall charge. , The number of address discharges is reduced, the contrast of the displayed image is improved, and the driving pulse applied to the display discharge tube is reduced to reduce the power consumption.

(2) In the driving method of the display discharge tube of the present invention, a driver for applying a pulse or a voltage to the second address electrode of the display discharge tube having the four-electrode structure is independently installed for each of RGB colors. , R, G, and B are applied with different widths or voltages, and an optimum width and voltage pulse are applied to each of the RGB electrodes to stabilize the address discharge between the first address electrode and the second address electrode. Further, the driver for the second address electrode may be any one of the three colors RGB.
Only the colors are independently provided, and a pulse having a width and voltage different from those of the other two colors is applied to stabilize the address discharge between the first address electrode and the second address electrode.

(3) The display discharge tube driving method according to the present invention performs a gray scale display by temporally dividing one frame into a plurality of sub-frames by the display electrode having the four-electrode structure. In a sub-frame having an image signal, a discharge sustaining pulse for maintaining a main discharge is applied between the electrodes of the display electrode. In a sub-frame having no image signal, a main discharge is maintained between the electrodes of the display electrode. Is not applied.

(4) In the driving method of the display discharge tube of the present invention, the reset discharge for initializing the discharge cells on the screen by the display discharge tube having the four-electrode structure is performed in a frame having an image signal, and the image signal is output. This is not performed for frames without.

(5) In the method of driving a display discharge tube of the present invention, a period is provided in which wall charges formed by the main discharge of the display electrode having a four-electrode structure are erased by applying a wall charge erasing pulse. The wall charge erasing pulse includes a pulse train having a voltage lower than the voltage of the pulse for maintaining the main discharge. Further, in the driving method of the display discharge tube according to the present invention, the voltage of the wall charge erasing pulse train is a value less than the minimum discharge sustaining voltage. Further, the applied voltage of the wall charge erasing pulse train gradually decreases to a value less than the minimum discharge sustaining voltage. In the driving method of the display discharge tube of the present invention, after applying the wall charge erasing pulse train, a wall charge erasing pulse having a value equal to or higher than the minimum discharge sustaining voltage is applied to the display electrode pair.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 2 is an exploded perspective view illustrating a schematic structure of a display discharge tube according to this embodiment, and FIG. 3 is a cross-sectional view illustrating a schematic structure of the display discharge tube shown in FIG. .
In FIG. 3, the second substrate is shown rotated by 90 ° with respect to the first substrate in order to facilitate understanding of the structure. This display discharge tube is used as a first substrate,
For example, using a transparent glass substrate, the front glass substrate 1
And Further, as the second substrate, for example, a transparent glass substrate is used, which is referred to as a back glass substrate 2.

The periphery of the front glass substrate 1 and the rear glass substrate 2 is sealed with frit glass, and the following structure is housed in a sealed tube, and the tube is evacuated to a vacuum. Then, helium (He), neon (Ne), argon (Ar), etc. and xenon (Xe)
A discharge gas such as a mixed gas of the above is sealed.

The structure housed in the tube is formed as follows. The second address electrode 7 is formed on the rear glass substrate 2 by a thin film process or a thick film process such as printing. Next, a white dielectric layer 8b is formed on the second address electrode 7.
Is formed by printing or the like, and then the stripe-shaped partition walls 3 are formed by screen printing, sandblasting, or the like. The stripe-shaped barrier ribs 3 are arranged in parallel with the second address electrodes 7. Next, the phosphors 10 of the three primary colors RGB are formed on the second address electrode 7 and on the inner wall surface of the stripe-shaped partition wall 3 by a method such as printing.

On the other hand, in FIGS. 2 and 3, a display electrode 5 composed of electrode pairs 5M1 and 5M2 is formed on the front glass substrate 1 by a thin film process or a thick film process such as printing. The electrode pair 5M1, 5M2 of the display electrode 5
Between them, the first address electrode 6 is formed by a thin film process or a thick film process such as printing. On the electrode pairs 5M1, 5M2 of the display electrode 5 and the first address electrode 6, a transparent dielectric layer 8a, grid-like partition walls 4, and a protective film 9 are formed.

The transparent dielectric layer 8a is formed by printing an insulator made of transparent glass or the like, and the grid-like partition 4 is formed by printing an insulator made of black glass or the like. The protective film 9 is an oxide thin film such as MgO having a high secondary electron emissivity, and is formed by an evaporation method or the like.

One display cell formed by a discharge region defined by the grid-like partition walls 4 on the front glass substrate 1 side and the stripe-like partition walls 3 on the rear glass substrate 2 side has two display electrodes 5. The electrode pairs 5M1 and 5M2, the first address electrode 6, and the second address electrode 7 are arranged.

By separating the address electrode and the display electrode, the display electrode can share the electrode 5M1 and the electrode 5M2 which form an electrode pair in the discharge region of the adjacent cell. For example, a discharge space (discharge region) can be separated by forming a grid-like partition 4 on the substantially center of each of 5M1 and 5M2 so that two sides thereof overlap.

The display discharge tube of this embodiment is manufactured as follows. Hereinafter, the process will be described with reference to the process chart of FIG. 4 which outlines the manufacturing process of the display discharge tube according to the present invention.

Front glass substrate 1 and rear glass substrate 2
A soda glass plate having a thickness of 2.0 mm was used. The display cell pitch is 0.33 mm in width and 1.0 mm in length. In addition,
The thickness of the glass substrate is not particularly limited as long as it has a vacuum strength and there is no problem in handling during manufacture. Further, the material of the glass is preferable to soda glass as long as high strain point glass can be used.

First, the display electrode 5 is provided on the front glass substrate 1.
And the transparent electrodes 5b and 6b as the first address electrodes 6 are respectively 0.65 m wide.
For example, a pattern is formed to a thickness of 0.15 mm with an ITO film. Next, in a thin film process, for example, a Cr-Cu-
The Cr multilayer film is formed as mother electrodes 5a and 6a. By using the transparent electrode 5b and the mother electrode 5a for the display electrode 5, it is possible to increase the electrode area while suppressing a decrease in light transmittance and an increase in electric resistance.

The electrode width of the electrode pair 5M1 and 5M2 of the display electrode 5 is as follows when the discharge cell (discharge area) pitch is 1.0 mm.
It is approximately 0.05-0.8 mm, and the electrode pairs 5M1, 5M2
Has a width of 0.1 to 0.8 mm. If the width of the electrode pair 5M1 and 5M2 of the display electrode is 0.8 mm or more, the electrode width of the first address electrode 6 formed on the same substrate cannot be sufficiently secured, and it takes time for address discharge. Absent.

If the electrode width of the transparent electrodes 5b constituting the electrode pairs 5M1 and 5M2 is 0.1 mm or less, a thick mother electrode is required to reduce the electric resistance of the transparent electrodes. Can not.

The width of the mother electrode 5a is approximately 0.05 to 0.3 mm.
It is. When the width of the mother electrode 5a is 0.3 mm or more, the light transmittance of the discharge cell decreases, and the luminance decreases. If the width of the mother electrode 5a is 0.05 mm or less, the electric resistance of the display electrode 5 (transparent electrode) does not decrease, and driving is difficult. In addition,
The first address electrode 6 also has an electrode pair 5M1 of the display electrode 5,
When a transparent electrode and a mother electrode are used as in 5M2, a decrease in light transmittance and an increase in electric resistance can be suppressed, and the electrode area can be increased.

The electrode width of the first address electrode is approximately 0.03 to 0.4 mm when the discharge cell pitch is 1.0 mm.
If the electrode width of the first address electrode 6 is 0.03 mm or less, the electrode area becomes small, so that the voltage of the address discharge becomes high and a long time is required to generate a reliable discharge, which is not preferable. The electrode width of the first address electrode 6 is 0.4
mm or more, the electrode width of the display electrode 5 becomes narrow,
It is not preferable because it is difficult to increase the luminance.

The electrode width of the mother electrode formed on the transparent electrode of the first address electrode is approximately 0.03 to 0.1 mm. When the electrode width of the mother electrode is 0.1 mm or more, the transmittance of the discharge cells is reduced, and the luminance is undesirably reduced. Also,
If the width of the mother electrode is 0.03 mm or less, the electric resistance of the first address electrode does not decrease, so that driving becomes difficult.

Here, the electrode pair 5 of the display electrode 5 is used.
Although an example in which transparent electrodes are used for M1, 5M2 and the first address electrode 6 has been described, the electrode pair 5M1, 5M of the display electrode 5 is used.
A transparent electrode may not be used for each of the M2 and the first address electrode. For example, the electrode pair 5M1 of the display electrode 5,
In a pattern composed of only the mother electrode without using a transparent electrode for 5M2, for example, if the electrode width is set to 0.2 to 0.6 mm, the electrode interval becomes wider and the discharge sustaining voltage becomes higher. Luminous efficiency can be increased. In addition, the mother electrode 5
The materials a and 6a only need to have a small electric resistance.
There is no problem even if it is a metal such as i, Al, Au or the like, or a multilayer film such as Cr-Au-Cr. In the above, the example in which the ITO film is used for the transparent electrode has been described. However, since it is sufficient that a sufficient electrode area can be secured without lowering the light transmittance, a Nesa film or the like can be used.

After the above-mentioned electrodes are formed, a transparent dielectric layer 8a made of transparent glass or the like is formed on the entire surface to cover the electrodes, and a pair of electrodes 5M1, 5M constituting the display electrode 5 is formed.
On the outline of the mother electrode 5a formed on the second transparent electrode 5b,
A grid-like partition wall 4 is formed at a height of 0.03 mm so that two opposing sides of the four sides overlap. This lattice-shaped partition 4 is made of black glass or the like. When the grid-like partition walls 4 are laminated by, for example, one or more times of printing, it is preferable that at least the first layer be black because the contrast of a displayed image is improved.

Further, if the grid-like partition 4 is formed on the transparent electrode 5b of the display electrode, there is no problem in the image display function. It is preferable to form a partition portion of the grid-like partition 4 parallel to the direction in which the display electrode 5 extends so as to overlap the mother electrode 5a, since a decrease in transmittance can be suppressed and a display image becomes bright.

After forming the grid-like partition walls 4, an MgO film is formed as a protective film 9 to a thickness of 500 to 800 nm by a known method such as electron beam evaporation (EB evaporation).

On the other hand, on the rear glass substrate 2, a second address electrode 7 is formed of Ag, Ni, A with an electrode width of 0.10 mm.
l, metal such as Au, Cr-Cu-Cr, Cr-Au-C
It is formed by a printing method or a photo process with a multilayer film such as r. A white dielectric layer 8b is formed on the second address electrode 7.
Is formed to a thickness of 0.015 mm by printing an insulating material such as white glass. The electrode width of the second address electrode 7 is approximately 0.05 to 5 when the discharge cell pitch is 0.33 mm.
0.2 mm. When the electrode width is 0.05 mm or less, the discharge starting voltage becomes high or the discharge takes time, so that it is difficult to reliably perform the address discharge. The white dielectric 8b has no significant difference in basic functions whether or not it is formed. However, the utilization efficiency of the reflected light of the phosphor 10 is improved by the white dielectric 8b, and the stripe-shaped partition walls 3 are not used.
Address electrode 7 when forming by the sand blast method
This has the advantage of serving as a protective film.

Next, the stripe-shaped partition wall 3 is
It is formed by printing, sand blasting, or the like so as to be located in the gap in parallel with the address electrode 7.

Thereafter, phosphors 10 of each color of RGB are formed on the second address electrode 7 and on the inner wall surface of the stripe-shaped partition wall 3 by printing or the like. The width of the stripe-shaped partition wall 3 is 0.06 mm, and the height is 0.15 mm. The width of the stripe-shaped partition wall 3 is approximately 0.02 to 0.1 mm,
The height is 0.05 to 0.25 mm, and is formed by printing or sandblasting. If the width of the stripe-shaped partition walls 3 is 0.1 mm or more, the aperture ratio becomes low, and it becomes difficult to increase the luminance. The opening ratio of the stripe-shaped partition walls 3 is improved as the width is reduced. However, if the width is 0.02 mm or less, partition walls having a sufficient height cannot be formed. If the height of the stripe-shaped partition walls 3 is 0.05 mm or less, a sufficient amount of phosphor cannot be applied, and if the height of the stripe-shaped partition walls 3 is 0.25 mm or more, the height of the partition walls 3 cannot be increased. It becomes difficult to form. This back glass substrate 2
Then, a phosphor 10 in a paste state is formed by printing or the like so as to correspond to each of the RGB colors.

The front glass substrate 1 thus manufactured
And the back glass substrate 2 so that two sides of a stripe-shaped partition wall 3 formed on the back glass substrate 2 and a lattice-shaped partition wall 4 formed on the front glass substrate 1 overlap, and an exhaust pipe (not shown). After sealing with frit glass so that) is fixed, exhaust is performed. Next, gas is sealed and the chip is turned off.
The sealing gas is an ionizable gas such as He-Xe or Ne-Xe, and is sealed at 25 ° C. at a pressure of approximately 400 Torr.

Next, a method of driving the display discharge tube formed as described above will be described. FIG. 5 is a circuit block diagram showing a schematic configuration of a display device using a display discharge tube to which the driving method of the present invention is applied. P having the above configuration
Around the DP 20, a display electrode driver 21, a first address electrode driver IC group (1, 2, 3,... M) 22, and a second address electrode driver IC group (1, 2, 3,... N) 2
3a, 23b and a controller 24 are arranged.

Based on a video signal and a synchronizing signal input from a display signal source such as a host computer or a television receiving circuit, the controller 24 generates a display signal and an address signal at a predetermined timing, and
1. A video signal is displayed on the PDP 20 as a visible image by applying it to the first address electrode driver IC group 22 and the second address electrode driver IC group 23a, 23b.

FIG. 6 is a diagram showing a driving method for realizing a gray scale display by temporally dividing one frame into a plurality of sub-frames. The example which displays is shown. In the address blocks in the figure, an address period for performing an address discharge, which is a period that is not necessarily required, a reset period for performing a reset discharge, which is not necessarily required, and an electric field application that is not necessarily required, are applied. One or two electric field application periods are included. The sustain period includes a main discharge for display, which is a discharge performed between the display electrode pairs, and a trigger discharge for shifting a discharge between the first address electrode and one of the display electrodes to a discharge between the display electrode pairs. .

FIG. 7 is a driving waveform diagram for explaining a driving method of the display discharge tube according to the present embodiment. In FIG. 7, first, in order to make all the discharge cells on the screen of the display discharge tube uniform, that is, the electrodes 5M1 and 5M2 and the first address electrode 6, which constitute the electrode pair of the display electrode 5, Second
In order to reset the charge on the address electrode 7 to an initial state, a reset discharge is performed between the display electrode 5M2 and the first address electrode 6 to erase the wall charge on the electrode in the display cell.

That is, during the reset period shown in FIG.
A pulse of _PRM is applied to M2 and the first address electrode 6 (6-
1,6-2, to discharge by applying a _{P RC} pulses ··· 6-n). Since this pulse is intended to erase wall charges, it is a narrow pulse. In general, in a so-called AC type PDP, wall charges are not generated when the pulse width is small during discharge, and wall charges are generated when the pulse width is wide. In this embodiment, the pulse widths of P _RM and P _RC are 1 μS, and the voltages of P _{RM and} + _RC are +400 V and −150 V, respectively.

This reset discharge is for the purpose of erasing the electric charge on the electrode surface in the cell. If a discharge occurs, the reset discharge is caused between the display electrode pair, the address electrode pair, the display electrode or the electrode pair. The reset discharge may be performed between the address electrodes or the electrode pairs. When a reset discharge is performed between the first address electrode 6 and a display electrode, for example, 5M2, less light emission is caused by the reset discharge than when a reset discharge is performed between a pair of display electrodes, and the contrast of a displayed image is improved.

For example, the display cell pitch is 0.33 m in width.
m, 1.00 mm long, the electrode 5M1 and the electrode 5M2 each have a width of 0.6 mm, and the first address electrode 6 has a width of 0.6 mm.
In the case of 15 mm, assuming that the brightness due to the discharge between the electrodes 5M1 and 5M2 of the electrode pair constituting the display electrode 5 is 1, the brightness due to the discharge between the first address electrode 6 and the electrode 5M1 is about 0.5. is there.

That is, the reset discharge is applied to the display electrode 5M.
1 and 5M2, the reset discharge is performed between the first address electrode 6 and the display electrode 5M1 or the reset discharge is performed between the first address electrode 6 and the display electrodes 5M1 and 5M2. , And the contrast of the displayed image can be improved.

After this reset discharge (after erasing the entire wall charge), the waveforms shown are applied to the display electrodes 5M1, 5M2 and the first address electrode 6 during the electric field 1 application period in FIG.

The display electrodes 5M1, 5M2 and the first address electrode 6 are on the first substrate, a positive voltage is applied to the first substrate, the second address electrode is on the second substrate, Since the second substrate side remains at 0 V, an electric field is applied between the electrode group of the first substrate and the electrode group of the second substrate, and a negative space charge generated by a discharge generated during the reset period is generated. Positive space charges are accumulated in the electrode group of the first substrate as wall charges in the electrode group of the second substrate.

It is to be noted that there is no problem in basic driving without applying an electric field after the reset discharge. However, by applying the electric field, space charges in the display cell are accumulated on the electrodes, and the address voltage is reduced. Can be lowered. In other words, an electric field may be applied relatively between the address electrode pairs, and the voltage may be applied only to the first address electrode 6, for example. Note that there is no problem in the basic function whether or not a voltage is applied to the display electrode pair.

Due to the wall charges, the discharge between the first address electrode 6 and the second address electrode 7 during the address period in FIG. 7 is easier than in the case where the waveform during the electric field 1 application period in FIG. 7 is not applied. Can be awakened. In this embodiment,
V _M2 is ₊ 70V, _{V C} + is + 80V.

After the electric field 1 application period shown in FIG. 7, the waveforms of the address period are displayed by the display electrodes 5M1, 5M2, the first address electrodes 6 (6-1, 6-2,..., 6-n) and the second It is applied to the address electrodes 7 (7-1,..., 7-n).
The first address electrodes 6 (6-1, 6-2,.
n) is a so-called scan electrode, the second address electrode 7 (7-
1,..., 7-n) correspond to so-called data electrodes.

The first address electrode generates a discharge (address discharge) between the first address electrode and the second address electrode.
A pulse P _C of the negative polarity to the address electrodes 6, a positive pulse P _A is applied to the second address electrode 7, to accumulate wall charges on the first address electrode and the second address electrode 7.

The second of the subframes in which the reset discharge has been performed
Pulse P _A applied to the address electrodes, rather than an address difference data obtained by comparing the image information between the two consecutive subframes, a data processing based on the sub-frame itself image information. A method of creating a difference address by comparing image information between two consecutive subframes and a method of maintaining discharge at the display electrode will be described later with reference to FIGS.

At this time, a positive voltage V is applied to the display electrode 5M1.
_A negative voltage V _M1− is applied to _{M1 +} and 5M2. VM1 ₊ applied to the display electrode 5M1 is a voltage that does not discharge any of the other electrodes (the display electrode 5M2, the first address electrode 6, and the second address electrode 7). _M1- is another electrode (display electrode 5M1, first address electrode 6, and second address electrode 7).
Is a voltage that does not discharge any of the above.

In this embodiment, VM1 ₊ is +60.
_{V, V M1-} is -60 _V, P C, the pulse width with _{P A} 4
a [mu] S, the voltage is _{P C} -150V, _{P A} is + 80V
It is.

Even if wall charges are accumulated on the address electrodes by the address discharge, the space charges remain, and the wall charges can be accumulated on the display electrodes by applying a voltage to the display electrodes, and the sustain period is maintained. Thus, the first discharge can be easily caused. Therefore, the waveform shown in the electric field 2 application period is applied to the display electrodes 5M1, 5M2 and the first address electrode 6 after the address period in FIG.

During the electric field 2 application period, space charges generated by the address discharge are accumulated as wall charges on the display electrodes 5M1, 5M2 and the first address electrode 6. By providing the electric field 2 application period, the space charge in the cell is accumulated on the electrode to which the voltage is applied, the voltage of the first discharge in the sustain period is reduced, and the space charge is prevented from moving to the unaddressed cell. Reduce discharge. In this embodiment, V
_{M1 +} is + _{60V, V M1-} is _{-60V, V C-} -1
50V.

After the electric field 2 application period in FIG. 7, the waveform of the sustain period is applied to the display electrodes 5M1, 5M2 and the first address electrode 6. At the beginning of the sustain period, that is, before the main discharge for display, the pulse P is applied to the first address electrode 6.
_TC, applying a pulse _{P TM1} to the display electrodes 5M1, cause trigger discharge between the electrodes, the pulse P the discharge
The display is shifted to another display electrode 5M2 to which _TM2 has been applied.

The pulse P _TC is a pulse (1 μS) having such a width that wall charges are not accumulated, and the pulse P _TM1 and the pulse P _TM2 are pulses (4) having a width such that wall charges are accumulated.
μS). Further, in this _embodiment, the _{P TC} +80
V and _PTM1 are -100V, and _PTM2 is + 140V.

After the discharge between the first address electrode 6 and the display electrode 5M1 has shifted to the discharge between the display electrodes 5M1 and 5M2, two types of pulses PSM ₊ are applied between the display electrodes 5M1 and 5M2. , _PSM- are applied alternately to perform main discharge. The pulse width is 4 μS for both P _SSM- and P _{SSM +}
It is. The voltages of P _SSM− and P _{SSM +} vary depending on the structure of the discharge tube, the composition of the sealed discharge gas, and the like. In this embodiment, P _SSM− = + 30 V and P _{SSM +} = −200 V.

In this embodiment, an example in which a trigger signal is input to the first address electrode 6 has been described. However, there is no problem in basic functions without inputting a trigger signal. In that case, a trigger discharge may be performed using wall charges on the first address electrode 6. By applying a trigger signal to the first address electrode as in the present embodiment, the range of voltage setting that can be driven can be increased.

In this embodiment, an example is described in which pulses of both positive and negative polarities are applied to the pulses during the sustain period. However, the present invention is not limited to this. If there is a relatively predetermined potential difference between the display electrodes 5M1 and 5M2, the pulse applied for the main discharge may be a pulse having only a negative polarity or a pulse having only a positive polarity.

In this embodiment, as shown in FIG. 7, a reset period, an electric field 1 application period, an address period, an electric field 2 application period, a sustain period, and a cycle adjustment period are used.
The present invention can be similarly applied as long as there is at least a reset period and a sustain period in which a main discharge for display performed between the display electrode pairs is performed. Note that the reset period does not necessarily need to be set for each sub-frame, and the contrast of a display image can be improved by reducing the number of resets.

When the image information is compared between two subframes (hereinafter abbreviated as SF) continuous in FIG. 8 to create difference address data, the positions of the rows and columns of the image data on the subframes Show the relationship.

FIG. 1A is a waveform chart for explaining a driving method of the display discharge tube according to the present embodiment. In FIG. 1A,
Although the image signals and address signals from the Nth row and the Kth column have been described, the same processing as described below is performed for other rows and columns.

In FIG. 1A, the image signals of SF2 and SF3 are the same. At this time, at the end of the sustain period of SF2, a width (4 μS) at which wall charges are accumulated.
Of the display electrodes 5M1 and 5M
A wall charge is formed on M2, and the address signals of SF3 are all L
At the low level, no address discharge is caused. In FIG. 1A, in order to prevent an address discharge from occurring in SF3, the address period and the electric field 2 application period described in FIG. 7 may be omitted.

In the sustain period of SF3, the driving waveform of the sustain period shown in FIG. 7 is applied. In FIG. 7, an operation is performed in which the wall charge formed on the first address electrode during the address period is transferred from one discharge of the first address electrode and the display electrode to a discharge between the display electrodes by a trigger signal. In FIG. 1A, since a wall charge has already been formed on the display electrode of the cell which has undergone the address discharge in SF2, it is applied to the first address electrode in the cell on which the wall charge has been formed. P _TC is not work enabled, occurred discharge between the display electrodes by the pulse P _TM2 applied to pulse P _TM1 and the display electrodes 5M2 applied to the display electrode 5M1, then sustaining pulse P
Main discharge for display is continued by alternately applying _{SM +} and _PSM- .

In a cell in which no address discharge occurs and no wall charge is formed in SF2, P applied to the first address electrode
_TC, depending on the pulse _{P TM2} applied to pulse _{P TM1} and the display electrodes 5M2 applied to the display electrode 5M1, discharge is not occurred between the display electrodes. Therefore, even if the sustaining pulses P _{SM +} and P _SM− are applied alternately _thereafter , the main discharge does not occur. Therefore, even if all the address signals are at the Low level (or the address period and the electric field 2 application period shown in FIG. 7 are omitted), a main discharge for image display can be generated. The pulse widths and voltages of the pulses P _TC , P _TM1 , P _TM2 , P _{SM +} and P _SM− are 1 _μS and ₊₈₀ , respectively.
V, 4μS, -100V, 4μS, + 140V, 4μ
S, +30 V, 4 μS, −200 V.

(Embodiment 2) In this embodiment, as shown in FIG. 1B, there is an image signal in the K + 2th column of SF2.
There is no image signal in the K + 2 column of SF3,
There is no image signal in the third column, and there is an image signal in the K + 3 column of SF3.

In this embodiment, if the wall charge formed on the display electrode in SF2 is left, a discharge occurs in the cells in the (K + 2) th column where the main discharge should not be performed in SF3.
Cannot be addressed by SF3.

Therefore, the sustaining pulses P _{SM +} and P _SM− applied at the end of the sustain period of SF2 are set to a pulse width (1 μS) that does not accumulate wall charges, and the wall of the cell where the main discharge has occurred is set. The charge is erased and SF3
Now, apply the same address signal as the SF3 image signal,
The same processing as in the address period, the electric field 2 application period, and the sustain period shown in FIG. 7 is performed.

In this embodiment, the pulse width of the last pulse P _{SM +} and P _{SM− in} the sustain period of SF2 is set to 1 _μS.
The pulse voltage and pulse width applied during the address period, the electric field 2 application period, and the sustain period are the same as those in the first embodiment, except for the following.

(Embodiment 3) FIG. 1C shows that K +
There is no image signal in the third column, there is an image signal in the (K + 3) th column of SF3, and the image signals in the other columns are SF2 and SF3.
Are the same.

In the present embodiment, the wall charges formed on the display electrodes in SF2 are left, only the cells to be newly addressed are addressed in SF3, and the wall charges formed on the first address electrodes are changed by the trigger signal. By performing an operation of shifting from the discharge of one of the first address electrode and the display electrode to the discharge between the display electrodes, a main discharge for display according to the image signal of SF3 can be performed.

Therefore, at the end of the sustain period of SF2, a discharge sustaining pulse of 4 μS to the extent that wall charges are accumulated is applied to form wall charges on the display electrodes 5M1 and 5M2, and the address signal of SF3 is applied. As shown in FIG. 1C, an address operation is performed by treating only an increase in the image signal in SF3 with respect to the image signal in SF2 as an address signal.

The cell newly addressed in SF3 is the first cell
The wall charges formed on the address electrodes are transferred from one of the first address electrode and the display electrode to the discharge between the display electrodes by a trigger signal, thereby forming wall charges on the display electrodes. be able to.

[0078] Since the SF2 already wall charges in the display electrode of the address discharged cells are formed, the formed cell wall charges, P _TC applied to the first address electrode
Although not work enabled, it occurred discharge between the display electrodes by the pulse P _TM2 applied to pulse P _TM1 and the display electrodes 5M2 applied to the display electrode 5M1, then the sustaining pulse P _{SM +} and Main discharge can be continued by alternately applying _PSM- .

In a cell where no address discharge occurs and no wall charge is formed in SF2, the P applied to the first address electrode
_TC, the discharge does not occur between the display electrode by a pulse _{P TM2} applied to pulse _{P TM1} and the display electrodes 5M2 applied to the display electrode 5M1. Therefore, even if the sustaining pulses P _{SM +} and P _SM− are alternately applied _thereafter , the main discharge for display does not occur.

Therefore, the SF3 image signal is compared with the SF3 image signal.
Even if only the increased image signal is used as the address signal,
Main discharge according to the image signal can be generated.

In this embodiment, the pulse PA applied to the second address electrode in SF3 is different from the image signal in SF2 by S
The voltages and pulse widths applied during the address period, the electric field 2 application period, and the sustain period are the same as those in the first embodiment, except that the image signal is increased by F3.

The operations of the above-described first to third embodiments are performed by comparing SF1 and SF2, SF2 and SF3, and SF3 and SF.
4, SF4 and SF5, SF5 and SF6, SF6 and SF7
And SF7 and SF8.

As a method of temporally dividing one frame into a plurality of sub-frames to realize a gradation display,
Although the example in which one frame is temporally divided into eight subframes has been described, the driving method of the present embodiment is also effective in a method in which one frame is temporally divided into six to ten subframes to realize gray scale display. It is.

In this embodiment, the comparison between subframes is performed between SF1 and SF8. During this time, wall charges may be left on the display electrodes, so that the display on the screen of the display discharge tube may be left. The resetting of all discharge cells to a uniform state will be performed at the beginning of SF1, but it is also possible to perform comparison between subframes over two or more frames.
When comparing between sub-frames over two or more frames, the reset may be performed in the first frame of the frames to be compared.

Example 4 A PDP used in this example was manufactured in the same manner as in Example 1. FIG. 9 is a circuit block diagram showing a schematic configuration of a display device using a display discharge tube to which the driving method of the present embodiment is applied. Around the PDP 20, a display electrode driver 21, a first address electrode driver IC group (1, 2, 3,... M) 22, and a second address electrode driver IC group (1, 2, 3,... N) 23a, 23b , And the controller 24 are arranged in the same manner as in the first embodiment. In this embodiment, an independent driver IC group is arranged for each of the RGB colors so that a signal having a different pulse width or pulse voltage can be applied to each of the second address electrodes RGB.

The controller 24 generates a display signal and an address signal at a predetermined timing based on a video signal and a synchronizing signal input from a display signal source such as a host computer or a television receiver circuit.
1. A video signal is displayed on the PDP 20 as a visible image by applying it to the first address electrode driver IC group 22 and the second address electrode driver IC group 23a, 23b.

FIG. 10 is an explanatory diagram of driving waveforms of the display discharge tube of this embodiment. FIG. 10 shows the second address electrode 7 (7-
1R, 7-1G, 7-1B,..., 7-nR) are the same as the drive waveforms shown in FIG.

After the electric field 1 application period in FIG. 10, the waveforms of the address period are displayed by the display electrodes 5M1, 5M2, the first address electrodes 6 (6-1, 6-2,..., 6-n), and the second electrode.
Address electrodes 7 (7-1R, 7-1G, 7-1B,...)
., 7-nR). The first address electrode 6
(6-1, 6-2,... 6-n) are so-called scan electrodes,
The second address electrodes 7 (7-1R, 7-1G, 7-1B,...)
.., 7-nR) correspond to so-called data electrodes.

The first address electrode and the second address electrode are driven by the first and second address electrodes so that a potential difference is generated between the first and second address electrodes.
A pulse _{P C} of the negative polarity to the address electrodes 6, a positive polarity pulse _P AR to the second address electrode _7, P _AG, applying a _{P AB,} the wall charges on the first address electrode and the second address electrodes 7 Let it accumulate. RGB on the second address electrode 7
Are formed, but if the phosphors are different in this manner, the address discharge starting voltages of the RGB cells will be different.

As an example, a case where the address discharge starting voltage of the G cell is the highest, followed by the B cell and the R cell will be described. For example, when cells of each color of RGB are driven by a common driver IC with reference to a pulse voltage applied to the second address electrode of the G cell, a disadvantage that a pulse of an unnecessarily high voltage is applied to the R and B cells occurs. . A driving method of increasing the pulse width to lower the discharge starting voltage is also conceivable. However, if the second address electrode driver IC is common to each of the RGB cells, the driving cannot be performed at a voltage lower than the discharging start voltage of the G cell, and R and The inconvenience that an unnecessarily high voltage pulse is applied to the B cell remains.

As shown in FIG. 9, the inconvenience can be solved by separately providing a second address electrode driver IC for each of the RGB cells and applying a pulse having an optimum width or voltage to each of the RGB cells. In this case, the display electrode 5
M1 has a positive voltage VM1 ₊ , and 5M2 has a negative voltage _VM1-
Is applied. VM1 ₊ applied to the display electrode 5M1 is a voltage that does not discharge any of the other electrodes (the display electrode 5M2, the first address electrode 6, and the second address electrode 7). _M1- is a voltage that does not discharge any of the other electrodes (the display electrode 5M1, the first address electrode 6, and the second address electrode 7). Note that in this embodiment, _{VM1 +} is ₊₆₀ V and _VM1-
There _{-60V, P C, P AR,} P AG, both the pulse width of _{P AB} 4 [mu] S, the voltage is _{P C} -150 _V, the _{P AR} +
_67V, a _{P AG} is + _{80V, P AB} is + 70V,
Other drive pulse widths and voltages are the same as in the first embodiment.

(Embodiment 5) FIG. 11 is a block diagram of a display device to which the method for driving a display discharge tube of the present invention is applied.
FIG. 11 differs from the fourth embodiment in that only the second address electrode driver IC of the G cell is independently installed.
FIG. 12 shows the driving waveform of the present embodiment. In this embodiment, as shown in FIG. 12, the R cells and B cells is the same as in Example 4 except that the driving pulse P _{AR B} is applied in common. In this embodiment, VM1 ₊ is +60 V, V
_M1- is _{-60V, P C, P ARB,} P AG, none of the pulse width 4 [mu] S, the voltage is _{P C -150V, P ARB}
There + 70 _V, a 80V, _{P AG} is +, width and voltage of the driving pulse Sohoka is the same as that of the Embodiment 1.

In the present embodiment, the description has been made of the configuration in which the second address electrode driver IC is provided in which only the G cells are independent.
The present invention can be applied to a configuration in which only the R cell is configured as an independent second address electrode driver IC, or a configuration in which only the B cell is configured as an independent second address electrode driver IC.

Example 6 A PDP used in this example was produced in the same manner as in Example 1. FIG. 13 is an explanatory diagram of a drive waveform of the display discharge tube according to the present embodiment. In SF1 shown in FIG. 13, processing from the reset period to the sustain period is performed. In SF2 of FIG. 13, although there is no reset period and no electric field 1 application period in SF1, the reset period does not necessarily need to be provided for each subframe (SF), and wall charges can be erased by an erase pulse in a sustain period. Good. By doing so, the number of times the reset pulse is applied can be reduced, and the contrast of the displayed image can be improved.

Since SF2 in FIG. 13 shows a case where there is no image signal, no pulse is applied to either the first address electrode or the second address electrode during the sustain period. As described above, in the sub-frame having no image signal, the main discharge for displaying the image does not occur during the sustain period, so that it is not necessary to apply the pulse for maintaining the main discharge. That is, in a subfield where there is no image signal, when a pulse for maintaining the main discharge is applied during the sustain period, the main discharge does not occur because there is no wall charge in the first address electrode and the second address electrode, but the plasma display panel (PDP) In order to charge and discharge the stray capacitance, a reactive current not related to the display flows and power is consumed. On the other hand, if a pulse for maintaining the main discharge is not applied in the sustain period in the subfield where there is no image signal as in the present embodiment, the above-described reactive current does not occur, and the driving power can be reduced. Further, even if a display cell which is easily discharged due to a variation in shape at the time of manufacturing is in a PDP, erroneous discharge of the display cell can be avoided by the driving method of the present embodiment, so that the display image quality is improved.

As a method of temporally dividing one frame into a plurality of sub-frames to realize a gradation display,
Although the example in which one frame is temporally divided into eight subframes has been described, the driving method of the present embodiment is also effective in a method in which one frame is temporally divided into six to ten subframes to realize gray scale display. It is.

(Embodiment 7) FIG. 14 is an explanatory diagram of driving waveforms of a display discharge tube according to this embodiment. FIG. 14 shows up to the middle of SF1 in FIG. 6, that is, from the reset period to the middle of the address period in FIG.
8 is omitted. Since there are image signals in the frame N-1 and the frame N + 2 shown in FIG. 14, during the reset period, the display electrode 5M1 and the first address electrodes 6 (6-1, 6)
,..., 6-n), a reset discharge is performed in order to bring all the discharge cells into a uniform initial state. No reset discharge is performed. The determination as to whether or not there is an image signal in a specific frame can be performed by referring to the signal of the frame memory in the controller shown in FIG.

In this embodiment, as shown in FIG. 14, in the frames N and N + 1 having no image signal, neither the address discharge in the address period nor the main discharge in the sustain period occurs. Therefore, the reset discharge of the present embodiment becomes unnecessary, and the increase in the luminance level of the black display portion of the display discharge tube can be suppressed, so that the contrast of the display image increases and the image quality improves. Further, since the reset discharge is not performed in the frame having no image signal, the power supplied to the display discharge tube can be reduced.

As a method of temporally dividing one frame into a plurality of sub-frames to realize a gradation display,
Although the example in which one frame is temporally divided into eight subframes has been described, the driving method of the present embodiment is also effective in a method in which one frame is temporally divided into six to ten subframes to realize gray scale display. It is.

Example 8 A PDP used in this example was manufactured in the same manner as in Example 1. FIG. 15 is an explanatory diagram of a driving waveform of the display discharge tube according to the present embodiment. In FIG. 15, processing from the reset period to the sustain period is performed in the first embodiment.
Is the same as

In this embodiment, the wall charges on the display electrodes 5M1 and 5M2 accumulated by the main discharge after the sustain period are erased by applying a pulse as shown in FIG. 15 to the display electrodes 5M1 and 5M2. It is difficult to reliably erase the wall charges distributed over the entire display electrode by applying one of the erase pulses having a narrow pulse width or the erase pulse having a wide pulse width. That is, when a pulse having the same voltage as the pulse applied in the main discharge and having a narrow pulse width is added, in a cell which is difficult to generate a discharge due to manufacturing variations, the discharge does not spread to the entire cell and leaves wall charges. When a pulse having a wide pulse width is applied, the voltage of the pulse is set so that the voltage obtained by adding the wall charge is equal to the minimum discharge voltage. If the value is based on this, no discharge occurs in a cell that is difficult to discharge, and if the value is set in reverse, wall charges are formed in a cell that easily discharges.

In this embodiment, the erasing pulses P _SSM− and P _{SSM + having} a value less than the minimum discharge sustaining voltage are used by utilizing the metastable generated by the main discharge and the remaining space charge.
Are gradually applied to weaken the discharge, and finally the discharge is stopped to erase the wall charges. In this embodiment, wall charges can be reliably erased irrespective of variations in the ease of discharge of each cell. The pulse width of P _SSM− and P _{SSM +} is 4 μm.
S, the voltage is -185V, + 15V.

In this embodiment, an example is described in which pulses of both positive and negative polarities are applied to the erase pulse. However, the present invention is not limited to this. If there is a relatively predetermined potential difference between the display electrodes 5M1 and 5M2, the erase pulse may be a pulse having only a negative polarity or a pulse having only a positive polarity.

In this embodiment, the erasing period is provided to erase the wall charges. However, the erasing period may not be provided and the wall charges may be accumulated in the display electrode by the discharge by the last pulse of the sustain period. . At this time, the voltage and width of the applied pulse may be set so that the generated wall charges facilitate the next reset discharge. As shown in the present embodiment, the number of reset discharges can be reduced by erasing the wall charges with the pulse in the erasing period, so that a decrease in the contrast of the display image due to the reset discharge can be avoided.

In this embodiment, as shown in FIG. 15, the reset period, the electric field 1 application period, the address period, the electric field 2 application period, the sustain period, and the cycle adjustment period are used.
The same applies if there is at least a reset period, an address period during which the address discharge is performed between the address electrode pairs, and a sustain period during which the main discharge is performed between the display electrode pairs. Note that the reset period does not necessarily need to be set for each sub-frame, and the contrast of a display image can be improved by reducing the number of resets.

Example 9 A PDP used in this example was manufactured in the same manner as in Example 1. FIG. 16 is an explanatory diagram of a driving waveform of the display discharge tube according to the present embodiment. In FIG. 16, processing from the reset period to the sustain period is performed in the first embodiment.
Is the same as In this embodiment, the wall charges on the display electrodes 5M1 and 5M2 accumulated by the main discharge after the sustain period are changed into pulses ( _PSSM1- and _PSS1- P) as shown in FIG.
_{SSM1 +} , P _{SSM2 +} , P _SSM2- , ..., P
_{SSMN +} , P _SSMN− ) are displayed on the display electrodes 5M1, 5M2.
To erase. This embodiment is different from the eighth embodiment in that the voltage of the pulse applied during the wall charge erasing period is gradually lowered to be less than the minimum discharge sustaining voltage. In this embodiment, the width of the erase pulse is a both a _{4μS, P SSM1-} is _{-195V, P SSM1 +} is +25
V, and thereafter, the absolute value of each voltage was reduced by 5 V so as to be less than the minimum discharge sustaining voltage.

Example 10 A PDP used in this example was manufactured in the same manner as in Example 1. FIG. 17 is an explanatory diagram of a drive waveform of the display discharge tube according to the present embodiment. In FIG. 17, the processing from the reset period to the sustain period is the same as in the first embodiment. Pulse as the wall charges shown in Figure 17 on the display electrodes 5M1,5M2 accumulated in the main discharge after the sustain period in the present embodiment, i.e., the minimum discharge sustaining erasing pulse voltage lower than the voltage P _SSM1-, P _{SSM +}
Are applied, and then a pulse P equal to or higher than the minimum discharge sustaining voltage is applied.
_{SSM2 +} and P _{SSM +} are applied. In the present embodiment, the pulse widths of P _{SSM +} and P _SSM1- are 4 μS, P _SSM1- is -185 V, and P _{SSM1 +} is +15 _V.
V. Also, the pulse width of P _SSM2 is 1 _μS , and the voltage is −200 V.

(Example 11) A PDP used in this example was manufactured in the same manner as in Example 1. FIG. 18 is an explanatory diagram of a driving waveform of the display discharge tube according to the present embodiment. In FIG. 18, the processing from the reset period to the sustain period is the same as in the first embodiment. In the present embodiment, the wall charges on the display electrodes 5M1 and 5M2 accumulated by the main discharge after the sustain period are converted into pulses ( _PSSM1- , _PSM1 ) as shown in FIG.
_{SSM1 +} , P _{SSM2 +} , P _SSM2- , ..., P
_{SSMN +} , P _SSMN− ) are displayed on the display electrodes 5M1, 5M2.
To erase. This embodiment is different from the eighth embodiment in that the voltage of the pulse applied during the wall charge erasing period is gradually reduced to be less than the minimum discharge sustaining voltage, and finally, the pulse pairs P _{SSNM +} and P _{SSNM +} that are higher than the minimum discharge sustaining voltage. ₋ Is applied. In this embodiment, except for the pulse P _SSMN− , the width of each of the erase pulses is 4 μS,
_SSM1- is -195V and _{PSSM1 +} is + 25V. Thereafter, the absolute value of each voltage is reduced by 5V to be less than the minimum discharge sustaining voltage. Further, the pulse P _SSMN− has a pulse width of 1 _μS and a voltage of −200 V.

[0109]

As described above, according to the driving method of the present invention, an AC type PDP having a four-electrode structure can be driven with low power consumption, and a high-definition, high-quality image display can be achieved. Obtainable.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a driving waveform of a display discharge tube according to an embodiment of the present invention.

FIG. 2 is an exploded perspective view illustrating a schematic structure of a display discharge tube to which the driving method according to the embodiment of the present invention is applied.

FIG. 3 is a schematic electrode arrangement view on a first substrate of a display discharge tube to which the driving method according to the embodiment of the present invention is applied.

FIG. 4 is a process chart for explaining a manufacturing process of a display discharge tube to which the driving method according to the embodiment of the present invention is applied.

FIG. 5 is a block diagram illustrating a schematic configuration of a display device to which a driving method according to an embodiment of the present invention is applied.

FIG. 6 is an explanatory diagram of a relationship between a frame and a sub-frame for realizing gradation display used for describing a method of driving a display discharge tube according to an embodiment of the present invention.

FIG. 7 is an explanatory diagram of a driving waveform of a driving method of the display discharge tube according to the embodiment of the present invention.

FIG. 8 is a schematic diagram illustrating the position of image data on a sub-frame in the method of driving the display discharge tube according to the embodiment of the present invention.

FIG. 9 is a block diagram illustrating a schematic configuration of a display device to which a driving method according to an embodiment of the present invention is applied.

FIG. 10 is an explanatory diagram of a driving waveform of a driving method of the display discharge tube according to the embodiment of the present invention.

FIG. 11 is a block diagram illustrating a schematic configuration of a display device to which a driving method according to an embodiment of the present invention is applied.

FIG. 12 is an explanatory diagram of a driving waveform of a driving method of the display discharge tube according to the embodiment of the present invention.

FIG. 13 is an explanatory diagram of a driving waveform of a driving method of the display discharge tube according to the embodiment of the present invention.

FIG. 14 is an explanatory diagram of driving waveforms in a driving method of the display discharge tube according to the embodiment of the present invention.

FIG. 15 is an explanatory diagram of a driving waveform of a driving method of the display discharge tube according to the embodiment of the present invention.

FIG. 16 is an explanatory diagram of a driving waveform of a driving method of the display discharge tube according to the embodiment of the present invention.

FIG. 17 is an explanatory diagram of a driving waveform of a driving method of the display discharge tube according to the embodiment of the present invention.

FIG. 18 is an explanatory diagram of driving waveforms in a driving method of the display discharge tube according to the embodiment of the present invention.

FIG. 19 is a schematic perspective view of a conventional AC PDP.

FIG. 20 is a schematic cross-sectional view of a conventional AC PDP.

[Explanation of symbols]

1 front glass substrate, 2 back glass substrate, 3 partition walls,
4 partition, 5 display electrode (memory electrode), 5a mother electrode, 5b transparent electrode, 5M1 display electrode, 5M2 display electrode, 6 first address electrode, 7 second address electrode, 8a: transparent dielectric layer, 8b: dielectric layer, 9: protective film (MgO), 10: phosphor, 11: first address electrode,
11a: mother electrode, 11b: transparent electrode, 20: PDP, 2
1 display electrode driver, 22 first address electrode driver IC group, 23a second address electrode driver IC group
23b: second address electrode driver IC group, 24: controller.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 642 G09G 3/20 642L H01J 11/00 H01J 11/00 K 11/02 11/02 B H04N 5/66 101 H04N 5/66 101B (72) Inventor Yuichi Kijima 3300 Hayano, Mobara-shi, Chiba F-term in Display Group, Hitachi, Ltd. (Reference) 5C040 FA01 FA04 GA02 GB03 GC02 GF02 GF03 MA02 MA03 5C058 AA11 BA02 BA05 BA07 BB03 BB13 5C080 AA05 BB05 CC03 DD03 DD07 DD26 DD27 EE17 EE29 EE30 FF09 HH02 HH05 HH07 JJ02 JJ04 JJ06 JJ07 5C094 AA05 AA10 AA22 AA53 BA31 CA19 DA15 DB04 EA04 EA05 EA10 EB10 EC04 FA31

Claims (5)

[Claims] 1. Each pixel (display cell) includes four electrodes, a display electrode pair covered with a dielectric layer and an address electrode pair, and at least one address electrode is a dielectric layer. A method for driving a display discharge tube having a covered four-electrode structure, wherein a main discharge for display is performed between electrodes of the display electrode pair, and then a first address electrode and a second address electrode are driven in accordance with a display image signal. An address discharge is generated between the address electrodes, a wall charge is formed on at least the first address electrode by the address discharge, and the main discharge is continued. One image signal frame is temporally divided into a plurality of sub-frames. The image information of two consecutive sub-frames is compared, the difference between the image information of the two sub-frames is addressed, and the upper wall of the first address electrode is addressed in the previous sub-frame. Charge formation, said A main discharge is continued by shifting a discharge between the first address electrode and the display electrode to a discharge between one of the electrodes and a discharge between the display electrodes. How to drive the tube. 2. Each pixel (display cell) includes a display electrode pair covered with a dielectric layer, and four electrodes including a first address electrode and a second address electrode, and at least one address electrode. A method of driving a display discharge tube having a four-electrode structure in which electrodes are covered with a dielectric layer, wherein a driver for applying a pulse or voltage to the second address electrode is independently installed for each of the RGB display cells, A driving method of a display discharge tube, wherein a driving signal of a different width or voltage is applied to each of the RGB display cells to perform an address discharge between a first address electrode and a second address electrode. 3. Each pixel (display cell) includes a display electrode pair covered with a dielectric layer, and four electrodes including a first address electrode and a second address electrode, and at least one address electrode. A method of driving a display discharge tube having a four-electrode structure in which electrodes are covered with a dielectric layer, wherein one frame is temporally divided into a plurality of sub-frames by the display discharge tube having a four-electrode structure. In the case of performing a grayscale display, a discharge sustaining pulse for maintaining a main discharge is applied between the electrodes of the display electrodes in a sub-frame having an image signal, and between the electrodes of the display electrode in a sub-frame having no image signal. A driving method of a display discharge tube, wherein a sustaining pulse for maintaining a main discharge is not applied. 4. Each pixel (display cell) includes a pair of display electrodes covered with a dielectric layer, and four electrodes including a first address electrode and a second address electrode, and at least one address electrode. A method for driving a display discharge tube having a four-electrode structure in which electrodes are covered with a dielectric layer, wherein a reset discharge for initializing a discharge cell on a screen with the display discharge tube having a four-electrode structure has an image signal. A method for driving a display discharge tube, wherein the method is performed in a frame and not performed in a frame having no image signal. 5. Each pixel (display cell) includes a display electrode pair covered with a dielectric layer, and four electrodes including a first address electrode and a second address electrode, and at least one address electrode. A method for driving a display discharge tube having a four-electrode structure in which electrodes are covered with a dielectric layer, the method comprising applying a wall charge erase pulse to a wall charge formed by a main discharge of the display discharge tube having a four-electrode structure. Set a period to erase,
The display discharge tube according to claim 1, wherein the wall charge erasing pulse includes a pulse train having a voltage lower than a voltage of a pulse for maintaining a main discharge, or a voltage of the wall charge erasing pulse train is a value less than a minimum discharge sustaining voltage. Drive method.