JP2000324490A - Encoded digital signal decoding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decode an encoded digital signal with a high transmission speed by a decoding part with a low processing speed. SOLUTION: The encoded digital signal is supplied from a stream separating part 2 to an encoding unit separating part 3 and separated by encoding unit. Each encoding unit Cij is divided into a plurality of kinds such as the odd- numbered one and the even-numbered one and supplied to a memory control part 4 together with a kind identifying signal Di expressing its kind. A memory area is divided by encoding unit kind in a memory part 5. The memory control part 4 identifies the kind of an encoding unit Cij by the kind identifying signal Di and writes the unit Cij in the memory area corresponding to the kind in the memory part 5. The memory areas of the memory part 5 are read in parallel, the first kind encoding unit F1 is decoded by the decoding signal decoding part 61 and the K-th kind encoding unit FK is decoded by the encoding signal decoding part 6K.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coded digital signal decoding apparatus, and more particularly to a coded digital signal decoding apparatus which can be applied to applications requiring high-speed decoding.

[0002]

2. Description of the Related Art MPEG (Mov) is one of the moving image compression standards.
ing Picture coding Experts Group) standards.
This is based on the ISO (Interna
WG8 (Working Group)
8), or a related compression standard (CCITT
H261).

The MPEG standards include MPEG-1 and M
PEG-2. The MPEG-2 standard classifies performance such as image size by introducing concepts of a profile and a level. At present, the MPEG-1 standard is used for video CDs and the like.
G @ 2 standard MP @ ML (Main Profile at Main Level)
Is used. In the future, MPEG with more expanded performance
-2 standard MP @ HL (Main Profile at High Level) will be used in digital broadcasting and the like.

[0004] At present, various announcements have been made regarding MP @ ML decoding devices. Examples of MP @ ML decoding devices are disclosed in, for example, Japanese Patent Application Laid-Open No.
No. 32-927.

[0005] A conventional standard MP @ ML decoder is as follows.
As shown in FIG. 6, one stream information is selected from a stream supply unit 50 that supplies a multiplexed stream, and a plurality of pieces of stream information 500 and 501 supplied from the stream supply unit 50. Multiplexing / demultiplexing unit 51 for separating the information 502 into various pieces of information; a memory unit 52 for temporarily storing the separated information 502; and one coded video signal for reading and decoding the coded video signal from the memory unit 52 The decoding unit 53 and the decoded video signal 505
D / A converter 55 for converting the encoded audio signal into an analog video signal 507, one encoded audio signal decoding unit 54 for reading and decoding the encoded audio signal from the memory unit 52, and converting the decoded audio signal 506 into an analog audio signal 508. Convert to D
/ A converter 56.

[0006]

Here, the transmission speed of the encoded digital video signal of MP @ ML is 15 Mbit / s.
Second, whereas the transmission speed of the encoded digital video signal of MP @ HL is 80 Mbit / sec.
The decoding device for the P ＠ HL encoded digital video signal is M
The processing speed is required to be about six times or more as compared with the decoding apparatus for the P ＠ ML encoded digital video signal.

According to this, in the conventional coded digital signal decoding device, in order to perform such high-speed processing, the decoding processing speed of the decoding unit of the coded video signal decoding device is simply reduced by about It is necessary to increase it six times or more. However, in order to increase the processing capacity in this way, it is necessary to greatly increase the internal operating frequency of the decoding unit.
Accordingly, the configuration circuit becomes complicated and power consumption increases.

SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem, suppress the complexity of the constituent circuits and suppress an increase in power consumption, and to decode an encoded digital video signal at a high transmission rate. A decoding device is provided.

[0009]

In order to achieve the above-mentioned object, the present invention provides a stream supply for supplying N (N is a positive integer) streams multiplexed by at least one multiplexing method. Unit and a specified stream from the stream supplied from the stream supply unit,
A stream separation unit that separates the coded digital signal from the separated stream and outputs the coded digital signal in response to the stream request signal; and outputs the coded digital signal from the stream separation unit for each coding unit. A coding unit separating unit that separates and classifies the separated coding units into n types (where n is a positive integer), a memory unit in which a different memory area is set for each type of the coding units, The type of the coding unit from the coding unit separation unit is identified, and the coding unit is written into the memory area of the memory unit corresponding to the type, and K types (where K is a positive integer and ,
K ≦ n) are provided for each of the memory control units for reading the coding units in parallel from the K memory areas in which the coding units are written, and for each type of the coding units read from the memory unit. A K number of coded signal decoding units for decoding a corresponding type of coded unit read from the memory unit, and a decoding unit obtained by decoding the coded unit with the K number of coded signal decoding units in a predetermined order. , And a decoded signal output unit for outputting as a decoded digital signal.

With this configuration, the coding units of the same coded digital signal are classified into a plurality of types and are decoded separately and in parallel for each of these types. Transmission speed of the coded digital signal to be transmitted, the internal frequency of the decoding unit can be lowered, and the complexity of the circuit configuration and increase in power consumption can be suppressed. Even when the unit is used, the processing time of each coding unit is shortened, so that even in this case, power consumption can be reduced.

In order to achieve the above object, the present invention also provides a stream supply unit for supplying N types (where N is a positive integer) of streams multiplexed by at least one type of multiplexing method, From the stream supplied from the supply unit, the specified L types (where L is a positive integer, L ≦ N) of the streams are separated, and further, the coded digital signal is separated from the separated streams. hand,
A stream separation unit that outputs the coded digital signal separated from the stream of the type requested by the stream request signal for a unit period, and separates and separates the coded digital signal from the stream separation unit for each coding unit. A coding unit separation unit for classifying the coding units into n types (where n is a positive integer) and L stream memory areas for each type of stream separated by the stream separation unit are set. And a memory unit in which a coding unit memory area is set for each type of coding unit separated by the coding unit separation unit for each stream memory area, and the coding unit is supplied from the coding unit separation unit. Each time, the type of the encoding unit and the type of the stream to which the encoding unit belongs are identified, and the identification result is written to the memory area of the memory unit corresponding to the identification result. A memory control unit that reads coding units in parallel from K memory units (where K ≦ n) in each stream memory unit of the memory unit, and a coding unit that is read from the memory unit (L × K) coded signal decoding units, which are provided for each type of stream and coding unit, and decode the corresponding type of coding unit read from the memory unit, respectively. K)
And a decoded signal output unit that takes in in a predetermined order decoding units obtained by decoding the coding units in the coded signal decoding units and outputs the decoded units in parallel as L types of decoded digital signals.

According to this configuration, the same effects as those of the above-described invention can be obtained, and the decoding of a plurality of streams can be performed in a similar manner and in parallel.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an encoded digital signal decoding apparatus according to the present invention,
1 is a stream supply unit, 2 is a stream separation unit, 2a is a memory, 3 is a coding unit separation unit, 4 is a memory control unit, 5
The memory unit, 6 _1, ..., is 6 _k coded signal decoding section, 7 is an output unit.

This embodiment is an MPE used for digital broadcasting scheduled to start broadcasting in Japan in 2000.
It is assumed that the apparatus is a decoding apparatus for a digital video signal encoded by MP @ HL of the G-2 standard, and that a plurality of streams encoded by MP @ HL of the MPEG-2 standard are decoded and output to the outside.

In FIG. 1, a stream supply unit 1 provides N types (for example, transponders such as communication satellites and receiver antennas) multiplexed by at least one type of multiplexing system (where N is 2 stream a ₁ over an integer), ......, a _N (e.g., transport stream (TS: transport stream) and a program stream (P
S: Program Stream), for example, streams constituting N different types of channels)
Supplied to

In the stream separating section 2, N types of streams A ₁ ,..., A _N supplied from the stream supplying section 1 are provided.
From the desired stream A _i (where i = 1,
,..., N) are further selected, and the stream B _i of the encoded digital signal is extracted from the selected stream A _i.
(For example, a video elementary stream (Video ES: Video Elementary) encoded by the MPEG-2 standard
Stream)) is separated and temporarily written to the memory 2a,
The data is read out according to the stream request signal S from the memory control unit 4 and supplied to the coding unit separation unit 3.

In the coding unit separation unit 3, the stream B _i of the coded digital signal supplied from the stream separation unit 2 has n types (where n is a positive integer) of coding units (for example, MPEG-2 standard). (A picture header layer in the Video ES coded in the above, a slice layer of an even-numbered line, a slice layer of an odd-numbered line in the input order, etc.). The coding unit C _ij is a coding unit type identification signal indicating the type of the coding unit C _ij at that time (ie, the above-mentioned picture header layer, even-line slice layer, odd-line slice layer, etc.). with D _j, it is supplied to the memory control unit 4.

The memory control unit 4 has a memory write control signal W
_C , the coding unit C from the coding unit separation unit 3
_ij is written as a write encoding unit E _ij in the memory unit 5. In this case, the type of the supplied encoding unit C _ij is determined with reference to the encoding unit type identification signal D _j. By controlling the write delay signal W _A in accordance with the result of the determination (accordingly, the type of the encoding unit C _ij ), the write encoding unit E _ij is divided into its types and stored in the memory unit 5. Write. Here, the type of the coding unit C _ij is K
It is assumed that there are types (hence, j = 1, 2,..., K), and the write encoding unit E _ij is divided into K sequences and written into the memory unit 5.

The memory control unit 4 reads out the coding units E ₁ ,... EK of the respective _streams in parallel from the memory unit 5 in response to the memory read control signal R _C and the read address signal R _A. read coding units E ₁ sequence to the encoded signal decoding unit ₆₁ of the first series, ..., read coding unit E _K of the K-series
Are supplied to the K-th sequence coded signal decoding unit 6 _K to be decoded simultaneously. In this case, the memory controller 4, the coded signal decoding section _61, ..., the coding unit transfer control information G ₁ from 6 _K, ..., in response to the transfer request by the G _K, there is the request The sequence coding unit F _i for the j-th sequence encoded signal decoding unit 6 _j (where j = 1, 2,..., K) is read from the memory unit 5, and the j-th sequence To the encoded signal decoding unit _6j .

[0020] Here, the amount of information of the coding unit of the coded digital signal B _i that is supplied to the coding unit separation unit 3 is not constant, thus, it is read out and the coding unit E _ij is written in the memory unit 5 The data amount of the coding unit _Fj differs individually. Therefore, the decoding processing time at the same coded signal decoding unit 6 _j also to different for each coding unit F _j, coded signal decoding section _61, ..., in each 6 _K, decoding one coded unit Unlike the time required to process these coded signal decoding unit 6 _1, ..., 6 _K coding unit transfer control information G ₁ is the memory control unit 4, ..., coding units F ₁ by G _K, ... …,
The timing for requesting F _K will also be different. In short, the coded signal decoding unit 6 _1, ......, 6 _K, the following coding unit F _1, ......, and is ready captures F _K, the encoding unit transfer control information G _1, ......, G and outputs a _K, next coding unit to the memory control unit 4 F _1, ......, to request F _K.

A request for the next coding unit F _j is received from the _j-th coded signal decoding unit 6 _{j with the} coding unit transfer control information G _j , and in response to this, the memory control unit 4 Upon reading out the coding unit F _j of the j-th sequence, the memory control unit 4 sends the read coding unit F _j to the coding signal decoding unit 6 _j of the j-th sequence. The unit transfer control information G _j is sent, and then the read coding unit F _i is transferred. Therefore, this j-th
Coded signal decoding unit 6 _j series receives the coded unit transfer control information G _j, and ready incorporation the coding unit F _j, a coding unit F _j transferred from the memory controller 4 held in takes in once built coding unit for memory, with one complete decoding of previous coding unit F _j, starts decoding processing reads the coding unit F _j of the coding unit memory I do.

The respective coded signal decoding section _61, ..., the 6 _K, the above operation is coding units F _1, ..., are performed for each F _K.

Each of the coded signal decoding units 6 ₁ ,..., 6 _K is provided with a decoding unit memory, and the decoded coding unit (hereinafter referred to as a decoding unit) is stored in the decoding unit memory. Is temporarily held. When the decoded signal transfer control information I _j is output from the decoded signal output unit 7, the coded signal decoding unit 6 _{j reads the} decoding unit H _j from the decoding unit memory and sends it to the decoded signal output unit 7. Will be transferred.

The coded signal decoding units 6 ₁ ,.
... In 6 _K, the encoding unit F _1, ......, but in which F _K is decoded is supplied, in the case of the MPEG-2 standard, these coding units F _1, ......, F _K slice Then, the encoded signal is supplied to the encoded signal decoding units 6 ₁ ,..., 6 _K in slice units, and it goes without saying that the actual decoding process is performed in macro block units. In this embodiment including this, the coded signal decoding units 6 ₁ ,
..., 6 _K are decoded in coding units.

[0025] Here, as described above, K types of coding units F _1, ......, coded signal decoding unit 6 ₁ F _K, ......, but are decoding process in parallel by 6 _K, decoding Signal output unit 7
.., 6 _K correspond to the order of the coding units C _ij transferred from the coding unit separation unit 3 to the memory control unit 4 by the decoding units obtained by decoding in the coded signal decoding units 6 _{1 ,.} in order to the order, the coded signal decoding unit 6 _1, ..., decryption units I ₁ from 6 _K, ..., decoded signal transfer control information I ₁ the reading order of I _k, the output of the ...... I _K Determined by timing. Thus, when the coded signal decoding unit 6 _j receives the decoded signal transfer control information I _j from the decoded signal output unit 7, the coded signal decoding unit 6 _j starts reading the decoding unit H _j from the decoding unit memory, and the decoding unit H _j
And transfers the decoded unit H _j in the decoded signal output section 7 outputs the decoded signal transfer control information I _j indicating the transfer. Decoded signal output unit 7 receives the decoded signal transfer control information I _j from the coded signal decoding unit 6 _j, outputs as a decoded signal J captures decoding unit H _j from the coded signal decoding unit 6 _j Immediately before the output of the decoding unit _Hj ends, the next decoding unit _Hp (where p = 1, 2,...)
, J−1, j + 1,..., K), and sends the decoded signal transfer control information I _p to the encoded signal decoding unit 6 _p . In this way, from the decoded signal output unit 7, the encoding unit separation unit 3
, A decoded signal J consisting of a series of decoding units H _{j in the} same order as the coding units C _ij is obtained. The decoded signal J is supplied to a video / audio device or a recording device (not shown).

[0026] Incidentally, the memory provided in such decoded signal output unit 7, a coded signal decoding unit 6 _1, ..., writes the decoding unit taken from 6 _K in the order successively to the memory,
By successively reading this, after taking in the decoding unit H _j from a certain coded signal decoding unit 6 _j , a time interval is taken between taking in the next decoding unit H _p from another coded signal decoding unit 6 _p. Even if there is, it is possible to read out sequential decoding units from this memory by continuously arranging them.

The memory control unit 4 also monitors the state of the memory unit 5, and sends a stream request signal S to the stream separation unit 2 when the coding unit can be written in the memory unit 5. . The stream separation unit 2 receives the stream request signal S while the memory 2
The stream is read from a and transferred to the coding unit separation unit 3.

FIG. 2 is a block diagram showing a specific example of the coding unit separation unit 3 in FIG. 1. 3a is a header detection unit, 3b is a coding unit type identification signal generation unit, and FIG.
The same reference numerals are given to the portions corresponding to and the duplicate description will be omitted.

The data structure of the MPEG-2 standard includes a sequence layer, a GOP (Group of picture) layer, a picture layer,
A six-layer structure including a slice layer, a macroblock layer, and a block layer is adopted, and a header is provided at the head of each of the sequence layer, the GOP layer, the picture layer, and the slice layer. The sequence header indicates the size, aspect ratio, bit rate, designation of profile and level, presence / absence of B picture, etc.
The header indicates the time from the beginning of the sequence, and the picture header indicates the display order, picture type,
The slice header indicates a search range of a moving vector, and the slice header indicates a vertical position of a slice in a picture. In this embodiment, this slice is used as a coding unit.

In FIG. 2, the coding unit separating section 3 comprises a header detecting section 3a and a coding unit type identification signal generating section 3b. Header detector 3a analyzes the stream B _i of the coded digital signal supplied from the stream separating unit 2, a sequence header and GOP header, picture header, and so on slice header, detects a header for each encoding unit I do. Here, together with the slice, the sequence header, the GOP header, and the picture header are also used as coding units.
The type of these coding units is determined from the information content of each header. Here, a plurality of types are set for the slice, and the type of the input slice is also determined by the slice header. As the types of slices, for example, odd-numbered slices and even-numbered slices in a picture are set as different types of coding units.
When the header detection unit 3a detects the header for each coding unit and determines the type of the coding unit, the header detection signal DH indicating that the header has been detected and the header type value V
H and outputs the coding unit having the detected header to the memory control unit 4 as a coding unit C _ij .

The coding unit type identification signal generator 3b determines the type of the coding unit _Cij supplied to the memory controller 4 at this time from the header detection signal DH supplied from the header detector 3a and the header type value VH. _Is generated and supplied to the memory control unit 4.

FIG. 3 is a block diagram showing a specific example of the memory control unit 4 and the memory unit 5 in FIG. 1, wherein 4a is a write memory area selector, 4b is a read memory area selector,
Reference numeral 4c denotes a memory area information table unit, and 4d denotes a memory management unit. Parts corresponding to those in FIG.

In the figure, a memory section 5 is provided with n independent memory areas of memory areas 1, 2, 3, 4,..., N. Are associated with each other. That is, the same in the memory area, the same type of coding units represented by the same coding unit type identification signal D _j is written. For example, a sequence header is assigned to the memory area 1, a GOP header is assigned to the memory area 2, a picture header is assigned to the memory area 3, and different types of slices are assigned to the memory areas 4,.

The memory controller 4 includes a write memory area selector 4a for controlling the writing of the memory section 5, a read memory area selector 4b for controlling the reading of the memory section 5, and a table representing the storage state of the memory section 5. It comprises a stored memory area information table section 4c and a memory management section 4d that manages the state of the memory section 5 based on the storage table of the memory area information table section 4c.

When the coding unit C _ij and the coding unit type identification signal D _j are supplied from the coding unit separation unit 3, the write memory area selection unit 4 a
the memory area of the memory unit 5 corresponding to the coding unit type identification signal D _j from the c table m (where, m = 1,2, ...
, N) to generate a write address signal W _A and a memory write control signal W _C for designating the write area. Based on these, the coding unit C _ij is stored in the memory unit. 5
In the corresponding memory area m. At the same time, the write memory area selection section 4a corrects the table of the memory area information table section 4c so that the area of the memory area m where the coding unit _Cij is written is set as a non-writable area. .

The read memory area selecting unit 4b, coded signal decoding unit 6 _1, ..., one of 6 _K, i.e., the coding unit transfer control signal G _j from the coded signal decoding unit 6 _j The coding unit F _j is read from the memory unit 5 based on the coding unit transfer control signal G _j, and the coded signal decoding unit 6 _j is read from the memory area information table unit 4c based on the coding unit transfer control signal G _j.
, A memory area m ′ of the memory unit 5 where the coding unit F _j to be read is stored (where m ′ = 1, 2,...,
n), a read address signal _RA for designating the read area and a memory write control signal _RC are generated, and the coding unit Fj is _extracted from the memory area m 'based on these. It is read and transferred to the encoded signal decoding unit _6j . Also, this time, the read memory area selecting unit 4b, a region where coding unit F _j is read in the memory area m 'to a writable area, modifying the table in the memory area information table section 4c I do.

[0037] Thus, in the memory unit 5, the same type of the coding unit is to be stored in the same memory region, coded signal decoding unit 6 _1, ......, 6 _K is each independently The decoding operation of the same type of encoding unit is performed, and accordingly, the contents are corrected in the memory area information table section 4c, and the following memory areas 1 and 2 in the memory section 5 are always updated.
,..., N can be known.

The memory management section 4d manages the state of the memory section based on the information in the memory area information table section 4c, and determines, for example, whether writing in the memory section 5 is possible in picture units or slice units. , When writing is possible, generates a stream request signal S and sends it to the stream separation unit 2.

The memory area information table section 4c also stores information for determining the read timing of each header stored in a predetermined memory area of the memory section 5 (in the above case, the memory areas 1, 2, 3). When the last slice of one sequence layer is read, a sequence header is read from the memory area 1 and transferred to each of the coded signal decoding units 6 ₁ ,..., 6 _K. When it is determined from the header that the profile and level are MP @ HL and the bit rate is determined, the processing speed is set according to the determination result. This MP @ H
L has a very high transmission rate compared to the conventional generally used MP @ ML. However, the decoding of the coding unit is not performed by one coding and decoding unit, but the coding unit of the slice is set by K. Coded signal decoding units 6 ₁ ,
.., 6 _K in parallel, the processing speed of each of the encoded signal decoding units 6 ₁ ,..., 6 _K can be made approximately 1 / K times the transmission speed of MP @ HL. these coded signal decoding section _61, ..., as the 6 _K, the input stream is M
Even if it complies with P ＠ HL, it is possible to suppress the complexity of the circuit configuration and increase in power consumption, and furthermore,
A low-speed encoded signal decoding unit used in the conventional MP @ ML can also be used.

Further, following the sequence header forwarding, GOP header is read from the memory area 2, then the picture header from the memory area 3 is read and coded signal decoding unit 6 _1, ..., a 6 _K Is done. The GOP header is stored in the sequence each time the coding unit of the last slice of the GOP is read from the memory unit 5, and the picture header is stored in the GOP each time the coding unit of the last slice of the picture is read. Is read. When the picture header is supplied, the coded signal decoding units 6 ₁ ,..., 6 _K are set to perform an I, P or B picture decoding operation according to the information content.

FIG. 4 is a diagram showing a method of storing coding units and a method of reading coding units in the memory unit 5 in FIG.
This is for the coding unit of the slice,
The types will be described as two types of odd-numbered coding units and even-numbered coding units in the order of input.

FIG. 4 (a) shows the input order of such coding units in a certain picture, where odd-numbered coding units 1, 3, 5,... The even-numbered coding units 2, 4, 6,... Are the type 1 coding units.

FIG. 4B shows a method of storing the coding unit in the memory unit 5. The memory unit 5 includes areas 1, 2,
.. Are divided into a plurality of areas, and coding units are written in this order. Hereinafter, assuming that coding units are input as shown in FIG. 4A, a method of writing these coding units will be described.

First, when a coding unit 1 of type 0 is input, the coding unit 1 is written in the area 1 of the memory unit 5. Therefore, this area 1 is determined as an area in which a coding unit of type 0 is written. Next, when a coding unit 2 of type 1 is input, it is written to the next area 2.
Therefore, this area 2 is determined as an area in which a type 1 coding unit is written. Next, when the coding unit 3 of the type 0 is input, it is written in the area 1 following the coding unit 1, and when the next coding unit 4 of the type 1 is input, the coding unit 3 is encoded. Data is written following unit 2.

Similarly, the coding unit 5 is changed to the area 1
First, when the coding unit 6 is written in the area 2 and then the coding unit 7 is input, this is also written in the area 1. However, a part of the coding unit 7 is written in the area 1. Therefore, the rest is written to the free top area 3. Therefore, this area 3 is determined as an area in which a coding unit of type 0 is written. Similarly, when a coding unit 8 of type 1 is input, a part of the coding unit 8 cannot be written to the area 2, and the rest is written to the free top area 4. Is determined in the area where the coding unit is written.

Hereinafter, the coding unit 9 is written in the area 3, the coding unit 10 is written in the area 4, and the coding unit 11 is written in the area 3. A part of the next coding unit 12 is written in the area 4. If not, the rest is similarly written to the first free area 5, and this area 5 is determined as the area where the type 1 coding unit is written.

In this way, the coding units are written in different areas for each type. However, since all types of coding units are written in order from the top area, the memory is previously stored for each type. The memory unit 5 can be used without waste as compared with the case where the writing area of the unit 5 is determined.

When the coding unit written as shown in FIG. 4B is read, the coding unit of type 0 and the coding unit of type 1 are read independently. That is, reading of the coding unit 1 of the area 1 and the coding unit 2 of the area 2 simultaneously starts, and the coding units 1, 3, 5,... reads out the ... respectively the write order, the coding unit 1, 3, 5, ... are decoded by the encoding signal decoding unit _61, a coding unit 2, 4, 6, ... are coded signal decoding decoding in parts 6 _2.

[0049] The reading may be read at the same rate as the coding unit C _ij of input, also coded signal decoding section _61, ..., at a transmission speed matching the processing speed of 6 _K You may make it read.

In the above description, there are two types of coding units. However, in general, every n ′ (where n ′ is an integer of 1 or more) coding units are of the same type.
The same applies to (n ′ + 1) types of coding units. In this case, (n ′ + 1) coded signal decoding units are also used, and their decoding processing speed is 1 / (n ′ + 1) times the transmission speed of the input decoding unit C _ij .

FIG. 5 is a block diagram showing another embodiment of the coded digital signal decoding apparatus according to the present invention. In FIG. 5, portions corresponding to those in FIG.

This embodiment has basically the same configuration as the embodiment shown in FIG. 1, but is capable of decoding a plurality of streams in parallel. .

In the figure, N types (where N is a positive integer) of streams A ₁ ,..., A _N multiplexed from the stream supply unit 1 to the stream separation unit 20 by at least one multiplexing method. Is supplied. Stream separation unit 2 '
, These N types of streams A _1, ......, a desired Q type from A _N (where, Q is a positive integer, Q ≦ N) to separate the stream (e.g., the Q-channel stream) of In addition, the coded signal B is separated for each separated stream, and each is temporarily stored in a built-in memory (not shown), read out from this memory in response to the stream request signal S from the memory control unit 4 ', and output. , A stream type identification signal L indicating the type of stream to be output at this time
Is also output.

In this case, the stream is read from the built-in memory of the stream separation unit 2 'in, for example, a picture unit and the read speed is set to Q times the write speed.
It is necessary to read Q types of streams. The stream to be read is determined by the stream request signal S, and therefore, the encoded signal B output from the stream separation unit 2 '
Is a coded signal of one of the Q types of streams, and the stream type identification signal L indicates the type of the stream of the coded signal B being output at this time.

The coding unit separation unit 3 ′ takes in the coded signal B output from the stream separation unit 2 ′ and the stream type identification signal L, and converts the coded signal B supplied from the stream separation unit 2 into Similarly to the coding unit separation unit 3 shown in FIG. 1, the coding unit C is separated into n types of coding units and supplied to the memory unit 4 '. At the same time, the coding unit separation unit 3 ′ generates a coding unit type identification signal D representing the type of the coding unit C output to the memory control unit 4 ′ and the type of the stream based on the captured stream type identification signal L. And the memory control unit 4 ′ together with the coding unit C.
To supply.

The memory control unit 4 'determines the type of the coding unit C supplied from the coding unit separating unit 3' from the coding unit type identification signal D, and according to the determination result, determines the coding unit C Write control to the memory unit 5 '. The memory control unit 4 'also has the same configuration as the memory control unit 4 shown in FIG. 3, but in this memory control unit 4', the write memory area selection unit 4a 'the kinds of streams belonging coding unit C is supplied identified from, to be specified with the stream memory area to be written this coding unit C with the write address signal W _a, also the memory area information table section 4c , A table indicating the storage state of the coding unit memory areas of all stream memory areas.

Here, in the memory section 5 ', a memory area is divided for each of the Q types of streams, and a memory area set for each stream (hereinafter referred to as a stream memory area) is shown in FIG. As shown, writing is performed so as to be divided for each coding unit (a memory area in which the same type of coding unit is recorded is hereinafter referred to as a coding unit memory area. Therefore, each stream area is It will be divided by the coding unit memory area).

When the coding unit C and the coding unit type identification signal D corresponding to the coding unit C are supplied, the memory control unit 4 'determines which stream the coding unit C is based on from the coding unit type identification signal D. , A memory write control signal W _C is generated, and a write address in a corresponding coding unit memory area in a corresponding stream memory area is determined according to a result of the determination. generating a write address signal W _a is specified. As a result, the coding unit C is written as the coding unit E at a predetermined address of the corresponding coding unit memory area in the corresponding stream memory area of the memory unit 5 ′.

The reading of all the coding unit memory areas of all the stream memory areas of the memory section 5 'is performed in parallel by the memory control section 4'. These reads also
As in the embodiment shown in FIG. 1, the encoded signal decoding units 6 ₁ ,
.., Coded signal transfer control information G ₁ from 6 _K ′,.
This is performed according to G _K '.

Here, the K ′ encoded signal decoding units 6 ₁ ,
.., 6 _K ′ correspond to the coding unit memory areas for storing the coding units of the slices in the respective stream memory areas in the memory unit 5 ′. If the conversion unit is K types, K '
= Q × K. These coded signal decoding units 6 ₁ ,.
6 _K ′ are coded signal decoding units 6 ₁ ,.
..., as with 6 _K, decodes the encoded unit F corresponding slices are read from the coding unit memory area in the stream memory area of the memory unit 5 '. The other operations of the header are the same as those of the embodiment shown in FIG.

As described above, in the Q types of streams separated by the stream separation unit 2 ', their coding units F are decoded in parallel by the coded signal decoding units 6 ₁ ,..., 6 _K '. , JQ, the decoded signals J ₁ , J ₂ ,..., J _Q of the Q types of streams are obtained in parallel. Moreover, as with the embodiment shown in FIG. 1, coded signal decoding unit 6 _1, ..., stream A ₁ inputted the processing speed of 6 _K ', ..., approximately 1 / K of the transmission speed of A _N Even if the input stream conforms to MP @ HL, the coded signal decoding units 6 ₁ ,.
The complexity of the circuit configuration of 6 _K ′ and the increase in power consumption can be suppressed, and the coded signal decoding unit used in the conventional MP @ ML can also be used.

In the above embodiment, when a decoding unit capable of high-speed processing is used, the processing time of the coding unit can be greatly reduced, and the power consumption is reduced accordingly. Becomes possible.

[0063]

As described above, according to the present invention,
Since the coding units forming the stream of the coded digital signal are divided into a plurality of types and the respective types of coding units are decoded in parallel, the processing speed is lower than the transmission speed of the input stream. Since these coding units can be decoded, there is no need to increase the internal frequency of the decoding unit, it is possible to suppress the complexity of the circuit configuration and increase in power consumption, and a decoding unit capable of high-speed processing is provided. Even when used, the processing time can be greatly reduced, and the power consumption can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an encoded digital signal decoding device according to the present invention.

FIG. 2 is a block diagram showing a specific example of a coding unit separation unit in FIG.

FIG. 3 is a block diagram showing a specific example of a memory control unit and a memory unit in FIG. 1;

FIG. 4 is a diagram for explaining a specific example of a writing method and a reading method of a coding unit in a memory unit in FIG. 1;

FIG. 5 is a block diagram showing another embodiment of the coded digital signal decoding device according to the present invention.

FIG. 6 is a block diagram showing a conventional decoding device for a digital signal encoded by MP @ ML of the MPEG-2 standard.

[Explanation of symbols]

Reference Signs List 1 stream supply unit 2, 2 'stream separation unit 2a memory 3, 3' coding unit separation unit 3a header detection unit 3b coding unit type identification signal generation unit 4, 4 'memory control unit 4a write memory area selection unit 4b reading memory area selecting section 4c memory area information table unit 4d memory management unit 5, 5 'memory portion _{6 1 ~6 K, 6 1 ~6} K' coded signal decoding unit 7, 7 'decoded signal output unit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Koichi Terui 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Digital Media Development Division, Hitachi, Ltd. Address: Hitachi, Ltd. Digital Media Development Division (72) Inventor: Satoshi Takashimizu 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term: Hitachi Digital Media Development Division, F5 Term (reference) RB01 RB09 RB10 RB16 SS01 UA05 UA36 UA38 5C078 CA31 CA35 DA00 DA02 9A001 EE04 HH27 HH30 JJ13 JJ18 JJ19 KK56

Claims (6)

[Claims] An encoded digital signal decoding apparatus for decoding an encoded digital signal for each encoding unit, comprising: N (where N is a positive integer) streams multiplexed by at least one multiplexing method. A stream supply unit for supplying a stream request, separating a specified stream from the stream supplied from the stream supply unit, separating an encoded digital signal from the separated stream, and converting the encoded digital signal into a stream request signal. A stream separating unit that outputs the coded digital signal from the stream separating unit for each coding unit, and classifies the separated coding units into n types (where n is a positive integer). A coding unit separating unit, a memory unit in which a different memory area is set for each type of the coding unit, and the coding from the coding unit separating unit The type of the unit is identified, the coding unit is written in the memory area of the memory unit corresponding to the type, and K types (where K is a positive integer and K ≦ n) are written. A memory control unit that reads the coding units from the K memory areas in parallel, and a code of a corresponding type that is provided for each type of coding unit that is read from the memory unit and that is read from the memory unit. K decoding units for decoding a coding unit, and decoding in which decoding units obtained by decoding coding units by the K coding signal decoding units are taken in a predetermined order and output as a decoded digital signal. A coded digital signal decoding device characterized by having a signal output unit. 2. The coding unit separation unit according to claim 1, wherein the coding unit separation unit detects, from the coded digital signal, header information including a header type value indicating the type of each coding unit,
A header detection unit that outputs a header detection signal indicating that the header information has been detected and the header type value; and a coding unit type indicating the type of the coding unit from the header detection signal and the header type value. An encoding unit identification signal generation unit that generates an identification signal, wherein the memory control unit identifies the type of the encoding unit based on an encoding unit type identification signal. Decoding device. 3. The memory unit according to claim 1, wherein the memory unit has n memory areas, and the memory control unit identifies a type of the coding unit supplied from the coding unit separation unit. A write memory area selector for controlling to write the coding unit into a memory area of the memory section corresponding to the identification result among the n memory areas; and a code from the coded signal decoder. Reading a coding unit from a memory area of the memory unit specified by the coding unit transfer control signal in accordance with the coding unit transfer control signal, and supplying the read coding unit transfer control signal to the coded signal decoding unit that has generated the coding unit transfer control signal A memory area selection unit, and memory area information indicating a storage state of an encoding unit of each memory area in the memory unit is stored. A memory area information table for correcting the memory area information in accordance with writing of a coding unit by an output memory area selector; and encoding in the memory based on the memory area information stored in the memory area information table. An encoded digital signal decoding apparatus, comprising: a memory management unit that manages a storage state of a unit and outputs the stream request signal to the stream separation unit according to the storage state. 4. An encoded digital signal decoding apparatus for decoding an encoded digital signal for each encoding unit, comprising: N (where N is a positive integer) streams multiplexed by at least one multiplexing method. And a stream supply unit for supplying L from the stream supplied from the stream supply unit (where L is a positive integer and L ≦ N)
A stream separating unit that separates a coded digital signal from the separated stream and outputs the coded digital signal separated from a stream of the type required by the stream request signal for a unit period. A coding unit separation unit that separates the coded digital signal from the stream separation unit into coding units, and classifies the separated coding units into n types (where n is a positive integer); L stream memory areas are set for each type of stream separated by the stream separation unit, and coding unit memories for each type of coding unit separated by the coding unit separation unit for each stream memory area A memory unit in which an area is set, and each time the coding unit is supplied from the coding unit separation unit, the type of the coding unit and the coding unit belong. The type of the stream is identified and written to the memory area of the memory unit corresponding to the identification result, and K (where K ≦ n) K encoding unit memories in each stream memory unit of the memory unit A memory control unit that reads the coding units in parallel from the memory unit; and a memory control unit that is provided for each type of a stream of the coding unit read from the memory unit and a type of the coding unit. (L × K) coded signal decoding units for decoding the various types of coding units, and a decoding unit obtained by decoding the coding unit with the (L × K) coded signal decoding units. A decoded signal output unit for taking in order and outputting in parallel as L types of decoded digital signals. 5. The stream separation unit according to claim 4, wherein the stream separation unit generates and outputs a stream type identification signal indicating a type of the stream with respect to the coded digital signal to be output. Detecting, from the encoded digital signal supplied from the stream separation unit, header information including a header type value indicating the type of each encoding unit, a header detection signal indicating that the header information has been detected, and the header type value; From the header detection signal, the header type value, and the stream type identification signal output from the stream separation unit, and the encoding unit indicates the type of the encoding unit and the type of the stream. A coding unit identification signal generation unit for generating a unit type identification signal, wherein the memory control unit is configured to generate a unit type identification signal based on the coding unit type identification signal. There are coded digital signal decoding apparatus characterized by identifying the type of stream type bed of the coding unit of the coding unit belongs. 6. The memory control unit according to claim 4, wherein the memory control unit identifies a type of the encoding unit and a type of stream supplied from the encoding unit separation unit, and A write memory area selection unit that performs control of writing the coding unit in the coding unit memory area corresponding to the identification result of the stream memory area corresponding to the identification result; and Reading a coding unit from the coding unit memory area in the stream memory area in the memory unit specified by the coding unit transfer control signal according to the coding unit transfer control signal, A read-out memory area selection unit for supplying the coded signal decoding unit that has generated the error, and a storage state of a coding unit in each coding unit memory area in the memory unit. A memory area information table for storing the memory area information to be written and correcting the memory area information according to the writing of the coding unit by the writing memory area selecting unit and the writing of the coding unit by the reading memory area selecting unit; A memory that manages a storage state of a coding unit in the memory unit according to the memory area information stored in the memory area information table unit, and outputs the stream request signal to the stream separation unit according to the storage state; An encoded digital signal decoding device comprising a management unit.