JP2000323678A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JP2000323678A
JP2000323678A JP11132616A JP13261699A JP2000323678A JP 2000323678 A JP2000323678 A JP 2000323678A JP 11132616 A JP11132616 A JP 11132616A JP 13261699 A JP13261699 A JP 13261699A JP 2000323678 A JP2000323678 A JP 2000323678A
Authority
JP
Japan
Prior art keywords
insulating film
film
metal oxide
upper electrode
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11132616A
Other languages
Japanese (ja)
Inventor
Kazuhiko Yamamoto
山本  和彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP11132616A priority Critical patent/JP2000323678A/en
Publication of JP2000323678A publication Critical patent/JP2000323678A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To form a capacitor device whole insulating film of a metal oxide film is covered with an upper electrode formed of a metal nitride film by simplifying the manufacturing process, improving the accuracy of working and preventing degradation of device characteristics. SOLUTION: An insulating film 2 in which a hole as upper electrode forming region of a capacitor device is formed on a semiconductor substrate 1, and the upper electrode 3 of the capacitor device is formed in the opening of the insulating film 2. A material gas of organic metal base is intermittently supplied to the surface of the semiconductor substrate 1 for selectively depositing a insulating film 4 of metal oxide film only on the surface of the lower electrode 3. At the time of deposition, the insulating film 4 is heat treated in an oxide atmosphere. By heat treatment, the insulating film 4 changes is conductive property to its original insulating property. A capacitor device is obtained by forming an upper electrode 5 of metal nitride film. Since the insulating film 4 is selectively deposited only on the surface of the lower electrode 3, manufacturing process can be simplified and the accuracy of working can be improved.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置の製造
方法に関するものであり、詳しくは、ダイナミックラン
ダムアクセスメモリー(以下、DRAMと記す)の容量
素子の製造方法に係わり、更に詳しくは、金属酸化物高
誘電体膜を用いたDRAMの製造方法に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a capacitive element of a dynamic random access memory (hereinafter referred to as DRAM). The present invention relates to a method for manufacturing a DRAM using a high dielectric constant film.

【0002】[0002]

【従来の技術】DRAMの分野では、微細化によるチッ
プ面積の縮小と記録密度の大容量化が要求されている。
近年、微細化の進行とともにDRAMの電荷蓄積部の占
有する面積が縮小され、DRAMの動作に必要な電荷蓄
積量を確保することが非常に困難になりつつある。この
ようなキャパシタ容量の不足対策として、従来、容量絶
縁膜材料として用いられてきたシリコン酸化膜やシリコ
ン窒化膜よりも比誘電率の高い金属酸化物、例えば酸化
タンタル、酸化バリウム・ストロンチウム・チタン化合
物などで置き換える試みがなされている。これにより同
面積でより大きな電荷の蓄積が可能となり、今後のDR
AMキャパシタはさらに微細化が可能となる。
2. Description of the Related Art In the field of DRAM, there is a demand for a reduction in chip area and an increase in recording density due to miniaturization.
In recent years, as the miniaturization progresses, the area occupied by the charge storage portion of the DRAM has been reduced, and it has become extremely difficult to secure the amount of charge storage required for the operation of the DRAM. As a countermeasure against such a shortage of the capacitance of the capacitor, a metal oxide having a higher relative dielectric constant than a silicon oxide film or a silicon nitride film conventionally used as a material for a capacitor insulating film, for example, tantalum oxide, barium oxide / strontium / titanium compound Attempts have been made to replace them. This makes it possible to store a larger amount of electric charge in the same area,
The AM capacitor can be further miniaturized.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、金属酸
化膜は、例えば水素やシラン(水素化シリコン)などの
還元性ガスに曝されると容易に還元されて金属過剰組成
となり、絶縁膜でありながら電気伝導性を示し、容量素
子においては電流リークにより電荷蓄積ができないとい
う問題が生じてしまう。この容量素子形成後における還
元性ガスは、例えば層間絶縁膜堆積に用いる水素含有原
料ガス、あるいはアルミニウム配線を低抵抗化するため
の熱処理に用いる水素などから供給される。
However, when the metal oxide film is exposed to a reducing gas such as hydrogen or silane (silicon hydride), the metal oxide film is easily reduced and becomes a metal excess composition. It shows electrical conductivity, and a problem arises in that charge cannot be stored in a capacitor due to current leakage. The reducing gas after the formation of the capacitive element is supplied from, for example, a hydrogen-containing source gas used for depositing an interlayer insulating film, or hydrogen used for a heat treatment for reducing the resistance of an aluminum wiring.

【0004】図2は従来の半導体装置の製造方法を示す
工程断面図である。まず、図2(a)に示すように、シ
リコン基板を用いた半導体基板1上に、容量素子の下部
電極の形成領域を開口した絶縁膜2を形成し、その後、
絶縁膜2の開口に導電性の下部電極3を形成する。次
に、図2(b)に示すように、金属酸化膜からなる容量
絶縁膜4と上部電極5とを全面に積層して堆積し、レジ
スト6のパターニングを行う。つづいて図2(c)に示
すように、レジスト6をマスクとして容量絶縁膜4と上
部電極5を一括してエッチングし容量素子を得る。しか
しこの図2(c)に示される従来構造の容量素子(例え
ば、特開平7−235639号公報に記載のものも同
様)では、金属酸化膜からなる容量絶縁膜4の端部側壁
は露出しており還元性ガスの侵入が容易である。
FIG. 2 is a process sectional view showing a conventional method for manufacturing a semiconductor device. First, as shown in FIG. 2A, on a semiconductor substrate 1 using a silicon substrate, an insulating film 2 having an opening in a region where a lower electrode of a capacitor is formed is formed.
A conductive lower electrode 3 is formed in the opening of the insulating film 2. Next, as shown in FIG. 2B, a capacitor insulating film 4 made of a metal oxide film and an upper electrode 5 are stacked and deposited on the entire surface, and the resist 6 is patterned. Subsequently, as shown in FIG. 2C, the capacitive insulating film 4 and the upper electrode 5 are collectively etched using the resist 6 as a mask to obtain a capacitive element. However, in the capacitor having the conventional structure shown in FIG. 2C (for example, the same as that described in Japanese Patent Application Laid-Open No. 7-235639), the end side wall of the capacitor insulating film 4 made of a metal oxide film is exposed. And the ingress of reducing gas is easy.

【0005】このような容量絶縁膜4の端部側壁の露出
を防ぐためには、図3(d)や特開平7−161934
号公報に示されるように、金属酸化膜からなる容量絶縁
膜4を金属窒化膜からなる上部電極5で完全に覆ってし
まう必要がある。図3は他の従来の半導体装置の製造方
法を示す工程断面図である。この方法では、図3(a)
に示すように、容量絶縁膜4を堆積した後、レジスト7
をパターニングし、そのレジスト7をマスクとして一旦
容量絶縁膜4のエッチングを行い(図3(b))、さら
に図3(c)に示すように、上部電極5を堆積後にレジ
スト8をパターニングしてエッチングして容量素子を得
ることになり、図2に示された製造方法に比べて複雑化
した工程が必要である。マスク合わせ回数の増加はコス
トを上昇させ、技術的にも微細パターンを高精度に作製
するという困難さが加わってしまう。さらに容量絶縁膜
4上にレジスト7を堆積することになり、容量絶縁膜4
と上部電極5の界面の汚染による素子特性の劣化も問題
となる。
In order to prevent the end side wall of the capacitive insulating film 4 from being exposed, FIG. 3D and FIG.
As shown in the publication, it is necessary to completely cover the capacitance insulating film 4 made of a metal oxide film with the upper electrode 5 made of a metal nitride film. FIG. 3 is a process sectional view showing another conventional method for manufacturing a semiconductor device. In this method, FIG.
As shown in FIG. 7, after the capacitive insulating film 4 is deposited, a resist 7 is formed.
The capacitor 7 is once etched using the resist 7 as a mask (FIG. 3B), and as shown in FIG. 3C, after the upper electrode 5 is deposited, the resist 8 is patterned. Since a capacitor is obtained by etching, a complicated process is required as compared with the manufacturing method shown in FIG. The increase in the number of times of mask alignment increases the cost, and technically, it is difficult to manufacture a fine pattern with high accuracy. Further, a resist 7 is deposited on the capacitance insulating film 4 and the capacitance insulating film 4
There is also a problem of deterioration of device characteristics due to contamination of the interface between the electrode and the upper electrode 5.

【0006】そこで本発明の目的は、金属酸化膜からな
る容量絶縁膜が還元性ガスの曝露によって導電性になる
ことを防止するために容量絶縁膜が金属窒化膜からなる
上部電極で覆われた容量素子を、工程を簡略化するとと
もに加工精度を向上し、かつ素子特性の劣化を防止して
作製できる半導体装置の製造方法を提供することであ
る。
Therefore, an object of the present invention is to prevent the capacitance insulating film made of a metal oxide film from becoming conductive by exposure to a reducing gas, so that the capacitance insulating film is covered with an upper electrode made of a metal nitride film. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of manufacturing a capacitor by simplifying a process, improving processing accuracy, and preventing deterioration of element characteristics.

【0007】[0007]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体基板上に形成された開口を有する絶縁
膜の開口に容量素子の下部電極となる導電膜を形成する
第1の工程と、半導体基板上に真空中で有機金属系の原
料ガスを断続的に供給することによって導電膜の表面の
みに選択的に導電性の金属酸化膜を堆積する第2の工程
と、導電性の金属酸化膜を酸化性雰囲気中で熱処理する
ことによって絶縁性の金属酸化膜に改質する第3の工程
と、容量素子の上部電極となる金属窒化膜を絶縁性の金
属酸化膜を覆うように形成する第4の工程とを含む。
According to a method of manufacturing a semiconductor device of the present invention, a first step of forming a conductive film serving as a lower electrode of a capacitor in an opening of an insulating film having an opening formed on a semiconductor substrate is provided. And a second step of selectively depositing a conductive metal oxide film only on the surface of the conductive film by intermittently supplying an organometallic source gas in a vacuum on the semiconductor substrate; A third step of reforming the metal oxide film into an insulating metal oxide film by heat-treating the metal oxide film in an oxidizing atmosphere; and forming a metal nitride film serving as an upper electrode of the capacitor element so as to cover the insulating metal oxide film. And forming a fourth step.

【0008】この製造方法によれば、容量素子の作製に
おいて、半導体基板上に真空中で有機金属系の原料ガス
を断続的に供給することによって、容量絶縁膜となる金
属酸化膜を下部電極(導電膜)の表面にのみ選択的に堆
積することができ、微細なパターンをエッチングせずに
自己整合して形成することができるため、加工精度を向
上することができる。また、容量絶縁膜をリソグラフィ
ーとエッチングを用いずに形成するため、工程を簡略化
することができる。また、容量絶縁膜の堆積と上部電極
の堆積を連続して行うので容量絶縁膜と上部電極との界
面が汚染されることがなく、容量素子の劣化を防止でき
る。
According to this manufacturing method, in the production of a capacitive element, a metal oxide film serving as a capacitive insulating film is intermittently supplied on a semiconductor substrate in a vacuum to form a metal oxide film serving as a capacitive insulating film. Since it can be selectively deposited only on the surface of the conductive film) and can be formed in a self-aligned manner without etching a fine pattern, processing accuracy can be improved. Further, since the capacitor insulating film is formed without using lithography and etching, the process can be simplified. Further, since the deposition of the capacitor insulating film and the deposition of the upper electrode are performed successively, the interface between the capacitor insulating film and the upper electrode is not contaminated, and deterioration of the capacitor can be prevented.

【0009】金属酸化膜には、タンタル、ビスマス、ス
トロンチウム、チタン、バリウムのいずれか一つを含む
金属酸化物を用いることが好ましい。
It is preferable to use a metal oxide containing any one of tantalum, bismuth, strontium, titanium and barium for the metal oxide film.

【0010】また、金属窒化膜には、チタン、バナジウ
ム、クロム、ジルコニウム、ニオブ、モリブデン、ハフ
ニウム、タンタル、タングステンのいずれか一つを含む
金属窒化物を用いることが好ましい。
It is preferable to use a metal nitride containing any one of titanium, vanadium, chromium, zirconium, niobium, molybdenum, hafnium, tantalum, and tungsten for the metal nitride film.

【0011】[0011]

【発明の実施の形態】本発明の実施の形態を、図面を参
照しながら説明する。図1は、本発明の実施の形態にお
ける容量素子の製造方法の工程断面図を示すものであ
る。
Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a process sectional view of a method of manufacturing a capacitive element according to an embodiment of the present invention.

【0012】まず周知の方法を用いて、図1(a)に示
すように、シリコン基板からなる半導体基板1上に、容
量素子の下部電極の形成領域を開口した酸化シリコンの
絶縁膜2(厚さ:例えば20nm)を形成し、その後、
絶縁膜2の開口に導電膜からなる容量素子の下部電極3
を形成する。この導電膜としては、例えばドープドシリ
コン膜(厚さ:例えば100nm)を形成する。絶縁膜
2は素子分離のためのものである。
First, using a well-known method, as shown in FIG. 1A, an insulating film 2 (thickness) of silicon oxide is formed on a semiconductor substrate 1 made of a silicon substrate. Is formed, for example, 20 nm).
A lower electrode 3 of a capacitive element made of a conductive film in an opening of the insulating film 2
To form As this conductive film, for example, a doped silicon film (thickness: for example, 100 nm) is formed. The insulating film 2 is for element isolation.

【0013】次に、図1(b)に示すように、有機金属
系の原料ガス(例えばペンタエトキシタンタル)を半導
体基板1上に30Pa以下の真空中で断続的に供給し、
金属酸化膜(例えば酸化タンタル)からなる容量絶縁膜
4を下部電極3表面にのみ選択的に堆積する。有機金属
系の原料ガスの供給時間と中断時間の比は1:2であ
る。供給時間は20秒から1分であり、供給時間に対応
して中断時間を40秒から2分とする。堆積を行う温度
範囲は、500℃以下である。
Next, as shown in FIG. 1B, an organometallic source gas (for example, pentaethoxy tantalum) is intermittently supplied onto the semiconductor substrate 1 in a vacuum of 30 Pa or less.
A capacitance insulating film 4 made of a metal oxide film (for example, tantalum oxide) is selectively deposited only on the surface of the lower electrode 3. The ratio between the supply time of the organometallic source gas and the interruption time is 1: 2. The supply time is 20 seconds to 1 minute, and the interruption time is 40 seconds to 2 minutes corresponding to the supply time. The temperature range in which the deposition is performed is 500 ° C. or less.

【0014】ドープドシリコン膜からなる下部電極3の
表面には原子の結合に寄与しない電子(以下、ダングリ
ングボンドと記す)が多く、このダングリングボンドは
ペンタエトキシタンタルの分解に対して触媒の効果があ
る。したがってペンタエトキシタンタルは容易に分解
し、速い堆積速度で酸化タンタルが堆積する。一方、酸
化シリコンの絶縁膜2上ではダングリングボンドが少な
く、ペンタエトキシタンタルは分解しにくく、酸化タン
タルは堆積しない。たとえ堆積してもペンタエトキシタ
ンタルの断続的な供給中断によって付着した原子は再蒸
発するため、選択的な酸化タンタルの堆積が可能とな
る。また、有機金属系の原料ガスを用いているため、酸
化タンタルには炭素や水素などの不純物が混入してお
り、酸化タンタル本来の特性は絶縁体であるが、堆積直
後は導電体になっている。したがって酸化タンタルの容
量絶縁膜4上にもダングリングボンドは存在し、たとえ
膜厚が厚くなっても選択的堆積は維持されつづける。そ
して、所望の膜厚の酸化タンタル(厚さ:例えば10n
m)を堆積する。酸化タンタルの膜厚は5nm以上20
nm以下であれば構わない。
The surface of the lower electrode 3 made of a doped silicon film has many electrons (hereinafter referred to as dangling bonds) that do not contribute to the bonding of atoms, and these dangling bonds act as catalysts for the decomposition of pentaethoxy tantalum. effective. Therefore, pentaethoxy tantalum is easily decomposed, and tantalum oxide is deposited at a high deposition rate. On the other hand, dangling bonds are small on the silicon oxide insulating film 2, pentaethoxy tantalum is hardly decomposed, and tantalum oxide is not deposited. Even if it is deposited, the attached atoms are re-evaporated due to the intermittent interruption of the supply of pentaethoxy tantalum, so that selective deposition of tantalum oxide is possible. In addition, since tantalum oxide is mixed with impurities such as carbon and hydrogen because of the use of organometallic raw material gas, the original characteristics of tantalum oxide are insulators, but it becomes a conductor immediately after deposition. I have. Therefore, dangling bonds also exist on the tantalum oxide capacitance insulating film 4, and even if the film thickness increases, the selective deposition is maintained. Then, tantalum oxide having a desired film thickness (thickness: for example, 10 n
m). The thickness of tantalum oxide is 5 nm or more and 20
nm or less.

【0015】次に、堆積された容量絶縁膜4を酸素、一
窒化酸素、二窒化酸素などの酸化性雰囲気中で熱処理を
加える。熱処理の条件は700℃以上、30秒以上であ
る。この熱処理により、堆積中に容量絶縁膜4に混入し
た炭素や水素が除去され、除去された原子の格子位置に
は酸素が挿入される。この結果、容量絶縁膜4は導電性
から本来の特性である絶縁性へ改質される。
Next, the deposited capacitive insulating film 4 is subjected to a heat treatment in an oxidizing atmosphere such as oxygen, oxygen mononitride, or oxygen dinitride. The conditions of the heat treatment are 700 ° C. or more and 30 seconds or more. By this heat treatment, carbon and hydrogen mixed in the capacitive insulating film 4 during the deposition are removed, and oxygen is inserted into lattice positions of the removed atoms. As a result, the capacitance insulating film 4 is modified from conductivity to insulation, which is the original characteristic.

【0016】次に、図1(c)に示すように、金属窒化
膜(例えば窒化チタン)からなる上部電極5を堆積し、
その上にレジスト6をパターニングし、レジスト6をマ
スクとして上部電極5をエッチングした後、レジスト6
を除去すると、容量素子が得られる(図1(d))。
Next, as shown in FIG. 1C, an upper electrode 5 made of a metal nitride film (for example, titanium nitride) is deposited,
A resist 6 is patterned thereon, and the upper electrode 5 is etched using the resist 6 as a mask.
Is removed, a capacitive element is obtained (FIG. 1D).

【0017】以上のように本実施の形態によれば、下部
電極3の表面にのみ選択的に自己整合して容量絶縁膜4
を堆積できるため、図3のように容量絶縁膜4を全面に
堆積してエッチングした場合に比べて工程数が少なく、
かつ精度良く形成することができる。また、容量絶縁膜
4の堆積と上部電極5の堆積を連続して行うため、容量
絶縁膜4と上部電極5の界面に汚染を与えることなく形
成することができ、その界面に汚染による素子特性の劣
化を防止できる。また、容量絶縁膜4は、金属窒化膜の
上部電極5で完全に覆われ、容量絶縁膜4の側壁端部が
露出していないため、還元性ガスの曝露から保護するこ
とができる。例えば、容量素子形成後に還元性ガスを含
む原料ガスで層間絶縁膜を堆積させても、あるいはアル
ミニウム配線形成後に水素熱処理を行っても、金属酸化
膜からなる容量絶縁膜4が還元されることはなく、電気
的特性の劣化を防止できる。
As described above, according to the present embodiment, the capacitance insulating film 4 is selectively self-aligned only to the surface of the lower electrode 3.
Therefore, the number of steps is smaller than the case where the capacitive insulating film 4 is deposited over the entire surface and etched as shown in FIG.
In addition, it can be formed with high accuracy. In addition, since the deposition of the capacitor insulating film 4 and the deposition of the upper electrode 5 are performed continuously, the capacitor insulating film 4 can be formed without contaminating the interface between the capacitor insulating film 4 and the upper electrode 5. Degradation can be prevented. Further, since the capacitor insulating film 4 is completely covered with the upper electrode 5 of the metal nitride film and the side wall end of the capacitor insulating film 4 is not exposed, it can be protected from exposure to the reducing gas. For example, even if an interlayer insulating film is deposited with a source gas containing a reducing gas after forming a capacitive element, or a hydrogen heat treatment is performed after forming an aluminum wiring, the capacitive insulating film 4 made of a metal oxide film is reduced. In addition, it is possible to prevent deterioration of electrical characteristics.

【0018】本実施の形態では、容量絶縁膜4に酸化タ
ンタルを例にとり説明したが、チタン酸バリウムストロ
ンチウム(BST)等でもよく、タンタル、ビスマス、
ストロンチウム、チタン、バリウムのいずれか1つを含
む金属酸化膜であれば同様の効果が得られることは言う
までもない。いずれの金属酸化膜からなる容量絶縁膜4
を形成する場合も、有機金属系の原料ガス、すなわち容
量絶縁膜4を構成する金属を含む有機金属ガスと酸化ガ
スを、真空中で半導体基板1上に断続的に供給すること
により、自己整合的に形成できる。有機金属系の原料ガ
スとしては、ペンタエトキシタンタルの他、例えばテト
ライソプロポキシチタニウム{Ti(i−OC3 7
4 }、ビスジピバロイルメタナートバリウム{Ba(D
PM)2;Ba(O2 11192 }、ビスジピバロイ
ルメタナートストロンチウム{Sr(DPM)2 ;Sr
(O2 11192 }等がある。
In the present embodiment, the capacitance insulating film 4 has been described using tantalum oxide as an example. However, barium strontium titanate (BST) or the like may be used, and tantalum, bismuth,
Needless to say, a similar effect can be obtained if a metal oxide film contains any one of strontium, titanium, and barium. Capacitive insulating film 4 of any metal oxide film
Is formed, an organic metal-based source gas, that is, an organic metal gas containing a metal constituting the capacitive insulating film 4 and an oxidizing gas are intermittently supplied onto the semiconductor substrate 1 in a vacuum, so that self-alignment is achieved. Can be formed. As a raw material gas of organic metal-based, other pentaethoxytantalum, such as tetra-isopropoxy titanium {Ti (i-OC 3 H 7)
4 }, bisdipivaloyl methanate barium {Ba (D
PM) 2 ; Ba (O 2 C 11 H 19 ) 2 }, bis dipivaloyl methanato strontium {Sr (DPM) 2 ; Sr
(O 2 C 11 H 19 ) 2 }.

【0019】また、上部電極5に窒化チタンを例にとり
説明したが、窒化タンタルや窒化タングステン等でもよ
く、チタン、バナジウム、クロム、ジルコニウム、ニオ
ブ、モリブデン、ハフニウム、タンタル、タングステン
のいずれか1つを含む金属窒化膜であれば同様の効果が
得られることは言うまでもない。
Although titanium nitride has been described as an example of the upper electrode 5, tantalum nitride, tungsten nitride or the like may be used. It goes without saying that a similar effect can be obtained if the metal nitride film contains the same.

【0020】[0020]

【発明の効果】以上の説明から明らかなように本発明の
半導体装置の製造方法によれば、容量素子の作製におい
て、半導体基板上に真空中で有機金属系の原料ガスを断
続的に供給することによって、容量絶縁膜となる金属酸
化膜を下部電極(導電膜)の表面にのみ選択的に堆積す
ることができ、微細なパターンをエッチングせずに自己
整合して形成することができるため、加工精度を向上す
ることができる。また、容量絶縁膜をリソグラフィーと
エッチングを用いずに形成するため、工程を簡略化する
ことができる。また、容量絶縁膜の堆積と上部電極の堆
積を連続して行うので容量絶縁膜と上部電極との界面が
汚染されることがなく、容量素子の劣化を防止できる。
本発明によって形成された容量素子では、金属酸化膜か
らなる容量絶縁膜が金属窒化膜の上部電極で覆われ、容
量絶縁膜の側壁端部が露出していないため、還元性ガス
の曝露から保護することができ、例えば、容量素子形成
後に還元性ガスを含む原料ガスで層間絶縁膜を堆積させ
ても、あるいはアルミニウム配線形成後に水素熱処理を
行っても、金属酸化膜からなる容量絶縁膜が還元される
ことはなく、電気的特性の劣化を防止できる。
As is apparent from the above description, according to the method of manufacturing a semiconductor device of the present invention, in manufacturing a capacitor, an organometallic source gas is intermittently supplied to a semiconductor substrate in a vacuum. Thus, a metal oxide film serving as a capacitor insulating film can be selectively deposited only on the surface of the lower electrode (conductive film), and a fine pattern can be formed in a self-aligned manner without etching. Processing accuracy can be improved. Further, since the capacitor insulating film is formed without using lithography and etching, the steps can be simplified. Further, since the deposition of the capacitive insulating film and the deposition of the upper electrode are performed successively, the interface between the capacitive insulating film and the upper electrode is not contaminated, and deterioration of the capacitive element can be prevented.
In the capacitive element formed according to the present invention, the capacitive insulating film made of the metal oxide film is covered with the upper electrode of the metal nitride film, and the side wall end of the capacitive insulating film is not exposed, so that it is protected from exposure to the reducing gas. For example, even if an interlayer insulating film is deposited with a source gas containing a reducing gas after forming a capacitive element, or a hydrogen heat treatment is performed after forming an aluminum wiring, a capacitive insulating film made of a metal oxide film can be reduced. And the deterioration of the electrical characteristics can be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態の半導体装置の製造方法を
示す工程断面図である。
FIG. 1 is a process sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

【図2】従来の半導体装置の製造方法を示す工程断面図
である。
FIG. 2 is a process cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

【図3】他の従来の半導体装置の製造方法を示す工程断
面図である。
FIG. 3 is a process sectional view illustrating another conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 絶縁膜 3 下部電極(導電膜) 4 容量絶縁膜(金属酸化膜) 5 上部電極(金属窒化膜) Reference Signs List 1 semiconductor substrate 2 insulating film 3 lower electrode (conductive film) 4 capacitance insulating film (metal oxide film) 5 upper electrode (metal nitride film)

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に形成された開口を有する
絶縁膜の前記開口に容量素子の下部電極となる導電膜を
形成する第1の工程と、前記半導体基板上に真空中で有
機金属系の原料ガスを断続的に供給することによって前
記導電膜の表面のみに選択的に導電性の金属酸化膜を堆
積する第2の工程と、前記導電性の金属酸化膜を酸化性
雰囲気中で熱処理することによって絶縁性の金属酸化膜
に改質する第3の工程と、前記容量素子の上部電極とな
る金属窒化膜を前記絶縁性の金属酸化膜を覆うように形
成する第4の工程とを含む半導体装置の製造方法。
A first step of forming a conductive film serving as a lower electrode of a capacitor in the opening of an insulating film having an opening formed on a semiconductor substrate; A second step of selectively depositing a conductive metal oxide film only on the surface of the conductive film by intermittently supplying the material gas of the above, and heat treating the conductive metal oxide film in an oxidizing atmosphere. And a fourth step of forming a metal nitride film serving as an upper electrode of the capacitive element so as to cover the insulating metal oxide film. And a method for manufacturing a semiconductor device.
【請求項2】 金属酸化膜は、タンタル、ビスマス、ス
トロンチウム、チタン、バリウムのいずれか一つを含む
金属酸化物からなることを特徴とする請求項1記載の半
導体装置の製造方法。
2. The method according to claim 1, wherein the metal oxide film is made of a metal oxide containing any one of tantalum, bismuth, strontium, titanium, and barium.
【請求項3】 金属窒化膜は、チタン、バナジウム、ク
ロム、ジルコニウム、ニオブ、モリブデン、ハフニウ
ム、タンタル、タングステンのいずれか一つを含む金属
窒化物からなることを特徴とする請求項1記載の半導体
装置の製造方法。
3. The semiconductor according to claim 1, wherein the metal nitride film is made of a metal nitride containing any one of titanium, vanadium, chromium, zirconium, niobium, molybdenum, hafnium, tantalum, and tungsten. Device manufacturing method.
JP11132616A 1999-05-13 1999-05-13 Manufacture of semiconductor device Pending JP2000323678A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11132616A JP2000323678A (en) 1999-05-13 1999-05-13 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11132616A JP2000323678A (en) 1999-05-13 1999-05-13 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JP2000323678A true JP2000323678A (en) 2000-11-24

Family

ID=15085505

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11132616A Pending JP2000323678A (en) 1999-05-13 1999-05-13 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JP2000323678A (en)

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