JP2000323650A - Trimmer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a technique for reducing the layout area of a trimmer circuit. SOLUTION: A first switch circuit 15-1 switches the resultant resistance of a first resistor group 14-1 according to an inputted digital signal, and a second switch circuit 15-2 switches the resultant resistance of a second resistor group 14-2 according to the inputted digital signal. Thus, the switching of the resultant resistance is operated by the first switch circuit 15-1 and the second switch circuit 15-2 so that the trimming of the resistance can be realized, and decoder for decoding the inputting digital signal can be unnecessitated. As a result, the layout area of the trimmer circuit can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trimming circuit for adjusting a resistance value, and is effective when applied to, for example, a D / A (digital / analog) conversion circuit for converting an input digital signal into an analog signal. Technology.

[0002]

2. Description of the Related Art For example, in a D / A conversion circuit for converting an input digital signal into an analog signal, it is necessary to adjust a resistance value in accordance with the input digital signal. A circuit is provided. In the trimming circuit, a plurality of resistors are connected in series with each other, and a desired resistance value involved in the circuit is obtained by appropriately selecting a series connection node.

[0003] As an example of a document describing a trimming circuit, "A / D. A / D in the digital AV era" issued by the Technical Information Association on September 28, 1992
D / A conversion circuit technology (page 99-).

[0004]

FIG. 2 shows a circuit to be compared with a trimming circuit according to the present invention.

An operational amplifier 12 and a resistor group 18 in which a plurality of resistors are connected in series with each other are provided. A series connection node of the plurality of resistors is selectively connected to the inverting input terminal ( A switch 17 for coupling to-) is coupled. The switch 17 includes a p-channel MOS transistor Q31 and an n-channel MOS transistor Q32 connected in parallel.
It is controlled based on the output signal of the decoder 13 that decodes the bit digital signal. p-channel type MOS
In order to simultaneously turn on and off the transistor Q31 and the n-channel MOS transistor Q32 connected in parallel to it, the output signal of the decoder 13 is directly transmitted to the gate electrode of the n-channel MOS transistor Q32, and the p-channel MOS transistor Q31 Is transmitted after the output signal of the decoder 13 is logically inverted by the inverter 16. The reference voltage (Vref) 11 is transmitted to the non-inverting input terminal (+) of the operational amplifier 12.
A plurality of switches 17 based on the output logic of the decoder 13
Is turned on, the potential of the series connection node of the corresponding resistor is selectively turned on.
Is transmitted to the inverting input terminal of the
The comparison result is fed back to the inverting input terminal of the operational amplifier 12 via the resistor group 18, so that the output potential of the operational amplifier 12 is stabilized at a predetermined value. Since the series connection nodes of the resistors are selectively switched by the input digital signals D0 to D4, the output potential of the operational amplifier 12 is changed accordingly. Vdd is a high-potential-side power supply.

The decoder 13 decodes digital signals D0 to D4 as shown in FIG.
5 inverters 132-1 to 132-5, and 12 NAND gates 131-1 to 131- disposed in the subsequent stage
12 and 32 NOR gates 13 arranged at the subsequent stage
3-1 to 133-32 are combined. NOR gate 1
The output signals of 33-1 to 133-32 are supplied to the decoder 1
3 decoded output signal.

As described above, the decoder 13 is provided, and the series connection node of the resistor group 18 is selected based on the output signal of the decoder 13. Therefore, when the number of bits of the input digital signal increases, It has been found by the present inventors that the number of gates constituting the decoder increases and the layout area of the trimming circuit increases.

An object of the present invention is to provide a technique for reducing the layout area of a trimming circuit.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the first resistor group (14-1), the second resistor group (14-2) connected in series thereto, and both ends of each of the resistors constituting the first resistor group can be individually short-circuited. A plurality of first conductivity type transistors (Q1
1 to Q15).
1) and a second switch circuit (15-2) including a plurality of second conductivity type transistors (Q21 to Q25) in which both ends of each of the resistors constituting the second resistor group are individually short-circuited. ).

According to the above means, the first switch circuit switches the combined resistance value of the first resistor group in accordance with the input digital signal, and the second switch circuit switches in accordance with the input digital signal. The combined resistance value of the second resistor group is switched. Thus, the first switch circuit and the second switch circuit
The switching of the combined resistance value by the switch circuit enables the trimming of the resistance value, and eliminates the need for a decoder for decoding the input digital signal. This reduces the layout area of the trimming circuit.

At this time, the first resistor group and the second resistor group
In the resistor group, when the value of the resistor corresponding to the least significant bit is 1R, the value of the resistor corresponding to the n-th bit is:
2 ⁿ R.

A resistor group (18) provided between the output terminal of the operational amplifier and the ground and having a plurality of resistors connected in series to each other, and a decoder (51) for decoding an input digital signal. And a selection circuit (16, Q31, Q32) capable of selecting a series connection node in the resistor group based on the output signal of the decoder, a trimming circuit is configured. And a second conductivity type transistor (Q12) connected in parallel to the resistor on the other end of the resistor group, and the same bit data in the digital signal. (D0) is commonly input to the gate electrode of the first conductivity type transistor and the gate electrode of the second conductivity type transistor. It can be formed.

According to the above-described means, the same bit data (D0) in the digital signal is commonly input to the gate electrode of the first conductivity type transistor and the gate electrode of the second conductivity type transistor. Is controlled, the voltage division ratio as viewed from the center of the resistor group is switched. This eliminates the need for the decoder to decode bits commonly input to the gate electrode of the first conductivity type transistor and the gate electrode of the second conductivity type transistor, thereby simplifying the configuration of the decoder. Can be achieved. Thus, the layout area of the trimming circuit can be reduced.

[0015]

FIG. 1 shows a configuration example of a trimming circuit according to the present invention.

The trimming circuit shown in FIG. 1 is not particularly limited, but can be formed by a known semiconductor integrated circuit manufacturing technique.
It is formed on one semiconductor substrate such as a silicon substrate.

The difference between the reference voltage input through the inverting input terminal (-), the non-inverting input terminal (+), and the signal input through the non-inverting input terminal is output. (Operational amplifier) 12 having an output terminal therefor, and a trimming circuit 10 coupled thereto.
0 is provided.

The trimming circuit 100 includes a first resistor group 14-1, a second resistor group 14-2, a first switch circuit 15
-1 and a second switch circuit 15-2.

The first resistor group 14-1 includes a plurality of resistors connected in series to each other, and is coupled between the output terminal and the inverting input terminal of the operational amplifier.

The second resistor group 14-2 includes a plurality of resistors connected in series to each other, and is coupled between the inverting input terminal of the operational amplifier 12 and the ground GND.

The first switch circuit 15-1 includes five p-channel MOS transistors Q11 to Q11 arranged corresponding to the number of bits of the inputted digital signals D0 to D4.
Q15, and the input digital signals D0-D
4, the combined resistance value of the first resistor group 14-1 is switched.

The second switch circuit 15-2 includes five n-channel MOS transistors Q21 to Q21 arranged corresponding to the number of bits of the input digital signals D0 to D4.
Q25, and switches the combined resistance value of the second resistor group 14-2 according to the input digital signal.

Here, in the first resistor group 14-1 and the second resistor group 14-2, when the value of the resistor corresponding to the least significant bit (0th bit) D0 of the input digital signal is 1R. , The value of the resistor corresponding to the n-th bit is 2
ⁿ R. That is, the input digital signals D0 to D4
Are 1R, 2R, 4R, 8R, and 16R, and the resistance value increases exponentially when viewed from the least significant bit.

The p-channel type MOS transistors Q11 to Q15 and the n-channel type MOS transistors Q21 to Q25 are connected so as to short-circuit both terminals of the corresponding resistors.

That is, the p-channel MOS transistor Q11 is connected to the resistor 1R in the first resistor group 14-1 so as to be short-circuited.
Reference numeral 12 denotes a p-channel MOS transistor Q13 which is connected to the resistor 2R in the first resistor group 14-1 so as to be short-circuited.
Is connected so that the resistor 4R in the first resistor group 14-1 can be short-circuited, the p-channel MOS transistor Q14 is connected so that the resistor 8R in the first resistor group 14-1 can be short-circuited, and the p-channel MOS transistor Q15 is The resistor 16R in the one resistor group 14-1 is short-circuitably connected.

Similarly, the n-channel MOS transistor Q21 is connected to the resistor 1R in the second resistor group 14-2 so as to be short-circuited, and is connected to the p-channel MOS transistor Q21.
Reference numeral 22 denotes an n-channel MOS transistor Q23 which is connected to the resistor 2R in the second resistor group 14-2 so as to be short-circuited.
Is connected so that the resistor 4R in the second resistor group 14-2 can be short-circuited, the n-channel MOS transistor Q24 is connected so that the resistor 8R in the second resistor group 14-2 can be short-circuited, and the n-channel MOS transistor Q25 is The resistor 16R in the two resistor group 14-2 is coupled to be short-circuitable.

The p-channel MOS transistor Q11 and the n-channel M transistor
The OS transistor Q21 is complementarily turned on and off, the first bit data D1 is used to complementarily turn on and off the p-channel MOS transistor Q12 and the n-channel MOS transistor Q22, and the second bit data D2 is used. P-channel type MOS transistor Q13 and n-channel type MOS transistor Q
23 are complementarily turned on and off, and the p-channel MOS transistor Q is controlled by the third bit data D3.
14 and the n-channel MOS transistor Q24 are complementarily turned on / off, and the data D5 of the fourth bit complementarily turns on / off the p-channel MOS transistor Q15 and the n-channel MOS transistor Q25.

In the above configuration, the digital signal D0
To D4, p-channel MOS transistors Q11 to Q15, n
By controlling the channel type MOS transistors Q21 to Q25, the first resistor group 14-1 and the second resistor group 1 are controlled.
4-2 is determined, the potential of the inverting input terminal (−) terminal of the operational amplifier 12 is determined accordingly, and feedback control is performed based on the comparison result with the reference voltage Vref. An output voltage OUT can be obtained. This output voltage corresponds to the digital signal D
The DC voltage is at a level corresponding to 0 to D4.

FIG. 4 shows a comparison result between the circuit shown in FIG. 1 and the circuits shown in FIGS. In the circuits shown in FIGS. 2 and 3, since the decoder 13 was used, five inverters, 12 NAND gates, and 32 NOR gates were required. In the circuit shown in FIG. Since no decoder is required, the number of logic gates is significantly reduced. Further, in the circuits shown in FIGS. 2 and 3, 32 switches are required. However, in the circuit shown in FIG. 1, only 10 switches are required to achieve the same resolution. As a result, the circuit shown in FIG. 1 can significantly reduce the layout area as compared with the circuits shown in FIGS.

According to the above-described example, the following effects can be obtained.

The first switch circuit 15-1 is connected to the first resistor group 14 according to the input digital signals D0 to D4.
−1, the second switch circuit 15−
2 switches the combined resistance value of the second resistor group 14-2 according to the input digital signals D0 to D4. The switching of the combined resistance value by the first switch circuit and the second switch circuit enables trimming of the resistance value. This eliminates the need for a decoder for decoding the input digital signal, so that the layout area of the trimming circuit can be reduced.

Although the invention made by the inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

For example, instead of completely omitting a decoder for decoding an input digital signal, decoding of some bits may be omitted. For example, as shown in FIG. 5, of the input digital signals D0 to D4, the circuit method shown in FIG. 1 is applied only to the 0th bit data D0, and the other data D1 to D4 are As in the circuits shown in FIGS. 2 and 3, a configuration in which decoding is performed by a decoder can be employed. Since D1 to D4 are 4 bits, 2 × 2 × 2 × 2 =
It becomes 16. On the other hand, bit D0 represents one bit in the present method. By switching this D0 to a high level and a low level, 16 (D1 to D4) × 2 ways (D0) = 3
2, which can represent 5 bits. In FIG. 5, the plurality of resistors constituting the resistor group 18 can all have the same value as in the case shown in FIG.

If the circuit system shown in FIG. 1 is applied to only the data D0 of the digital signals D0 to D4,
The number of output terminals of the decoder 51 can be reduced to the decoder 131/2 (= 16) shown in FIG.
The layout area of the trimming circuit can be reduced.

FIG. 6 shows a case where the trimming circuit according to the present invention is applied to a D / A conversion circuit.

When a D / A conversion circuit is configured, the operational amplifier 12 is a voltage follower having an output terminal and an inverting input terminal coupled to each other. The first resistor group 14-1 and the second resistor group
The resistor group 14-2 is connected in series, and the output voltage of the operational amplifier 12 is supplied to it. A D / A conversion output OUT is obtained from a series connection node of the first resistor group 14-1 and the second resistor group 14-2. A first switch circuit 15-1,
The configuration of the second switch circuit 15-2 and the coupling state between the second switch circuit 15-2 and the first resistor group 14-1 or the second resistor group 14-2 are shown in FIG.
Is the same as the case shown in FIG.

As in the case shown in FIG. 1, since a decoder for decoding digital signals D0 to D4 is not provided, the layout area can be reduced as in the circuit shown in FIG.

In the above description, the invention made mainly by the present inventor is referred to as D / A, which is a field of application which is the background of the invention.
Although the case where the present invention is applied to a conversion circuit has been described, the present invention is not limited to this, and can be widely applied to various logic circuits requiring trimming.

The present invention can be applied on the condition that a resistor group including at least a plurality of resistors connected in series is provided.

[0040]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the first switch circuit switches the combined resistance value of the first resistor group according to the input digital signal, and the second switch circuit controls the second resistor group according to the input digital signal. Switch the combined resistance value. By switching the combined resistance value by the first switch circuit and the second switch circuit in this manner, the trimming of the resistance value is enabled, so that a decoder for decoding the input digital signal is not required. ,
Thereby, the layout area of the trimming circuit can be reduced.

The same bit of data in the digital signal is commonly input to the gate electrode of the first conductivity type transistor and the gate electrode of the second conductivity type transistor, and their operations are controlled. By switching the voltage division ratio as viewed from the center of the resistor group, in the decoder, for the bit commonly input to the gate electrode of the first conductivity type transistor and the gate electrode of the second conductivity type transistor Need not be decoded, and the configuration of the decoder can be simplified accordingly. Thus, the layout area of the trimming circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration example of a trimming circuit according to the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a circuit to be compared with the circuit shown in FIG. 1;

FIG. 3 is a circuit diagram showing a detailed configuration example of a decoder included in the circuit shown in FIG. 2;

4 is an explanatory diagram of a comparison result between the circuit shown in FIG. 1 and the circuits shown in FIGS. 2 and 3. FIG.

FIG. 5 is a circuit diagram illustrating another configuration example of the trimming circuit according to the present invention.

FIG. 6 shows a D to which the trimming circuit according to the present invention is applied;
FIG. 3 is a circuit diagram illustrating a configuration example of an / A conversion circuit.

[Explanation of symbols]

 12 operational amplifier 14-1 first resistor group 14-2 second resistor group 15-1 first switch circuit 15-2 second switch circuit Q11-Q15 p-channel MOS transistors Q21-Q25 n-channel MOS transistors

Continued on the front page (72) Inventor Sou Segawa 15 Asahidai, Moroyama-cho, Iruma-gun, Saitama Prefecture Inside Nissan Eastern Semiconductor Co., Ltd. (72) Inventor Masaki Kudo 15-shi Asadaidai, Moroyama-machi, Iruma-gun, Saitama Nissha Eastern Semiconductor Co., Ltd. In-house F-term (reference) 5F038 AR21 AV02 AV06 AV13 DF03 EZ20

Claims (3)

[Claims] A first resistor group including a plurality of resistors connected in series to each other; and a second resistor group including a plurality of resistors connected in series to each other. And a plurality of first conductivity type transistors each of which is connected to both ends of each of the resistors constituting the first resistor group so as to be short-circuited individually in accordance with the input digital signal. A first switchable composite resistance value of the first resistor group.
A switch circuit, and a plurality of second conductivity type transistors arranged corresponding to the number of bits of the input digital signal and having both ends of the resistors constituting the second resistor group individually coupled so as to be short-circuited. And a second resistor group capable of switching the combined resistance value of the second resistor group according to the input digital signal.
A trimming circuit comprising a switch circuit. 2. In the first resistor group and the second resistor group, when the value of the resistor corresponding to the least significant bit is 1R, the value of the resistor corresponding to the n-th bit is 2 ⁿ R. The trimming circuit according to claim 1, wherein 3. A resistor group provided between an output terminal of an operational amplifier and ground and having a plurality of resistors connected in series with each other; a decoder for decoding an input digital signal; and an output of the decoder. A selection circuit capable of selecting a series connection node in the resistor group based on a signal, wherein a first circuit connected in parallel to a resistor on one end side in the resistor group is provided.
A conductive type transistor, and a second resistor connected in parallel to the resistor at the other end of the resistor group.
A transistor of a conductivity type, wherein data of the same bit in the digital signal is coupled so as to be commonly input to a gate electrode of the first conductivity type transistor and a gate electrode of the second conductivity type transistor. Trimming circuit.