JP2000323585A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To operate at a higher voltage than drain withstanding voltages of both p- and n-channel MOS transistors by forming four or more second conductivity type diffused layers on a first conductivity type semiconductor substrate and forming first conductivity type diffused layers in at least two second conductivity type diffused layers. SOLUTION: In a first p-well 18 surface first and second n-type diffused layers 35, 36 are formed, and a gate electrode 51 is formed on between both through a gate oxide film, thus forming an n-channel MOS transistor 4. In a second p-well 19 third and fourth n-type diffused layers 37, 38 are formed and in a third p-well 20 fifth and sixth n-type diffused layers 39, 40 are formed to constitute n-channel MOS transistors 5, 6. Thus the cascade connection can be made also at the n-channel MOS transistors 4, 5, 6 and an IC can be operated at a higher voltage than the drain withstanding voltage of each transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a complementary MOS device, and more particularly to a P-channel M-type semiconductor device.
The present invention relates to a semiconductor device which can operate at a voltage higher than the drain withstand voltage of both an OS transistor and an N-channel MOS transistor.

[0002]

2. Description of the Related Art FIG. 3 is a sectional view showing a conventional semiconductor device.

This semiconductor device is a complementary MOS device (CMOS). The semiconductor device is an N-type silicon substrate 1
The first to fifth LOCOS oxide films 105 to 109 are formed on the surface of the N-type silicon substrate 111. A silicon substrate 111 between a region under the first LOCOS oxide film 105 and a region under the third LOCOS oxide film 107
A P-well (P-type diffusion layer) 114 is formed on the surface.

A first LOCOS oxide film 105 and a second L
A well contact (P-type diffusion layer) 123 is formed between the OCOS oxide film 106 and the surface of the P well 114. The second LOCOS oxide film 106 and the third LO
An N-type source diffusion layer 135 and an N-type drain diffusion layer 136 are formed between the COS oxide film 107 and the surface of the P well 114.

The third LOCOS oxide film 107 and the fourth L
On the surface of the silicon substrate 111 between the OCOS oxide film 108, a P-type drain diffusion layer 126 and a P-type source diffusion layer 127 are formed. Fourth LOCOS oxide film 1
A substrate contact (N-type diffusion layer) 14 is provided on the surface of the silicon substrate 111 between the second substrate 08 and the fifth LOCOS oxide film 109.
2 are formed.

The source diffusion layer 135 and the drain diffusion layer 1
The gate electrode 1 is located between the gate electrodes 36 via a gate oxide film.
51 are formed, and the gate electrode 151, the source diffusion layer 135 and the drain diffusion layer 136 form an N-channel M
The OS transistor 104 is configured. A gate electrode 156 is formed between the source diffusion layer 127 and the drain diffusion layer 126 via a gate oxide film. The P-channel MOS transistor is formed by the gate electrode 156, the source diffusion layer 127 and the drain diffusion layer 126. 1
03 is configured.

The gate electrodes 151, 156 and LOCOS
On the oxide films 105 to 109, an interlayer insulating film 113 is formed.
Contact holes located on 3,135,136,126,127,142 are formed. In these contact holes and on the interlayer insulating film 113, the metal wiring 11 is formed.
7 are formed, and the metal wiring 117 is electrically connected to the diffusion layer. An insulating film 119 is formed on the metal wiring 117.

[0008]

In the above-mentioned conventional CMOS, when an IC having a high withstand voltage is formed, the IC is operated at a higher voltage than the lower drain withstand voltage of each of the P-channel MOS transistor and the N-channel MOS transistor.
Can not work. Therefore, a transistor having a drain withstand voltage higher than the operating voltage of the IC must be designed. However, forming a transistor having a high drain withstand voltage (high withstand voltage transistor) and a normal power supply unit on the same substrate requires a complicated process and increases the cost.

On the other hand, in a CMOS structure using a well diffusion layer having a polarity opposite to that of a normal silicon substrate, a transistor having a breakdown voltage higher than the drain breakdown voltage of each transistor is formed by so-called cascade connection of transistors according to the well polarity. (Improving the apparent breakdown voltage) is also conceivable. However, this cascade connection method is generally applicable to only one of a P-channel MOS transistor and an N-channel MOS transistor. In this way, cascade connection can be applied to only one polarity, so it is necessary to make a high breakdown voltage transistor with the opposite polarity, and as a result,
As in the case described above, a complicated process is required and the cost is increased.

The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor which can operate at a voltage higher than the drain withstand voltage of both a P-channel MOS transistor and an N-channel MOS transistor. It is to provide a device.

[0011]

In order to solve the above problems, a semiconductor device according to the present invention comprises a semiconductor substrate of a first conductivity type, and four or more second conductivity type semiconductor substrates formed on the semiconductor substrate of the first conductivity type. A first conductivity type diffusion layer formed in each of at least two of the four or more second conductivity type diffusion layers, and the one first conductivity type diffusion layer. A second conductivity type transistor formed in the conductivity type diffusion layer, the second conductivity type transistor being cascaded in a plurality of stages, and the at least two of the four or more second conductivity type diffusion layers. A first conductivity type transistor formed in each second conductivity type diffusion layer other than the second conductivity type diffusion layer, the first conductivity type transistor being cascaded in a plurality of stages; Second conductive cascaded in stages A transistor, a first conductivity type transistor connected in cascade to said plurality of stages, from C
A MOS is formed.

In the above semiconductor device, four or more second conductivity type diffusion layers are formed on the first conductivity type semiconductor substrate, and one of the first conductivity type diffusion layers is provided in at least two of the second conductivity type diffusion layers. By forming the diffusion layer, the first conductivity type semiconductor substrate and the first conductivity type diffusion layer are insulated from each other by the second conductivity type diffusion layer. Therefore, a cascade connection can be made on the side of the second conductivity type transistor. Thus, the IC can be operated at a voltage higher than the drain withstand voltage of each transistor, and the apparent withstand voltage can be improved.

A semiconductor device according to the present invention is a CMOS having a first conductivity type transistor cascaded in a plurality of stages and a second conductivity type transistor cascaded in a plurality of stages. Semiconductor substrate, four or more second conductivity type diffusion layers formed on the first conductivity type semiconductor substrate, and at least two second conductivity type diffusion layers of the four or more second conductivity type diffusion layers One first conductivity type diffusion layer formed in the layer, first and second second conductivity type diffusion layers formed in the one first conductivity type diffusion layer, and the first and second diffusion layers A gate electrode formed between the second conductive type diffusion layers via a gate insulating film, and the at least two second conductive type diffusion layers of the four or more second conductive type diffusion layers Of the first and second layers formed in the respective second conductivity type diffusion layers. A first conductivity type diffusion layer, characterized by comprising, a gate electrode formed through a gate insulating film on a mutual of the first and second first-conductivity-type diffusion layer.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is an equivalent circuit diagram showing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG.

As shown in FIG. 1, this semiconductor device has a C
It has a MOS structure, and P-channel MOS transistors 1 to 3 are cascaded in three stages, and N-channel MOS transistors 4 to 6 are cascaded in three stages.

As shown in FIG. 2, the semiconductor device has a P-type silicon substrate 11, and first to sixth N-wells (N-type diffusion layers) 14 to 1 are formed on the surface of the P-type silicon substrate 11.
6, 13a to 13c are formed. A first P well (P type diffusion layer) 18 is formed in the fourth N well 13a, and a second P well (P type diffusion layer) 19 is formed in the fifth N well 13b. A third P-well (P-type diffusion layer) 20 is formed in the sixth N-well 13c.

The first and second P-wells 18 have first and second
N-type diffusion layer (source diffusion layer and drain diffusion layer) 3
5, 36 are formed. A gate electrode 51 is formed between the first and second N-type diffusion layers 35 and 36 via a gate oxide film (not shown).
The first and second N-type diffusion layers 35 and 36 constitute an N-channel MOS transistor 4. Also, the first P
A first P-type diffusion layer (well contact) 23 is formed in the well 18 and near the first N-type diffusion layer 35. A substrate contact (P-type diffusion layer) 22 is formed on the P-type silicon substrate 11.

In the second P well 19, third and fourth N-type diffusion layers (source diffusion layer and drain diffusion layer) 37,
38 are formed. Third and fourth N-type diffusion layers 3
A gate electrode 52 is formed between the gate electrodes 7 and 38 via a gate oxide film (not shown). The gate electrode 52 and the third and fourth N-type diffusion layers 37 and 38 form an N-channel MOS transistor. 5 are configured. Further, a second P-type diffusion layer (well contact) 24 is formed in the second P-well 19 and near the third N-type diffusion layer 37.

In the third P well 20, fifth and sixth N-type diffusion layers (source diffusion layer and drain diffusion layer) 39,
40 are formed. Fifth and sixth N-type diffusion layers 3
A gate electrode 53 is formed between the gate electrodes 9 and 40 via a gate oxide film (not shown), and an N-channel MOS transistor is formed by the gate electrode 53 and the fifth and sixth N-type diffusion layers 39 and 40. 6 are configured. Further, a third P-type diffusion layer (well contact) 25 is formed in the third P-well 20 and near the fifth N-type diffusion layer 39.

In the fourth N well 13a, a seventh N type diffusion layer (well contact) 61 is formed.
In the N well 13b, an eighth N type diffusion layer (well contact) 62 is formed, and the sixth N well 13c is formed.
A ninth N-type diffusion layer (well contact) 63 is formed therein.

In the first N well 14, fourth and fifth P-type diffusion layers (drain diffusion layer and source diffusion layer) 26,
27 are formed. Fourth and fifth P-type diffusion layers 2
A gate electrode 56 is formed between the gate electrodes 6 and 27 via a gate oxide film (not shown), and an N-channel MOS transistor is formed by the gate electrode 56 and the fourth and fifth P-type diffusion layers 26 and 27. 3 are configured. Further, an eighth N-type diffusion layer (well contact) 42 is formed in the first N-well 14 and near the fifth P-type diffusion layer 27.

In the second N well 15, sixth and seventh P-type diffusion layers (drain diffusion layer and source diffusion layer) 28,
29 are formed. Sixth and seventh P-type diffusion layers 2
A gate electrode 55 is formed between the gate electrodes 8 and 29 via a gate oxide film (not shown), and an N-channel MOS transistor is formed by the gate electrode 55 and the sixth and seventh P-type diffusion layers 28 and 29. 2 are configured. A ninth N-type diffusion layer (well contact) 43 is formed in the second N-well 15 and in the vicinity of the seventh P-type diffusion layer 29.

In the third N-well 16, eighth and ninth P-type diffusion layers (drain diffusion layer and source diffusion layer) 30,
31 are formed. Eighth and ninth P-type diffusion layers 3
A gate electrode 54 is formed between the gate electrodes 0 and 31 via a gate oxide film (not shown), and an N-channel MOS transistor is formed by the gate electrode 54 and the eighth and ninth P-type diffusion layers 30 and 31. 1 is configured. Further, a tenth N-type diffusion layer (well contact) 44 is formed in the third N-well 16 and near the ninth P-type diffusion layer 31.

Between the diffusion layers 22 and 23, the diffusion layers 23 and
35, the diffusion layers 36 and 61, the diffusion layer 6
1 and 24, between the diffusion layers 24 and 37, between the diffusion layers 38 and 62, between the diffusion layers 62 and 25, between the diffusion layers 25 and 39, and between the diffusion layers 40 and 63. Between the diffusion layers 63 and 26, between the diffusion layers 27 and 42,
Between the diffusion layers 42 and 28, between the diffusion layers 29 and 43, between the diffusion layers 43 and 30, and between the diffusion layers 31 and 4.
The surface of each silicon substrate 11 between
A COS oxide film (not shown) is formed.

The gate electrodes 51 to 56 are electrically connected to each other by a wiring 8. Substrate contact 22, first
The P-well contact 23 and the first N-type diffusion layer 35 are electrically connected to Vss (GND) by wiring. The second and third N-type diffusion layers 36 and 37 and the second P well contact 24 are electrically connected to each other by wiring. Fourth and fifth N-type diffusion layers 38,
The 39 and the third P well contact 25 are electrically connected to each other by wiring. The sixth N-type diffusion layer 40 and the fourth P-type diffusion layer 26 are electrically connected to each other by the wiring 9.

The fifth and sixth P-type diffusion layers 27 and 28 and the first N-well contact 42 are electrically connected to each other by wiring. Seventh and eighth P-type diffusion layers 2
The 9, 30 and the second N-well contact 43 are electrically connected to each other by wiring. The ninth P-type diffusion layer 31 and the third N-well contact 44 are electrically connected to Vdd (power supply) by wiring.

Seventh to ninth N-type diffusion layers 61, 62, 63
Are electrically connected to the respective N-type drain diffusion layers 36, 38, and 40, or are connected to V _DD (power supply). According to the above-described embodiment, the P-type silicon substrate 11 and the first to third P-wells 1 are formed by forming the fourth to sixth N-wells 13a to 13c on the P-type silicon substrate 11.
8 to 20 are insulated. Therefore, the N-channel type M
The cascade connection can also be made on the side of the OS transistors 4, 5, and 6. That is, in the prior art, only the P-channel type MOS transistors 1, 2, 3 could be connected in cascade, but in the present embodiment, the N-channel type MOS transistors 4, 5, 6 can also be connected in cascade. You can make a connection. This allows the IC to be driven at a voltage higher than the drain breakdown voltage of each of the transistors 1 to 6.
Can be operated, and the apparent withstand voltage can be improved. For example, when the drain withstand voltage of each transistor is 15 V, the IC can be operated at a voltage close to 45 V by performing a three-stage cascade connection.

The present invention is not limited to the above embodiment, but can be implemented with various modifications.

[0030]

As described above, according to the present invention, four or more second-conductivity-type diffusion layers are formed on a first-conductivity-type semiconductor substrate, and at least two of the second-conductivity-type diffusion layers are respectively formed. One diffusion layer of the first conductivity type is formed therein. Therefore, it is possible to provide a semiconductor device capable of operating at a voltage higher than the drain withstand voltage of both the P-channel MOS transistor and the N-channel MOS transistor.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view of the semiconductor device shown in FIG. 1;

FIG. 3 is a cross-sectional view illustrating a conventional semiconductor device.

[Explanation of symbols]

1-3 P-channel type MOS transistor 4-6 N-channel type MOS transistor 8,9 Wiring 11 P-type silicon substrate 13a-13c Fourth-sixth N-well (N-type diffusion layer) 14-16 First-third N-well (N-type diffusion layer) 18-20 First to third P-well (P-type diffusion layer) 22 Substrate contact (P-type diffusion layer) 23 First P-type diffusion layer (Well contact) 24 Second P-type diffusion layer (well contact) 25 Third P-type diffusion layer (Well contact) 26 Fourth P-type diffusion layer (Drain diffusion layer) 27 Fifth P-type diffusion layer (Source diffusion layer) 28 Sixth P-type diffusion layer (drain diffusion layer) 29 seventh P-type diffusion layer (source diffusion layer) 30 eighth P-type diffusion layer (drain diffusion layer) 31 ninth P-type diffusion layer (source diffusion layer) 35 First N-type diffusion layer (source extension) Layer) 36 Second N-type diffusion layer (drain diffusion layer) 37 Third N-type diffusion layer (source diffusion layer) 38 Fourth N-type diffusion layer (drain diffusion layer) 39 Fifth N-type diffusion layer ( Source diffusion layer) 40 Sixth N-type diffusion layer (drain diffusion layer) 42 to 44 Tenth to twelfth N-type diffusion layer (well contact) 51 to 56 Gate electrode 61 to 63 Seventh to ninth N-type Diffusion layer (well contact) 103 P-channel MOS transistor 104 N-channel MOS transistor 105 to 109 First to fifth LOCOS oxide films 111 N-type silicon substrate 113 Interlayer insulating film 114 P-well (P-type diffusion layer) 117 Metal wiring 119 Insulating film 123 Well contact (P-type diffusion layer) 126 P-type drain diffusion layer 127 P-type source diffusion layer 135 N-type source diffusion layer 136 N Drain diffusion layer 142 substrate contact (N-type diffusion layer) 151,15
6 Gate electrode

Claims (2)

[Claims] A first conductivity type semiconductor substrate; and four or more second conductivity type semiconductor substrates formed on the first conductivity type semiconductor substrate.
A conductivity type diffusion layer; and at least two of the four or more second conductivity type diffusion layers.
A first conductivity type diffusion layer formed in each of the two second conductivity type diffusion layers; and a second conductivity type transistor formed in the one first conductivity type diffusion layer, wherein Cascade-connected second conductivity type transistors, and formed in each second conductivity type diffusion layer other than the at least two second conductivity type diffusion layers of the four or more second conductivity type diffusion layers. A first conductivity type transistor, comprising: a first conductivity type transistor cascaded in a plurality of stages; a second conductivity type transistor cascaded in the plurality of stages; and a cascade connection in the plurality of stages. A semiconductor device, wherein a CMOS is formed from the first conductivity type transistor. 2. A transistor of a first conductivity type cascaded in a plurality of stages and a second transistor cascaded in a plurality of stages.
A first conductive type semiconductor substrate; and four or more second conductive types formed on the first conductive type semiconductor substrate.
A conductivity type diffusion layer; and at least two of the four or more second conductivity type diffusion layers.
One first conductivity type diffusion layer formed in one second conductivity type diffusion layer; first and second second conductivity type diffusion layers formed in the one first conductivity type diffusion layer; A gate electrode formed between the first and second second conductivity type diffusion layers with a gate insulating film interposed therebetween; and a gate electrode of the at least two of the four or more second conductivity type diffusion layers. A first and second first conductivity type diffusion layer formed in each second conductivity type diffusion layer other than the two conductivity type diffusion layer; and a space between the first and second first conductivity type diffusion layers. And a gate electrode formed thereon with a gate insulating film interposed therebetween.