JP2000323583A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device, wherein an on resistance can be controlled by a gate voltage, with an increased controllable range of the gate voltage. SOLUTION: An EDVDMOS 201 is provided with an enhancement region 211 and a depletion region 212, and comprises a substrate 111, a P-type impurity diffused layer 112, an N+ source contact region 113, a P+ source contact region 114, a surface insulating film 115, an electrode interconnection 116 made of, e.g. silicon, an intermediate insulating film 117, an electrode interconnection 118 made of, e.g. Al, and an N+ channel section diffused region 119. Furthermore, the substrate 111 will become a drain, the interconnection 116 a gate, and the interconnection 118 a source, respectively. When the gate voltage is 0 V or lower, the overall on-resistance is controlled by the enhancement region 211, while when the gate voltage exceeds 0 V, the total on-resistance is controlled by the region 211.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art In recent years, optical MOS relays have been used in a wide range of fields such as OA equipment, communication equipment, and measurement equipment. The output section of the optical MOS relay has VDMOS-FE
T (Vertical Diffusion Meta)
l Oxide Semiconductor-Fie
ld Effect Transistor).

[0003] VDMOS-FETs are also expected to serve as common noise countermeasure elements in measuring instruments. For this reason, the VDMOS-FET has been required to improve the element withstand voltage and to reduce the on-resistance as much as possible.

[0004]

However, in general, F
ET is the drain current _{I DS} - by the gate voltage _{V G} characteristics, an enhancement type (enhancement
type) and depletion type
type).

[0005] In an enhancement-type VDMOS-FET, when the gate voltage _{V G} than 0V, the on-resistance Rone = ∞, and becomes the drain current _I DS = 0A. On the other hand, when the depletion-type VDMOS-FET, when gradually changing the gate voltage _{V G} in the positive direction,
ON resistance RonD becomes constant at a certain potential, the drain current _{I DS} is the saturated (drain current _{I DS} =
Drain saturation current I _{DS S} ).

As described above, the enhancement type VDMO
For S-FET, the gate voltage V _G on the basis of 0V, but changing the plus direction is possible to control the on-resistance Rone, it is difficult to control the on-resistance Rone by changing the negative direction is there. Conversely, when the depletion-type VDMOS-FET, and the gate voltage _{V G} is changed in the negative direction relative to the 0V on-resistance R
Although it is possible to control onD, it is difficult to control the on-resistance RonD by changing it in the plus direction. That is, the enhancement type VDMOS-FET
And depletion type VDMOS-FET are both ON resistance Rone, the range of the gate voltage _{V G} for controlling the RonD limit.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has as its object to provide a semiconductor in which the on-resistance can be controlled by the gate voltage and the range of the controllable gate voltage is expanded. It is to provide a device.

[0008]

According to a first aspect of the present invention, there is provided a semiconductor device including an enhancement type transistor and a depletion type transistor, wherein the semiconductor device is formed in one chip. A semiconductor device is provided. According to such a configuration, it is possible to omit a wire bonding step for electrically connecting the enhancement type transistor and the depletion type transistor formed on different chips.

Further, when each transistor is formed on a separate chip, it is necessary to form a circuit that can be shared by both transistors on each chip. In this regard, according to the semiconductor device of the first aspect, it is possible to provide a region for forming a shared circuit, so that the active region in which each transistor is formed is smaller than when the transistor is formed on another chip. As a result, the breakdown voltage of each transistor can be improved.

[0010] As described in claim 2, it is also possible to apply a vertical diffusion MOS transistor as the enhancement type transistor and the depletion type transistor.

According to the third aspect, the source of the enhancement type transistor and the source of the depletion type transistor are shared, the drain of the enhancement type transistor and the drain of the depletion type transistor are shared, and the gate of the enhancement type transistor and the depletion type transistor are used. A semiconductor device is provided in which the gates of the transistors are shared. According to such a configuration, by applying a predetermined gate voltage to the gate, the on-resistance of each transistor changes. When the gate voltage swings in the negative direction, the change in the on-resistance of the depletion type transistor is mainly reflected in the change in the on-resistance of the entire semiconductor device. When the gate voltage swings in the plus direction, the enhancement is mainly performed. The on-resistance of the type transistor is reflected on the on-resistance of the entire semiconductor device.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
Preferred embodiments of the semiconductor device according to the present invention will be described in detail. In the following description and the accompanying drawings, components having substantially the same functions and configurations are denoted by the same reference numerals, and redundant description is omitted.

First, a general enhancement type VDM
OS-FET and depletion type VDMOS-FE
The configuration and operation of T will be described with reference to FIGS.

FIG. 1 shows a general enhancement type VD.
MOS-FET (hereinafter, referred to as “EVDMOS”) 1
1 shows a cross section of FIG. This EVDMOS 101
Represents a substrate 111, a P-type impurity diffusion region 112,⁺Saw
Contact area 113, P ⁺Source contact area 1
14, surface insulating film 115, electrode made of polysilicon or the like
Wiring 116, intermediate insulating film 117, and Al or the like
It is composed of electrode wiring 118. Here, the substrate 11
1 is a drain, electrode wiring 116 is a gate, electrode wiring 11
8 is the source.

In the EVDMOS 101, a threshold voltage Vt (>
If 0V) than the gate voltage _{V G} is applied, the drain (substrate 111) - occur source (predetermined resistance to electrode wiring 118) between (ON resistance Rone) is the drain - given between the source and the drain current _{I DS} Flows. If the threshold voltage Vt below the gate voltage V _G is applied to the gate, the drain current I _DS does not flow.

In the EVDMOS 101, by adjusting the impurity concentration of the P-type impurity diffusion region 112,
It is possible to obtain the on-resistance RonE corresponding to the value of the gate voltage _{V G,} but if the gate voltage _V G = 0V, resulting in a drain current _I DS = 0A. And EVD
In MOS 101, the gate voltage _{V G} swings in the negative direction, the on-resistance RonE and the drain current I
_DS is fixed (ON resistance RonE = ∞, drain current I _DS = 0 A), and cannot be controlled.

FIG. 2 shows a general depletion type VDM.
OS-FET (hereinafter referred to as “DVDMOS”) 10
2 shows a cross section of FIG. This DVDMOS102
Are a substrate 111, a P-type impurity diffusion region 112, an N ⁺ source contact region 113, and a P ⁺ source contact region 1.
14, a surface insulating film 115, an electrode wiring 116 made of polysilicon or the like, an intermediate insulating film 117, an electrode wiring 118 made of Al or the like, and an N ⁺ channel region diffusion region 119. Here, the substrate 111 is a drain, the electrode wiring 116 is a gate, and the electrode wiring 118 is a source. The DVDMOS 102 has a configuration different from the EVDMOS 101 only in the N ⁺ channel portion diffusion region 119.

[0018] In this DVDMOS102, by adjusting the impurity concentration of the ^{N +} channel unit diffusion region 119, the on-resistance corresponding to the value of the gate voltage _{V G} Rond
Although it is possible to obtain a and gradually changing the gate voltage V _G in the positive direction, becomes a certain potential on resistance RonD constant, the drain current I _DS is the saturated (drain current I _{DS =} drain Saturation current I _DSS ).
That is, in DVDMOS102, the gate voltage _{V G} swings in the positive direction, the on-resistance RonD and drain current _{I DS} is fixed respectively, becomes uncontrollable.

Here, the configuration and operation of an enhancement type + depletion type VDMOS-FET (hereinafter, referred to as “EDVDMOS”) 201 as a semiconductor device according to an embodiment of the present invention will be described with reference to FIG.

FIG. 3 shows a cross section of the EDVDMOS201.
It is something. This EDVDMOS201 is enhanced
The displacement area 211 and the depression area 212
Substrate 111, P-type impurity diffusion region 112, N⁺Seo
Source contact region 113, P⁺Source contact area
114, a surface insulating film 115, an electrode made of polysilicon or the like.
Electrode wiring 116, intermediate insulating film 117, electrode made of Al, etc.
Wiring 118 and N ⁺From channel region diffusion region 119
It is configured. The substrate 111 is a drain, an electrode
The wiring 116 is a gate, and the electrode wiring 118 is a source.
FIG. 3 shows a cell composed of EDVDMOS201.
Although only one is described, multiple cells can be
It may be provided.

The enhancement region 211 corresponds to the E
The configuration is substantially the same as that of the VDMOS 101, and the depression area 212 is substantially the same as that of the DVDMOS 102 described above. The enhancement region 211 and the depression region 212 are EVDMOS
101 and the DVDMOS 102 are connected in parallel. In other words, EVDMOS 101 and DVDMO
The source, drain, and gate of S102 are commonly used.

Next, the EDV according to the embodiment of the present invention will be described.
The operation of the DMOS 201 will be described. The threshold voltage of the enhancement region 211 is Vte, and the threshold voltage of the depletion region 212 is Vtd. Then, each threshold voltage Vte, Vtd is
It is assumed that Expression (1) is satisfied.

Vtd <0V <Vte (1)

[0024] If the gate voltage _{V G} satisfies the formula (2),
Enhancement area 211, depression area 21
2 are both turned off, so that the EDVDMOS 201 as a whole has an on-resistance Ron = ∞ and a drain current I _DS =
It becomes 0A.

V _G <Vtd (2)

[0026] If the gate voltage _{V G} satisfies the formula (3),
The enhancement region 211 is turned off, and only the depression region 212 is turned on.

Vtd ≦ V _G <Vte (3)

Under the condition of equation (3), the gate voltage V is adjusted by adjusting the impurity concentration of the N ⁺ channel diffusion region 119 in the depletion region 212 for each cell.
The threshold voltage Vtd of the depletion region 212 can be controlled by _G (<0 V), and as a result, the ON resistance Ron of the entire EDVDMOS 201 can be controlled.

[0029] If the gate voltage _{V G} satisfies the formula (4),
Enhancement area 211, depression area 21
2 are both turned on.

[0030] Vte ≦ _V G ··· (4)

Under the condition of equation (4), for example, when the gate voltage V _G > 0 V, the on-resistance RonD in the depletion region 212 is fixed, and the depletion region 2
12, the drain current _IDS is saturated. However, by the impurity concentration of the P-type impurity diffusion regions 112 in the enhancement region 211 is adjusted for each cell, the cell which is turned with increasing gate voltage V _G is adjusted to increase, the gate voltage V _G> 0V
Thus, the ON resistance RonE in the enhancement region 211 can be controlled separately from the depletion region 212 where the ON resistance RonD is fixed. Thus, by raising the gate voltage _V G (> 0V), it is possible to EDVDMOS201 overall on-resistance Ron can be controlled to decrease.

Hereinafter, the EDV according to the embodiment of the present invention will be described.
The operation of the DMOS 201 will be described more specifically with reference to FIG.

[0033] the gate (electrode wiring 116), when the gate voltage _{V G} below the threshold voltage Vtd is applied _(V G <Vtd), in the enhancement region 211, the substrate 111 and the P-type impurity diffusion regions 112 PN
Since the junction, the drain current _{I DS} does not flow in the enhancement region 211. Depletion area 2
At 12, the N ⁺ channel diffusion region 119 formed immediately below the gate (electrode wiring 116) is inverted to P-type, so that the substrate 111, the P-type impurity diffusion region 112,
11 and the N ⁺ channel diffusion region 119 are PN junctions, so that the drain current I
_DS does not flow. Therefore, the ON resistance Ron of the EDVDMOS 201 as a whole becomes ∞, and the drain current I
_DS becomes 0A.

[0034] the gate (electrode wiring 116), the threshold voltage Vtd above, when the gate voltage _{V G} below the threshold voltage Vte is applied (Vtd ≦ _V G <V
te), in the enhancement region 211, the substrate 1
11 and the P-type impurity diffusion region 112 form a PN junction, so that the drain current I _DS
Does not flow. On the other hand, in the depletion region 212, the drain current _IDS is transferred from the substrate 111 through the N ⁺ channel portion diffusion region 119 to the N ⁺ source contact region 1
13 will flow. In other words, this time the drain current _{I DS,} based on the on-resistance RonD generated in depletion region 212, will flow through the depletion region 212. The change in the on-resistance RonD in the depletion region 212 is caused by the EDVD
This is reflected on the ON resistance Ron of the MOS 201 as a whole.

The gate against (electrode wiring 116), if the threshold voltage Vte more gate voltage _{V G} is applied (Vte ≦ _V G), in the enhancement region 211, P-type impurity diffusion region 11 which is located immediately below the gate
2 is inverted to N-type, the drain current _IDS is transferred from the substrate 111 through the surface layer 221 of the P-type impurity diffusion region 112 to the N ⁺ source contact region 113.
Will flow to In addition, the depletion area 212
, The drain current I _DS is changed from the substrate 111 to N ⁺
It flows to the N ⁺ source contact region 113 via the channel portion diffusion region 119. In other words, this time the drain current _{I DS,} the on-resistance RonE and depletion region 212 generated in the enhancement region 211
Flows through the enhancement region 211 and the depletion region 212 based on the on-resistance RonD generated in step (1). And the enhancement area 21
1 and the on-resistance RonD in the depletion region 212 are EDVDMOS20.
1 as the whole on-resistance Ron.

It should be noted, EDVD under conditions of Vte ≦ _{V G}
The ON resistance Ron of the MOS 201 as a whole is Vtd ≦
Compared to on-resistance Ron under conditions of V _G <Vte, minute on resistance RonE in the enhancement region 211, it will be reduced.

[0037] As described above, according to EDVDMOS201 according to an embodiment of the present invention, the gate voltage _{V G} is zero
For less V, the total on-resistance Ron is controlled by the depletion region 212, the gate voltage _{V G} is 0V
Is exceeded, the entire on-resistance Ron is controlled by the enhancement region 211. Therefore, the EDVDMOS2 according to the embodiment of the present invention is
01 is possible to control the on-resistance Ron by the gate voltage V _G of the positive and negative directions relative to the 0V.

Although the preferred embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to these embodiments. It is clear that a person skilled in the art can conceive various changes or modifications within the scope of the technical idea described in the claims, and those modifications naturally fall within the technical scope of the present invention. It is understood to belong.

For example, in the present embodiment, an EDVDMOS having an N-channel enhancement region 211 and an N-channel depletion region 212 is provided.
Although the present invention has been described with reference to 201, the present invention is not limited to this, and can be applied to a P-channel type configuration.

[0040]

As described above, according to the semiconductor device of the present invention, the range of the gate voltage used for controlling the on-resistance can be expanded.

In the semiconductor device according to the present invention, since the enhancement type transistor and the depletion type transistor are formed in one chip, for example, the chip in which the enhancement type transistor is formed and the depletion type transistor are formed. When connecting chips by wire bonding,
Since the wiring process is omitted, the manufacturing time can be reduced, the quality can be improved, and the like.

Further, since the enhancement type transistor and the depletion type transistor are formed in one chip, by providing a shared region for both transistors, the active region where each transistor is formed can be expanded. Therefore, the on-resistance of each transistor can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a general configuration of an enhancement transistor.

FIG. 2 is a cross-sectional view illustrating a general configuration of a depletion-type transistor.

FIG. 3 is a cross-sectional view showing a configuration of an enhancement type + depletion type VDMOS-FET according to the embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 101 Enhancement type VDMOS-FET 102 Depletion type VDMOS-FET 111 Substrate 112 P-type impurity diffusion region 113 N ⁺ source contact region 114 P ⁺ source contact region 115 surface insulating film 116 electrode wiring 117 intermediate insulating film 118 electrode wiring 119 N ⁺ channel Partial diffusion region 201 Enhancement type + depletion type VD
MOS-FET 211 Enhancement region 212 Depletion region 221 Surface layer

Claims (3)

[Claims] 1. A semiconductor device comprising an enhancement type transistor and a depletion type transistor, wherein the semiconductor device is formed in one chip. 2. The device according to claim 1, wherein said enhancement type transistor and said depletion type transistor are vertical diffusion MOS transistors.
2. The semiconductor device according to claim 1, wherein the semiconductor device is a transistor. 3. The source of the enhancement transistor and the source of the depletion transistor, the drain of the enhancement transistor and the drain of the depletion transistor are shared, and the gate of the enhancement transistor and the depletion transistor. 3. The semiconductor device according to claim 1, wherein a gate of the type transistor is shared.