JP2000322319A - Security circuit for semiconductor storage device and security system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a security circuit for a semiconductor storage device and a security system having a security function which is further strong and difficult to clarify. SOLUTION: An arithmetic circuit 20 performs a prescribed arithmetic operation based on an uncertain value generated by an uncertain value generating circuit 16. In an outside system which performs access to a semiconductor storage device, the same arithmetic operation is executed in the same way as the arithmetic circuit 20 based on the uncertain value, and the arithmetic result is inputted to an interface circuit 3 as an input password. When a specific password signal 21 indicating the arithmetic result is made coincident with a password signal 12 indicating an input password by the arithmetic circuit 20, a security release signal 14 is outputted from a comparator circuit 13. At the time of receiving the security release signal 14 from the comparator circuit 13, a bus control circuit 6 activates a memory space 9 after confirming that a security release condition is fulfilled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a security circuit and a security system for a semiconductor memory device which can prevent unauthorized or erroneous access to the semiconductor memory device.

[0002]

2. Description of the Related Art Data stored in a nonvolatile semiconductor memory device may contain data that is not desirable to be read or rewritten by a third party, such as information relating to personal privacy or information protected by copyright. is there. Also, EE
In a rewritable nonvolatile semiconductor memory device such as a PROM (electrically erasable and readable read-only memory), erroneous data rewriting can occur due to noise of the system or the nonvolatile semiconductor memory device itself. In order to protect the memory contents from accessing these unexpected memory contents, there is a nonvolatile semiconductor memory device in which a security circuit is incorporated.

FIG. 5 is a schematic block diagram illustrating a security operation of a nonvolatile semiconductor memory device in which the above security circuit is incorporated.

In FIG. 5, reference numeral 503 denotes an external system.
(Not shown), and an interface circuit 506 connected to an external system via a data input / output bus 502. An address signal 504 from the interface circuit 503 is input to the interface circuit 506. A bus control circuit connected to the bus control circuit 506 via a data input / output bus 505, an address signal 507 from the bus control circuit 506 is input to the bus control circuit 506, and a memory space connected to the bus control circuit 506 via the data input / output bus 508 It is. The interface section 503 and the bus control circuit 506 constitute a security circuit.

Next, a read security operation of the nonvolatile semiconductor memory device will be described. A read command and a read address are input to the nonvolatile semiconductor memory device by an input signal 501. Then, the interface circuit 503 analyzes the input signal 501 and
When a read operation is requested, a read address is transmitted to the bus control circuit 506 by an address signal 504, and data to be output is received from the bus control circuit 506 via the data input / output bus 505. At this time, the bus control circuit 506 determines whether or not the address indicated by the transmitted address signal 504 is in the memory space where the read operation is permitted. Then, the bus control circuit 50
6 determines that the address indicated by the address signal 504 is located in a memory space where reading is not permitted,
Data input / output bus 505 and read address signal 507
Perform some operation on the, output incorrect data,
No normal read operation is performed. On the other hand, address signal 5
When the bus control circuit 506 determines that the address indicated by the address 04 is located in the memory space where reading is permitted, the bus control circuit 506 correctly issues an address signal 507 and the address signal 507 is written at the designated address in the memory space 509. Data is read out via the data input / output bus 508,
Output correctly via the data input / output bus 505. Then, the interface circuit 5 receiving the correct output
03 outputs the received correct data to a data input / output bus 502 connected to an external system.

As means for outputting incorrect data, means for not generating an address signal other than means for outputting a fixed value to a data input / output signal (Japanese Patent Laid-Open No. 59-1).
There are means for disturbing the address signal (see JP-A-63-225839) and means for disturbing the received data (see JP-A-6-250929).

FIG. 6 is a schematic block diagram of a nonvolatile semiconductor memory device in which a security circuit using password input as security releasing means is incorporated. 6, an input circuit 603 receives an input signal 601 from an external system (not shown) and is connected to an external system via a data input / output bus 602.
An address signal 604 from the interface circuit 603 is input to the interface circuit 606.
03, a bus control circuit connected via a data input / output bus 605; 609, an address signal 607 from the bus control circuit 606 is input and connected to the bus control circuit 606 via a data input / output bus 608. A memory space; 610, a unique password storage circuit for outputting a unique password signal 611; 613, a unique password signal 611 from the unique password storage circuit 610; and a password signal 61 from the interface circuit 603.
2 is a comparison circuit that receives the security release signal 2 and outputs a security release signal 614 to the bus control circuit 606. The interface circuit 603, the bus control circuit 606, the unique password storage circuit 610, and the comparison circuit 613 constitute a security circuit.

Next, the security release operation of the nonvolatile semiconductor memory device having the above configuration will be described. When a “password input command” is externally input to the interface circuit 603 by the input signal 601, the nonvolatile semiconductor memory device receives the “input password” from the data input / output bus 602. Then, the interface circuit 60
3 sends a password signal 612 indicating “input password” to the comparison circuit 613. The unique password storage circuit 610 stores the “unique password” and sends a unique password signal 611 representing the “unique password” to the comparison circuit 613. Then, the comparison circuit 613
By comparing the unique password signal 611 representing the “unique password” with the password signal 612 representing the “input password”, the unique password signal 611 and the password signal 6 are compared.
12 and the security release signal 614
Issue Then, when the security release signal 614 is issued, the bus control circuit 606 normally performs subsequent access to the protected memory space.

[0009]

However, in the method of using the input of the "unique password" for the security release condition of the nonvolatile semiconductor memory device, the "unique password" and the "password input command" are determined by probing the input signal. It has the disadvantage of being easily clarified.
In addition, the provision of a dedicated command for security control has a drawback in that it is a great clue to clarifying the method of the release operation by analyzing the input signal.

SUMMARY OF THE INVENTION An object of the present invention is to provide a security circuit and a security system for a semiconductor memory device which have a stronger and harder to understand security function.

[0011]

In order to achieve the above object, a security circuit for a semiconductor memory device according to claim 1 is provided.
A security circuit for a semiconductor memory device that activates a predetermined memory space according to a security setting condition while activating the predetermined memory space according to a security release condition generates one or two or more indefinite values. An indefinite value generation unit that outputs a value, and an operation unit that performs a predetermined operation based on the indefinite value from the indefinite value generation unit,
A password input unit to which an input password is input from the outside, a password determination unit that determines whether a calculation result of the calculation unit matches the input password input to the password input unit, and a password determination unit. A memory activating unit that activates the predetermined memory space when it is determined that the operation result of the operation unit matches the input password, that the security release condition is satisfied.

According to the security circuit for a semiconductor memory device of the first aspect, when the predetermined memory space is activated from a state of being inactivated by a security setting condition, the external system accessing the semiconductor memory device includes: One or more indefinite values generated by the indefinite value generation unit are read out, and the same predetermined operation as that of the operation unit is performed based on the indefinite values. Next, the calculation result calculated by the external system is input to the password input unit as an input password. Then, the password determination unit determines whether or not the password determination unit matches the calculation result of the calculation unit with the input password. At this time, since the input password input from the external system is obtained by performing the same predetermined calculation as that of the arithmetic unit based on the indefinite value, it matches the arithmetic result of the arithmetic unit. Therefore, the password determination unit determines that the calculation result of the calculation unit matches the input password. Then, when the password determination unit determines that the calculation result of the calculation unit matches the input password, the memory activation unit determines that the security release condition is satisfied and activates the predetermined memory space.
In this way, the input value for releasing security, that is, the calculation result of the calculation unit, can be changed by changing the indefinite value by the indefinite value generation unit every time security is released. Therefore, unauthorized access to the protected memory space becomes extremely difficult, and a more robust and difficult-to-understand semiconductor memory device having a security function can be realized.

According to a second aspect of the present invention, a security circuit for a semiconductor memory device inactivates a predetermined memory space according to a security setting condition and activates the predetermined memory space according to a security release condition. A circuit for generating one or more indefinite values in the circuit, outputting an indefinite value, an indefinite value generation unit, an operation unit for performing a predetermined operation based on the indefinite value from the indefinite value generation unit, A password input command input unit into which a password input command is input; and a password input command determination unit that determines whether the calculation result of the calculation unit matches the password input command input to the password input command input unit. The password input command discriminating unit is configured to calculate the operation result of the operation unit and the password input command When it is determined that matches, a password input unit that inputs an input password, a password determination unit that determines whether or not the input password input to the password input unit matches a preset unique password, When the password determination unit determines that the input password and the unique password match,
A memory activating unit that activates the predetermined memory space on condition that the security release condition is satisfied.

According to the security circuit for a semiconductor memory device of the second aspect, when the predetermined memory space is activated from a state of being inactivated by a security setting condition, the external system accessing the semiconductor memory device includes: One or more indefinite values generated by the indefinite value generation unit are read out, and the same predetermined operation as that of the operation unit is performed based on the indefinite values. Next, the calculation result calculated by the external system is input to the password input command input unit as a password input command. Then, the password input command determination unit determines whether the calculation result of the calculation unit matches the password input command. At this time, since the password input command input from the external system is obtained by performing the same predetermined calculation as that of the arithmetic unit based on the indefinite value, the password input command coincides with the arithmetic result of the arithmetic unit. Therefore,
The password input command determination unit determines that the calculation result of the calculation unit matches the password input command. Then, when the password input command determining unit determines that the calculation result of the calculating unit matches the password input command, the password input unit is permitted to input the input password, and receives the input password ( (The same content as the unique password described later). When the password determining unit determines that the input password matches the preset unique password, the memory activating unit activates the predetermined memory space as satisfying the security release condition. . In this manner, the undefined value generated by the indefinite value generator changes every time security is released, thereby making it possible to change the password input command for inputting the input password for releasing security, that is, the calculation result of the calculation unit. . Therefore, unauthorized access to the protected memory space becomes extremely difficult, and a more robust and difficult-to-understand semiconductor memory device having a security function can be realized.

According to a third aspect of the present invention, there is provided a security circuit for a semiconductor memory device according to the first or second aspect, wherein the indefinite value generating section stores the generated indefinite value. Characterized by having a volatile memory cell.

According to the security circuit for a semiconductor memory device of the third aspect, by storing the non-volatile memory cell in which the indefinite value generated by the indefinite value generation section is rewritable, the indefinite value is cleared when the power is turned off. Since it is stored without being stored, the accumulated number of operations in the semiconductor memory device can be used as an indefinite value, or a pseudo-random number generated by a mixed congruential method can be used as an indefinite value. It is effective for

According to a fourth aspect of the present invention, a security circuit for a semiconductor memory device inactivates a predetermined memory space according to a security setting condition and activates the predetermined memory space according to a security release condition. In the circuit, a numerical value input unit to which a numerical value is externally input, an operation unit that performs a predetermined operation based on the numerical value input to the numerical value input unit, a password input unit to which an input password is externally input, A password discriminating unit for discriminating whether or not the calculation result of the calculating unit matches the input password input to the password input unit; and the password discriminating unit matches the calculation result of the calculating unit with the input password. When it is determined that the security release condition is satisfied, the predetermined memory space is activated. It is characterized in that a re-activation unit.

According to the security circuit for a semiconductor memory device of the fourth aspect, when the predetermined memory space is activated from the inactive state according to the security setting condition, the numerical value is obtained from an external system accessing the semiconductor memory device. A numerical value is input to the input unit, and the arithmetic unit performs an operation based on the numerical value input to the numerical input unit. Next, the external system performs the same operation as the operation unit based on the numerical value, and uses the operation result as an input password,
Enter the password in the password input section. Then, the password determination unit determines whether or not the password determination unit matches the calculation result of the calculation unit with the input password. At this time, since the input password input from the external system is obtained by performing the same predetermined calculation as the calculation unit based on the numerical value input to the numerical value input unit, the calculation result of the calculation unit and Matches. Therefore, the password determination unit determines that the calculation result of the calculation unit matches the input password. Then, when the password determination unit determines that the calculation result of the calculation unit matches the input password, the memory activation unit determines that the security release condition is satisfied and activates the predetermined memory space. In this way,
By changing the numerical value input to the numerical value input unit every time security is released, it is possible to change the input password for releasing security, that is, the calculation result of the arithmetic unit. Therefore, unauthorized access to the protected memory space becomes extremely difficult, and a more robust and difficult-to-understand semiconductor memory device having a security function can be realized.

According to a fifth aspect of the present invention, a security circuit for a semiconductor memory device inactivates a predetermined memory space according to a security setting condition and activates the predetermined memory space according to a security release condition. A circuit for inputting a numerical value from the outside; a calculating unit for performing a predetermined operation based on the numerical value input to the numerical input unit; and a password input command input unit for receiving a password input command from the outside A password input command determining unit that determines whether a calculation result of the calculation unit matches the password input command input to the password input command input unit; and If it is determined that the calculation result matches the password input command, the input password is determined. A password input unit for inputting a password, a password discriminating unit for discriminating whether or not the input password inputted to the password input unit matches a preset unique password; and And a memory activating unit that activates the predetermined memory space when it is determined that the password and the unique password match, and determines that the security release condition is satisfied.

According to the security circuit for a semiconductor memory device of the present invention, when the predetermined memory space is activated from a state of being inactivated by a security setting condition, the numerical value is obtained from an external system accessing the semiconductor memory device. A numerical value is input to the input unit, and the arithmetic unit performs an operation based on the numerical value input to the numerical input unit. Next, the external system performs the same operation as the operation unit based on the numerical value, and inputs the operation result to the password input command input unit as a password input command. Then, the password input command determination unit determines whether the calculation result of the calculation unit matches the password input command. At this time, since the password input command input from the external system is obtained by performing the same predetermined calculation as that of the arithmetic unit based on the numerical value, it matches the arithmetic result of the arithmetic unit. Therefore, the password input command determination unit determines that the calculation result of the calculation unit matches the password input command. Then, when the password input command determining unit determines that the calculation result of the calculating unit matches the password input command, the password input unit is permitted to input the input password, and receives the input password ( (The same content as the unique password described later). When the password determining unit determines that the input password matches the preset unique password, the memory activating unit activates the predetermined memory space as satisfying the security release condition. . By changing the numerical value input to the numerical value input unit every time security is released, it is possible to change a password input command for inputting an input password for releasing security, that is, a calculation result of the arithmetic unit. Therefore, unauthorized access to the protected memory space becomes extremely difficult, and a more robust and difficult-to-understand semiconductor memory device having a security function can be realized.

According to a sixth aspect of the present invention, in the security circuit for a semiconductor memory device according to any one of the first, second, fourth, and fifth aspects, the arithmetic unit is set under a predetermined condition. A rewritable nonvolatile memory cell for storing a constant stored therein, and using a constant stored in the rewritable nonvolatile memory cell for calculation.

According to the security circuit for a semiconductor memory device of the sixth aspect, it is possible to easily change the operation content of the operation unit by rewriting the constant stored in the nonvolatile memory cell.

According to a seventh aspect of the present invention, in the security circuit for a semiconductor storage device according to the first or fourth aspect, the password discriminating unit is inputted to the password input unit and the operation result of the operation unit. When it is determined that the input password does not match, the arithmetic unit further performs an operation on the operation result to change the operation result.

According to the security circuit for a semiconductor storage device of the present invention, when the operation result of the operation unit does not match the input password, the operation result is further added to the operation result of the operation unit. Since the calculation result is changed,
By trying all combinations of the password input command and the input password, the security release condition can be prevented from being clarified.

According to a second aspect of the present invention, in the security circuit for a semiconductor memory device according to the second or fifth aspect, the password input command discriminating section is configured to determine a result of the operation by the operation section and the password input command input. When it is determined that the password input command does not match the password input command input to the unit, the operation unit further performs an operation on the operation result to change the operation result.

According to the security circuit for a semiconductor memory device of the present invention, when the operation result of the operation unit does not match the password input command, the operation result is further added to the operation result of the operation unit. Since the calculation result is changed, it is possible to prevent the security release condition from being clarified by trying all combinations of the password input command and the input password.

According to a ninth aspect of the present invention, there is provided a security circuit for a semiconductor memory device according to any one of the first, second, fourth, and fifth aspects, wherein a key address set under predetermined conditions is selected. Then, the operation unit adds another operation to the operation result to change the operation result.

According to the security circuit for a semiconductor storage device of the ninth aspect, the operation result is changed by further performing an operation on the operation result of the operation unit by selecting a key address that has no apparent relation to the security control. Therefore, it becomes difficult for a third party to understand the security release condition.

According to a tenth aspect of the present invention, there is provided a security circuit for a semiconductor storage device according to any one of the first to ninth aspects, wherein the rewritable nonvolatile memory stores an operation result of the operation unit. It is characterized by having a cell.

According to the security circuit for a semiconductor memory device of the tenth aspect, by storing the non-volatile memory cell in which the operation result of the operation unit is rewritable, the operation result is stored without being cleared when the power is turned off. Therefore, it is possible to change the operation content using the operation result next time, and it becomes difficult for a third party to clarify the security release condition.

Further, a security circuit for a semiconductor memory device according to claim 11 is the security circuit for a semiconductor memory device according to claim 9, wherein the key address is stored in a rewritable nonvolatile memory cell.

According to the security circuit for a semiconductor memory device of the eleventh aspect, by storing the key address in the rewritable nonvolatile memory cell, it is possible to change the key address every time security is released. Security can be more reliably prevented from being released.

The security circuit for a semiconductor memory device according to the twelfth aspect of the present invention is the security circuit for a semiconductor memory device according to the eleventh aspect, wherein the rewritable nonvolatile memory cell for storing the key address includes It is characterized in that redundant memory cells constituting a part thereof are used.

According to the security circuit for a semiconductor memory device of the twelfth aspect, the key address is stored in unused redundant memory cells among redundant memory cells constituting a part of the memory of the semiconductor memory device. Therefore, it is not necessary to provide a separate memory cell for storing the key address, and the cost can be reduced.

According to a thirteenth aspect of the present invention, in the security circuit for a semiconductor storage device according to the eleventh aspect, the rewritable nonvolatile memory cell for storing the key address is set under a predetermined condition. A memory cell assigned to the assigned address.

According to the security circuit for a semiconductor memory device of the thirteenth aspect, the key address is stored in a memory cell assigned to an address set under a predetermined condition in a memory of the semiconductor memory device. It is not necessary to provide a separate memory cell for storing the key address, and the cost can be reduced.

A security system according to a fourteenth aspect is a security system comprising the security circuit for a semiconductor memory device according to any one of the first to thirteenth aspects, and a plurality of semiconductor devices including the semiconductor memory device. At least one of the semiconductor devices has a security setting unit for deactivating a predetermined memory space of the semiconductor storage device, and the semiconductor storage device is provided with the memory activation unit of the security circuit for the semiconductor storage device. Wherein at least one of the semiconductor devices includes a security release unit having a configuration obtained by removing the memory activation unit from the security circuit for the semiconductor storage device.

According to the security system of the present invention, in the semiconductor device having the security release unit, when the security release condition of the security release unit is satisfied, the security release signal is transmitted from the security release unit to the semiconductor device. Output to the memory activation unit of the storage device. Then, the memory activation unit receiving the security release signal activates a predetermined memory space of the semiconductor memory device. Therefore,
It is possible to realize a security system having a security function that is more robust and difficult to understand.

According to a fifteenth aspect of the present invention, in the security system according to the fourteenth aspect, the semiconductor device having the security release section is plural, and the memory activating section of the semiconductor memory device is plural. A predetermined memory space is activated based on a security release signal from the security release unit of the semiconductor device.

According to the security system of the present invention, in each of the semiconductor devices having the security release unit, when the security release condition of the security release unit is satisfied, the security release signal of each semiconductor device is transmitted from the semiconductor release device to the semiconductor device. The data is output to the memory activation unit of the storage device. Then, the memory activating unit that has received the security release signal from each semiconductor storage device activates a predetermined memory space of the semiconductor storage device. For example, if all the semiconductor devices having the security release unit do not satisfy the security release condition,
By preventing the memory activation unit from activating the memory space of the semiconductor memory device, the security function can be further strengthened. When at least one of the semiconductor devices having the security release unit satisfies the security release condition, the memory activation unit may activate the memory space.

[0041]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a security circuit and a security system for a semiconductor memory device according to the present invention will be described in detail with reference to the illustrated embodiments.

(First Embodiment) FIG. 1 is a schematic block diagram showing a configuration of a nonvolatile semiconductor memory device using a security circuit for a semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, reference numeral 3 denotes an interface circuit which receives an input signal 1 from an external system (not shown) and is connected to the external system via a data input / output bus 2;
Is a bus control circuit as a memory activating unit which receives an address signal 4 from the interface circuit 3 and is connected to the interface circuit 3 via a data input / output bus 5; A memory space to which a signal 7 is input and connected to the bus control circuit 6 via a data input / output bus 8. The memory space 9 may be the entire memory area of the nonvolatile semiconductor memory device or a part of the memory area. Reference numeral 16 denotes an indefinite value generation instruction signal 1 from the interface circuit 3.
5, an indefinite value generation circuit as an indefinite value generation section that outputs an indefinite value output signal 17 to the interface circuit 3; and an indefinite value output signal 17 from the indefinite value generation circuit 16 and the indefinite value output signal 17 from the interface circuit 3. Of the password input command signal 1
9 to the interface circuit 3 and an arithmetic circuit as an arithmetic unit for outputting the unique password signal 21;
13 is a unique password signal 21 from the arithmetic circuit 20
And the password signal 1 from the interface circuit 3
2 is a comparison circuit serving as a password discriminating unit that outputs a security release signal 14 to the bus control circuit 6 in response to the request. The interface circuit 3 also functions as a password input unit, a password input command input unit, and a password input command determination unit. Further, the interface circuit 3, the bus control circuit 6, the indefinite value generation circuit 16,
The arithmetic circuit 20 and the comparison circuit 13 constitute a security circuit for a semiconductor memory device.

In the nonvolatile semiconductor memory device having the above configuration, when security is set, access to the memory space 9 by the bus control circuit 6 does not operate normally. In order to release the security from the state where the security is set, first, an “undefined value generation command” is externally input to the interface circuit 3 by the input signal 1. When receiving the “undefined value generation command”, the interface circuit 3 issues an undefined value generation command signal 15 to the undefined value generation circuit 16.

Next, the indefinite value generation circuit 16 receiving the indefinite value generation command signal 15 generates an indefinite value, and sends the indefinite value to the interface circuit 3 and the arithmetic circuit 20.
When an “undefined value read command” is input from outside, the interface circuit 3 outputs the currently set undefined value to the outside via the data input / output bus 2. The arithmetic circuit 20 generates a “password input command” and a “unique password” by performing a specific operation based on the indefinite value output signal 17 sent from the indefinite value generation circuit 16, A password signal 21 representing “password” is transmitted to the comparison circuit 13, and a password input command signal 19 representing “password input command” is transmitted to the interface circuit 3. When the control signal input from the outside matches the password input command signal 19, the interface circuit 3 receives the input of the “input password” from the outside and outputs the “input password”.
Is transmitted to the comparison circuit 13.
Next, the comparison circuit 13 compares the unique password signal 21 representing the “unique password” generated by the arithmetic circuit 20 with the password signal 12 representing the “input password”.
When the unique password signal 21 and the password signal 12 match, a security release signal 14 is issued. When the bus control circuit 6 receives the security release signal 14, the bus control circuit 6 releases the security,
Perform subsequent access to the protected memory space normally.

Therefore, in order to release the security, an external system reads an indefinite value from this nonvolatile semiconductor memory device, executes the same operation as that of the arithmetic circuit 20, and generates a “password input command” and a “unique password”. calculate. Thus, security can be released only when the operation result of the external system matches the operation result inside the semiconductor device. Therefore, unauthorized access to the protected memory space 9 becomes extremely difficult, and a non-volatile semiconductor memory device having a stronger and harder to understand security function can be realized.

When the interface unit 3 receives a specific command from the outside, it issues an additional operation command signal 18, and upon receiving the signal, the operation circuit 20 sends the current "password input command" and "unique password". Further, even when the same indefinite value is generated, the “password input command” and the “unique password” can be changed by an external operation. As a condition for issuing the additional operation command signal 18, for example, a control that is seemingly unrelated to security control such as selection of a key address or an ID read command can be used to make it more difficult to clarify the security release condition. . When the additional operation command signal 18 is used, it is necessary for an external system to know the conditions under which the additional operation occurs and the contents of the additional operation.

Further, by storing the key address in a rewritable nonvolatile memory cell, the key address can be changed every time security is released, so that unauthorized release of security can be ensured. Can be prevented.

The rewritable nonvolatile memory cell for storing the key address may be stored in an unused redundant memory cell among redundant memory cells constituting a part of the memory of the nonvolatile semiconductor memory device. Alternatively, by storing a key address in a memory cell assigned to an address set under a predetermined condition, it is not necessary to provide a separate memory cell for storing the key address, and cost can be reduced.

According to the first embodiment, in order to prevent the security from being released by trying all combinations of the "password input command" and the "unique password", the "password input command" and the "password input command" If the “unique password” does not match the operation result, an undefined value is newly generated, or the additional operation instruction signal 18 is issued to update the “password input command” or the “unique password”. it can. Therefore, since the "password input command" and the "unique password" can be changed, it is difficult to clarify the security release condition only by probing the input signal.

Further, by using the constant stored in the rewritable nonvolatile memory cell for the operation executed by the arithmetic circuit 20, the operation is changed by rewriting the contents of the rewritable nonvolatile memory cell. It becomes possible. In particular, by using a rewritable nonvolatile memory cell such as an EEPROM, it becomes easy to use a different calculation method for each chip or to change the calculation method later.

It is not always necessary to use the operation result for both the “password input command” and the “unique password”, and one of them may be fixed. The above "password input command" or "unique password"
The security is reduced by fixing either one of them, but the trouble of releasing the security can be reduced.

The "undefined value" and "password" to be used do not need to be a single value, and a plurality of "undefined values" and "passwords" can be set. in this case,
By increasing the combination of the “undefined value” and the “password”, the probability that the security release condition is accidentally solved is reduced.

FIG. 2 is a schematic block diagram of a specific example of the indefinite value generating circuit 16 (shown in FIG. 1) according to the first embodiment. Reference numeral 31 denotes a power supply voltage; 32, a power-on detection circuit; An input signal, 34 is a counter circuit, 35 is a read data bus for the total number of power-on times, 36 is a write data bus for the total number of power-on times, and 37 is a rewritable nonvolatile memory cell. In this indefinite value generation circuit, by providing a rewritable nonvolatile memory cell, the cumulative power-on count is used as the “undefined value”.

Next, the operation of the indefinite value generating circuit will be described. When the power supply of the nonvolatile semiconductor memory device shown in FIG.
The power-on detection circuit 32 detects power-on and issues a power-on signal 33. When the counter circuit 34 receives the power-on signal 33, the counter circuit 34 reads the cumulative power-on count from that time through the read data bus 35 of the total power-on count from the non-volatile memory cell 37, and increments the read count by turning it on. Memory cell 37
Is written via the write data bus 36 of the total number of power-on times. Since the cumulative power-on count stored in the nonvolatile memory cell 37 changes every time the power is turned on, it can be used as an “undefined value” used in the first embodiment. Writing the “undefined value” and the operation result to the nonvolatile memory cell 37 is very effective for generating the next “undefined value”. Some operations on the nonvolatile semiconductor memory device are not cleared when the power is turned off.
The cumulative number of times (for example, turning on the power supply shown in FIG. 2) may be used as the “undefined value”, or a pseudo random number generated by the mixed congruential method may be used as the “undefined value”.

In the first embodiment, the “password input command” and the “unique password” are determined by the arithmetic circuit 20 as the arithmetic unit based on the “undefined value” by a predetermined arithmetic operation. Only the "password" may be obtained by calculation, and the "password input command" may be set as a fixed condition. On the other hand, only the “password input command” may be calculated by the arithmetic circuit 20 as the arithmetic unit based on the “undefined value”, and the “unique password” may be a fixed condition.

(Second Embodiment) FIG. 3 is a schematic block diagram of a nonvolatile semiconductor memory device using a security circuit for a semiconductor memory device according to a second embodiment of the present invention.
103 is an input signal 10 from an external system (not shown).
1 is input to the external system and the data input / output bus 10
The interface circuit 106 is connected via the interface signal 103 to the address signal 1 from the interface circuit 103.
04 is input, and a bus control circuit as a memory activation unit connected to the interface circuit 103 via the data input / output bus 105, and 109 is the bus control circuit 1
An address signal 107 is input from the interface circuit 1 to the bus control circuit 106 via a data input / output bus 108.
Receiving a signal 115 representing an arbitrary “numeric value” from the outside which is the source of the “unique password” and the “password input command” from step 03, outputs a password input command signal 119 to the interface circuit 103,
An arithmetic circuit serving as an arithmetic unit for outputting the unique password signal 121 is provided with a unique password signal 121 from the arithmetic circuit 120 and the interface circuit 103.
Is a comparison circuit as a password discriminating unit that receives the password signal 112 from the CPU and outputs a security release signal 114 to the bus control circuit 106. The interface circuit 103 also serves as a numerical value input section, a password input section, a password input command input section, and a password input command determination section. The interface circuit 103, the bus control circuit 106, the arithmetic circuit 120, and the comparison circuit 113 constitute a security circuit for a semiconductor memory device. Further, the memory space 109 may be the entire memory area of the nonvolatile semiconductor memory device or a part of the memory area.

In the nonvolatile semiconductor memory device having the above configuration, when security is set, access to a specific memory space by the bus control circuit 106 does not operate normally. In order to release the security from the state in which the security is set, first, an arbitrary “numerical value” is externally input to the interface circuit 103 via the data input / output bus 102. The interface circuit 103 sends a signal 115 representing this “numerical value” to the arithmetic circuit 120. Then, the arithmetic circuit 120 performs a specific arithmetic operation based on the signal 115 representing “numerical value”,
A unique password signal 121 and a password input command signal 119 are generated. The above operation circuit 1 in an external system
When a “password input command” generated by executing the same operation as in step 20 is input by the input signal 101, the interface circuit 103 transmits the input signal 101 to the comparison circuit 113 as a password signal 112. The comparison circuit 113 compares the unique password signal 121 generated by the arithmetic circuit 120 with the password signal 112 input from the outside, and issues a security release signal 114 when the unique password signal 121 and the password signal 112 match. I do. Then, when the bus control circuit 106 receives the security release signal 114, the bus control circuit 106 releases the security and normally executes the subsequent access to the protected memory space.

In the second embodiment, as in the first embodiment, it is possible to cause the arithmetic circuit 20 to perform an additional operation by performing a specific operation.

In order to release the security, the external system executes the same operation as the arithmetic circuit 120 on the “numeric value” input to the nonvolatile semiconductor memory device, and calculates the “password input command” and the “unique password”. There is a need to. In the second embodiment, unlike the first embodiment,
There is no need to incorporate a circuit for generating an “undefined value” in the nonvolatile semiconductor memory device. Also, if there is an externally generated means for generating an “undefined value” such as a random number, input the “undefined value” generated externally as a “numeric value” that is the basis of the “unique password” and “password input command”. Accordingly, the same effect as that of the first embodiment can be obtained, and the indefinite value generation circuit of the first embodiment becomes unnecessary. In the nonvolatile semiconductor memory device, when the same “numeric value” is input, the same “unique password” and “password input command” are generated, so that exactly the same effects as in the first embodiment are obtained. Although it is not possible to obtain, the first embodiment is different from the first embodiment in that any "numeric value", "unique password", and "password input command" that can be used each time can be used, and the input cannot be specified after the security release condition is clarified. The same effect can be obtained.

Therefore, the protected memory space 109
It becomes extremely difficult to make unauthorized access to the device, and it is possible to realize a nonvolatile semiconductor memory device having a stronger and harder to understand security function.

In the second embodiment, the "password input command" and the "unique password" are obtained by the predetermined operation by the operation circuit 120 as the operation unit. However, the operation unit obtains only the "unique password" by the operation. The "password input command" may be a fixed condition. On the other hand, only the “password input command” may be calculated by the arithmetic circuit 20 as an arithmetic unit, and the “unique password” may be set as a fixed condition.

(Third Embodiment) FIG. 4 is a schematic block diagram showing the configuration of a security system according to a third embodiment of the present invention. As shown in FIG. 4, an input signal 201 from an external system (not shown) is input to a nonvolatile semiconductor memory device A (hereinafter, device A), and the nonvolatile semiconductor memory device A is connected to the external system via a data input / output bus 202. Interface circuit 203 connected to the
3, the bus control circuit 206 connected to the interface circuit 203 via the data input / output bus 205, and the bus control circuit 2
An address signal 207 is input to the bus control circuit 206 and a memory space 209 is connected to the bus control circuit 206 via a data input / output bus 208. The non-volatile semiconductor storage device B (hereinafter referred to as device B) receives the input signal 2
And a security system circuit 224 serving as a security setting unit and a security canceling unit which receives an input signal from the interface circuit 223 and outputs a security canceling signal 214 to the bus control circuit 206 of the device A. And The security system circuit 224 of the device B is a circuit composed of the indefinite value generation circuit, the arithmetic circuit, and the comparison circuit shown in the first embodiment, or the second system.
The circuit including the arithmetic circuit and the comparison circuit described in the embodiment can be used.

In the security system having the above configuration, when security is set, access to a specific memory space of the device A by the bus control circuit 206 does not operate normally. To release the security from the state in which the security is set, first, a “security release command” is externally input to the device B. Then, in response to the “security release command”, the interface circuit 223 of the device B issues a security control execution command to the security system circuit 224 by the input signal 225. Then, the security system circuit 22 receiving the security control execution instruction
4 executes security control. This security control is to generate a password by performing a specific operation based on the “undefined value” generated by the undefined value generation circuit shown in the first embodiment, and to compare the password with an externally input password. A password is generated by performing a specific operation based on the control to be executed or an arbitrary “numeric value” input from the outside shown in the second embodiment, and comparison with the password input from the outside is performed. Use the control to be executed. The security system circuit 224 issues a security release signal 214 to the device A when the security release is permitted in the security control. Then, the bus control circuit 226 of the device A sends the security release signal 21
Upon receipt of No. 4, the security is released and the subsequent access to the protected memory space of the device A is normally performed.

Therefore, it is possible to realize a security system having a security function that is more robust and difficult to understand.

In the third embodiment, the security control is executed by inputting the security release signal 214 to the bus control circuit 206 in the device A, but by inputting this security release signal to the interface circuit 203, Security control may be performed.

Further, in the third embodiment, the security release signal 214 does not need to be a single signal, and the security control can be executed using a plurality of security release signals.

In the third embodiment, a security system having two nonvolatile semiconductor memory devices as semiconductor devices has been described. However, the security system is not limited to this, and a plurality of semiconductor devices including at least one semiconductor memory device may be used. It may be provided with a device. Also, security control may be performed on a plurality of semiconductor storage devices at the same time in the same manner.

In the first to third embodiments, the security circuit for a semiconductor memory device is applied to a nonvolatile semiconductor memory device. However, the present invention may be applied to a semiconductor memory device having no nonvolatile memory.

[0069]

As is clear from the above description, according to the security circuit for a semiconductor memory device of the first aspect of the present invention, the security is released by changing the indefinite value by the indefinite value generation unit every time the security is released. Input password, that is, the operation result of the operation unit can be changed, and unauthorized access to the protected memory space becomes extremely difficult, so that the security function of the semiconductor memory device can be strengthened and illegal (or incorrect) It is very effective in preventing reading, writing and duplication.

According to the security circuit for a semiconductor memory device of the second aspect of the present invention, the password input command for inputting the input password, that is, the password input command for inputting the input password, is changed by the variable value generated by the variable value generator every time security is released. It is possible to change the operation result of the operation unit, and it becomes extremely difficult to illegally access the protected memory space, so that the security function of the semiconductor memory device can be strengthened, and illegal (or erroneous) reading, writing and It is extremely effective in preventing duplication.

According to the security circuit for a semiconductor memory device of the invention of claim 3, in the security circuit for a semiconductor memory device of claim 1 or 4, the indefinite value generated by the indefinite value generation section can be rewritten. By storing the nonvolatile memory cell, the indefinite value is stored without being cleared when the power is turned off, so that the stored indefinite value can be effectively used to generate the next indefinite value.

According to the security circuit for a semiconductor memory device of the present invention, the password for releasing the security, that is, the operation of the operation unit, is changed by changing the numerical value input to the numerical value input unit every time the security is released. The ability to alter results and make unauthorized access to protected memory space extremely difficult enhances the security capabilities of semiconductor memory devices and prevents unauthorized (or erroneous) reads, writes and duplications It is extremely effective in doing.

According to the security circuit for a semiconductor memory device of the present invention, the password input command for inputting the input password, that is, the arithmetic operation, is changed by changing the numerical value input to the numerical value input unit every time security is released. It is possible to change the operation result of the section, and it becomes extremely difficult to make unauthorized access to the protected memory space, so that the security function of the semiconductor memory device can be strengthened and illegal (or erroneous) reading, writing and duplication It is extremely effective in preventing.

According to the security circuit for a semiconductor memory device of the invention of claim 6, in the security circuit for a semiconductor memory device according to any one of claims 1, 2, 4, and 5, the security circuit for use in the operation of the arithmetic unit is used. Since the constant is stored in the rewritable nonvolatile memory cell, it is possible to easily change the operation content of the arithmetic unit by rewriting the constant stored in the rewritable nonvolatile memory cell.

Further, according to the security circuit for a semiconductor memory device of the present invention, in the security circuit for a semiconductor memory device according to the first or fourth aspect, the password discriminating unit is configured to determine a result of the operation by the operation unit and the password input. If the input password entered in the section does not match, the operation result is changed by further adding the operation to the operation result of the operation section. The cancellation condition can be prevented from being clarified.

According to the security circuit for a semiconductor memory device of the present invention, in the security circuit for a semiconductor memory device according to the second or fifth aspect, the password input command discriminating unit determines the result of the operation by the operation unit and the password input command determination unit. If the password input command input to the password input command input unit does not match, the operation result is further added to the operation result of the operation unit and the operation result is changed, so that all combinations of the password input command and the input password are changed. Attempting to prevent the security release condition from being clarified can be prevented.

According to the security circuit for a semiconductor memory device according to the ninth aspect of the present invention, in the security circuit for a semiconductor memory device according to any one of the first, second, fourth, and fifth aspects, the security control is apparently related to security control. By selecting a non-existent key address, an operation is added to the operation result of the operation unit to change the operation result, so that security can be more reliably prevented from being released.

According to the security circuit for a semiconductor memory device of the present invention, in the security circuit for a semiconductor memory device according to any one of the first to ninth aspects,
By storing the non-volatile memory cell in which the operation result of the operation unit is rewritable, the operation result is not cleared when the power is turned off, so that the operation content can be changed using the operation result next.

According to the security circuit for a semiconductor memory device of the present invention, the key address is stored in a rewritable nonvolatile memory cell. The key address can be rewritten, and the security can be more reliably prevented from being illegally released.

Further, according to the security circuit for a semiconductor memory device of the twelfth aspect of the present invention, in the security circuit for a semiconductor memory device according to the eleventh aspect, of the redundant memory cells constituting a part of the memory of the semiconductor memory device, By storing the key address in a redundant memory cell that is not used, it is not necessary to newly provide a memory cell for storing the key address, and the cost can be reduced.

According to the security circuit for a semiconductor memory device of the present invention, in the security circuit for a semiconductor memory device of the present invention, an address assigned to an address set under a predetermined condition in a memory of the semiconductor memory device is provided. By storing the key address in the memory cell, it is not necessary to newly provide a memory cell for storing the key address, and the cost can be reduced.

According to the security system of the invention, a security system comprising the semiconductor memory device security circuit according to any one of claims 1 to 13 and a plurality of semiconductor devices including the semiconductor memory device. In the semiconductor device having the security release unit, when the security release condition of the security release unit is satisfied, a security release signal is output from the security release unit to the memory activation unit of the semiconductor storage device, and the security release signal is output. The memory activation unit receiving the
Since a predetermined memory space of the semiconductor memory device is activated, a more robust security system having a security function that is difficult to understand can be realized.

According to the security system of the fifteenth aspect, in the security system of the fourteenth aspect, the semiconductor device having the security release unit is plural, and the memory activation unit of the semiconductor storage device is Since a predetermined memory space is activated based on a security release signal from a security release unit of a plurality of semiconductor devices, a security system having a more robust and difficult to understand security function can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a nonvolatile semiconductor memory device using a security circuit for a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a schematic block diagram of a specific example of an indefinite value generation circuit used in the nonvolatile semiconductor memory device.

FIG. 3 is a schematic block diagram of a nonvolatile semiconductor memory device using a security circuit for a semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a schematic block diagram of a security system according to a third embodiment of the present invention.

FIG. 5 is a schematic block diagram of a nonvolatile semiconductor memory device using a conventional security circuit for a semiconductor memory device.

FIG. 6 is a schematic block diagram of a nonvolatile semiconductor memory device using another conventional security circuit for a semiconductor memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Input signal, 2 ... Data input / output bus, 3 ... Interface circuit, 4 ... Address signal, 5 ... Data input / output bus, 6 ... Bus control circuit, 7 ... Address signal, 8 ... Data input / output bus, 9 ... Memory Space 12 password signal 13 comparison circuit 14 security release signal 15 undefined value generation instruction signal 16 undefined value generation circuit 17 undefined value output signal 18 additional operation instruction signal 19 password Input command signal, 20: arithmetic circuit, 21: unique password signal, 31: power supply voltage, 32: power-on detection circuit, 33: power-on signal, 34: counter circuit, 35: data bus for reading the total number of power-on times, 36 ... write data bus for the total number of power-on times, 37 ... non-volatile memory cell, 101 ... input signal, 102 ... data input / output bus Reference numeral 103: Interface circuit 104: Address signal 105: Data input / output bus 106: Bus control circuit 107: Address signal 108: Data input / output bus 109: Memory space 113: Comparison circuit 114: Security release 115, a signal representing a numerical value that is a source of a password, 119, a password input command signal, 120, an arithmetic circuit, 121, a unique password signal, 201, an input signal, 202, a data input / output bus, 203, an interface circuit, 204 .., An address signal, 205, a data input / output bus, 206, a bus control circuit, 207, an address signal, 208, a data input / output bus, 209, a memory space, 222, an input signal, 223, an interface circuit, 224, a security system circuit, 225… input Force signal 214 Security release signal.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Ken Sumiya 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka F-term (reference) 5B017 AA01 AA06 AA08 BA05 BB03 BB05 BB10 CA12 CA16

Claims (15)

[Claims] 1. A semiconductor memory security circuit for inactivating a predetermined memory space according to a security setting condition and activating the predetermined memory space according to a security release condition, wherein one or more indefinite values are generated. An indefinite value generation unit that outputs the indefinite value, an operation unit that performs a predetermined operation based on the indefinite value from the indefinite value generation unit, a password input unit that receives an input password from outside, A password discriminator for discriminating whether or not the calculation result of the calculation unit matches the input password input to the password input unit; and the password discrimination unit matches the calculation result of the calculation unit with the input password. And determining that the security release condition has been satisfied, and activating the predetermined memory space. The semiconductor memory device for a security circuit characterized in that the. 2. A security circuit for a semiconductor memory device for inactivating a predetermined memory space according to a security setting condition and activating the predetermined memory space according to a security release condition, wherein one or more indefinite values are generated. An indeterminate value generator that outputs the indefinite value; an operation unit that performs a predetermined operation based on the indefinite value from the indefinite value generator; and a password input command input unit that receives a password input command from outside A password input command determining unit that determines whether a calculation result of the calculating unit matches the password input command input to the password input command input unit; and If it is determined that the calculation result matches the password input command, the input password is input. A password input unit, a password determination unit that determines whether the input password input to the password input unit matches a preset unique password, and the password determination unit determines whether the input password and the unique password And a memory activating unit for activating the predetermined memory space when it is determined that the security release condition is satisfied. 3. The security circuit for a semiconductor memory device according to claim 1, wherein the indefinite value generation unit has a rewritable nonvolatile memory cell that stores the generated indefinite value. Security circuits for semiconductor storage devices. 4. A security circuit for a semiconductor memory device in which a predetermined memory space is deactivated according to a security setting condition and a predetermined memory space is activated according to a security release condition. Unit, an operation unit for performing a predetermined operation based on the numerical value input to the numerical value input unit, a password input unit to which an input password is externally input, and an operation result of the operation unit and input to the password input unit A password discriminating unit for discriminating whether or not the input password matches the input password, and when the password discriminating unit discriminates that the calculation result of the calculating unit matches the input password, the security release condition is satisfied. And a memory activating unit for activating the predetermined memory space.置用 security circuit. 5. A semiconductor memory security circuit for inactivating a predetermined memory space according to a security setting condition and activating the predetermined memory space according to a security release condition, wherein a numerical value input from the outside is performed. Unit, a calculation unit for performing a predetermined calculation based on the numerical value input to the numerical value input unit, a password input command input unit for externally inputting a password input command, a calculation result of the calculation unit, and the password input A password input command determining unit that determines whether or not the password input command input to the command input unit matches; and that the password input command determining unit matches the calculation result of the calculation unit with the password input command. If it is determined, the password input section for inputting the input password and the password A password discriminating unit for discriminating whether or not the input password input to the password input unit matches a preset unique password; and that the password discriminating unit matches the input password and the unique password. A memory activating unit for activating the predetermined memory space upon determining that the security release condition is satisfied; and a security circuit for a semiconductor memory device. 6. The security circuit for a semiconductor memory device according to claim 1, wherein the arithmetic unit is configured to store a constant set under a predetermined condition. A security circuit for a semiconductor memory device, comprising a volatile memory cell and using a constant stored in the rewritable nonvolatile memory cell for calculation. 7. The security circuit for a semiconductor memory device according to claim 1, wherein said password discriminating unit discriminates that a result of operation of said computing unit does not match the input password input to said password input unit. Then, the operation section adds an operation to the operation result to change the operation result, thereby providing a security circuit for a semiconductor memory device. 8. The security circuit for a semiconductor memory device according to claim 2, wherein the password input command discriminating unit determines the result of the operation by the operation unit and the password input command input to the password input command input unit. When it is determined that they do not match, the arithmetic unit further performs an operation on the operation result to change the operation result, and the result is changed. 9. The semiconductor memory device security circuit according to claim 1, wherein when a key address set under a predetermined condition is selected, the arithmetic unit includes: A security circuit for a semiconductor memory device, wherein the operation result is further changed by adding an operation to the operation result. 10. The security circuit for a semiconductor memory device according to claim 1, further comprising a rewritable nonvolatile memory cell for storing a result of the operation performed by said operation unit. Security circuits for semiconductor storage devices. 11. The security circuit for a semiconductor memory device according to claim 9, wherein the key address is stored in a rewritable nonvolatile memory cell. 12. The security circuit for a semiconductor memory device according to claim 11, wherein a redundant memory cell forming a part of a memory of the semiconductor memory device is used as the rewritable nonvolatile memory cell for storing the key address. A security circuit for a semiconductor memory device. 13. The security circuit for a semiconductor memory device according to claim 11, wherein a memory cell assigned to an address set under a predetermined condition is used as a rewritable nonvolatile memory cell for storing the key address. A security circuit for a semiconductor memory device. 14. A security system comprising: the semiconductor memory device security circuit according to claim 1; and a plurality of semiconductor devices including the semiconductor memory device. At least one has a security setting unit that deactivates a predetermined memory space of the semiconductor storage device. The semiconductor storage device has the memory activation unit of the security circuit for the semiconductor storage device. A security system, wherein at least one of the semiconductor devices has a security release unit having a configuration obtained by removing the memory activation unit from the security circuit for the semiconductor storage device. 15. The security system according to claim 14, wherein a plurality of said semiconductor devices having said security release unit are provided, and said memory activation unit of said semiconductor storage device is said security device of said plurality of semiconductor devices. A security system for activating a predetermined memory space based on a security release signal from a release unit.