JP2000315946A5 - - Google Patents

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Publication number
JP2000315946A5
JP2000315946A5 JP2000076669A JP2000076669A JP2000315946A5 JP 2000315946 A5 JP2000315946 A5 JP 2000315946A5 JP 2000076669 A JP2000076669 A JP 2000076669A JP 2000076669 A JP2000076669 A JP 2000076669A JP 2000315946 A5 JP2000315946 A5 JP 2000315946A5
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JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2000076669A
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JP2000315946A (ja
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Publication date
Priority claimed from US09/271,551 external-priority patent/US6131168A/en
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Publication of JP2000315946A publication Critical patent/JP2000315946A/ja
Publication of JP2000315946A5 publication Critical patent/JP2000315946A5/ja
Withdrawn legal-status Critical Current

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JP2000076669A 1999-03-18 2000-03-17 刻時システム及び刻時方法 Withdrawn JP2000315946A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/271,551 US6131168A (en) 1999-03-18 1999-03-18 System and method for reducing phase error in clocks produced by a delay locked loop
US271551 1999-03-18

Publications (2)

Publication Number Publication Date
JP2000315946A JP2000315946A (ja) 2000-11-14
JP2000315946A5 true JP2000315946A5 (ja) 2007-05-10

Family

ID=23036070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000076669A Withdrawn JP2000315946A (ja) 1999-03-18 2000-03-17 刻時システム及び刻時方法

Country Status (2)

Country Link
US (1) US6131168A (ja)
JP (1) JP2000315946A (ja)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19944248C2 (de) * 1999-09-15 2002-04-11 Infineon Technologies Ag Inputbuffer einer integrierten Halbleiterschaltung
US6868504B1 (en) 2000-08-31 2005-03-15 Micron Technology, Inc. Interleaved delay line for phase locked and delay locked loops
US6535038B2 (en) 2001-03-09 2003-03-18 Micron Technology, Inc. Reduced jitter clock generator circuit and method for applying properly phased clock signals to clocked devices
US6937680B2 (en) * 2001-04-24 2005-08-30 Sun Microsystems, Inc. Source synchronous receiver link initialization and input floating control by clock detection and DLL lock detection
US20020184577A1 (en) * 2001-05-29 2002-12-05 James Chow Precision closed loop delay line for wide frequency data recovery
KR100548549B1 (ko) * 2001-12-31 2006-02-02 주식회사 하이닉스반도체 지연 고정 루프 회로
US6836166B2 (en) * 2003-01-08 2004-12-28 Micron Technology, Inc. Method and system for delay control in synchronization circuits
KR100636920B1 (ko) 2005-06-22 2006-10-19 주식회사 하이닉스반도체 반도체 소자의 타이밍 마진 판별 회로
GB0605150D0 (en) * 2006-03-14 2006-04-26 Glaxo Group Ltd Counter For Use With A Medicament Dispenser
US9143140B2 (en) 2011-02-15 2015-09-22 Cavium, Inc. Multi-function delay locked loop
JP5893958B2 (ja) * 2011-03-31 2016-03-23 ローム株式会社 半導体装置、及び電子機器
US8917129B1 (en) * 2013-06-12 2014-12-23 Ambarella, Inc. Generating signals with accurate quarter-cycle intervals using digital delay locked loop
US9281034B2 (en) 2013-10-03 2016-03-08 Cavium, Inc. Data strobe generation
US9793900B1 (en) 2016-06-29 2017-10-17 Microsoft Technology Licensing, Llc Distributed multi-phase clock generator having coupled delay-locked loops

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5740213A (en) * 1994-06-03 1998-04-14 Dreyer; Stephen F. Differential charge pump based phase locked loop or delay locked loop
JP2858561B2 (ja) * 1996-05-30 1999-02-17 日本電気株式会社 デジタルｄｌｌ回路
US5999576A (en) * 1997-07-14 1999-12-07 Realtek Semiconductor Corp. Delay-locked loop for data recovery
US6037812A (en) * 1998-05-18 2000-03-14 National Semiconductor Corporation Delay locked loop (DLL) based clock synthesis
US6055287A (en) * 1998-05-26 2000-04-25 Mcewan; Thomas E. Phase-comparator-less delay locked loop

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