JP2000315941A - Phase adjustment circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To adjust a phase difference between both pulse signals to substantially provide a phase difference of 180 degrees to the two pulse signals even when there is dispersion in a delay amount of each of inverters being component of a variable delay circuit. SOLUTION: The phase adjustment circuit is provided with a variable delay circuit 10 that generates a delayed clock pulse (DCLK) by delaying a clock pulse (CLK) signal and with a delay adjustment circuit 20 that adjusts a delay of the variable delay circuit 10 depending on a result of measurement of a phase difference between the CLK signal and the DCLK signal. The delay adjustment circuit 20 is provided with a PLL circuit 30 having a voltage controlled oscillator 33 consisting of a ring oscillator and having a counter 35 to count number of circulations of the signal in the ring oscillator. A state of the PLL circuit 30 at each of an up-edge time of the CLK signal and an up-edge time of the DCLK signal are compared and number of inverter stages of the variable delay circuit 10 is controlled in response to the result of comparison.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase adjusting circuit for adjusting a phase difference between two pulse signals so that the two pulse signals have a phase difference of substantially 180 degrees.

[0002]

2. Description of the Related Art A memory LSI employing a so-called DDR (double data rate) system is known. According to this method, in order to realize high-speed data transfer, control synchronized with both the rising edge (rising edge) and the falling edge (falling edge) of the clock pulse signal is performed. Therefore, a clock pulse signal having a duty ratio of 50% is required.

A clock pulse signal having a duty ratio of 50% can be generated from two pulse signals having a phase difference of 180 degrees. According to a conventional technique, a first pulse signal is input to a variable delay circuit including an even number of inverters connected in cascade to form one inverter chain. The delay amount of each inverter is adjusted so that the first pulse signal and the output pulse signal of the last-stage inverter have a phase difference of 360 degrees. Then, a second pulse signal having a phase difference of 180 degrees with respect to the first pulse signal is extracted from the center point of the inverter chain.

[0004]

According to the above prior art, if the delay amount of each inverter varies, a difference occurs between the delay amount of the first half and the delay amount of the second half of the inverter chain. . Therefore, the phase difference between the first pulse signal and the second pulse signal greatly deviates from 180 degrees. This problem is particularly serious when the frequency of both pulse signals is high.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a variable delay circuit in which the two pulse signals have a phase difference of substantially 180 degrees even if the delay amounts of the individual inverters vary. An object of the present invention is to make it possible to adjust a phase difference.

[0006]

To achieve the above object, the present invention provides a variable delay circuit for generating a second pulse signal obtained by delaying a first pulse signal by a variable delay amount. Measuring the phase difference between the first pulse signal and the second pulse signal, and, according to the result of the measurement, such that the first and second pulse signals have a phase difference of substantially 180 degrees. A configuration including a delay adjusting circuit for adjusting the delay amount of the variable delay circuit is basically adopted.

More specifically, in the first phase adjustment circuit according to the present invention, the variable delay circuit includes a plurality of inverters each having substantially the same unit delay amount and cascaded with each other. . The delay adjustment circuit counts a ring oscillator composed of an odd number of inverters each having substantially the same delay amount as each of the inverters constituting the variable delay circuit, and counts the number of turns of the signal in the ring oscillator. A first latch circuit for latching an output of each of the odd number of inverters constituting the ring oscillator and an output of the counter in response to an edge of the first pulse signal; A second latch circuit for latching the output of each of the odd number of inverters constituting the ring oscillator and the output of the counter in response to the edge of the second pulse signal; and the first and second latches A first pulse from an edge of the first pulse signal to an edge of the second pulse signal based on a latch result of each of the circuits.
Is the unit delay amount, and the length of the second period from the edge of the second pulse signal to the next edge of the first pulse signal is the unit delay amount. Respectively, and calculates the first value according to the result of the calculation.
The number of cascaded stages of the inverter to be used for generating the second pulse signal among the plurality of inverters forming the variable delay circuit is set so that the length of the period is substantially equal to the length of the second period. And an arithmetic circuit for controlling.

Further, in the second phase adjusting circuit according to the present invention, the delay adjusting circuit includes a capacitor for holding an analog control voltage for controlling a delay amount of the variable delay circuit and an edge of the first pulse signal. A first control pulse signal having a pulse width equal to the length of the first period up to the edge of the second pulse signal; and a first control pulse signal having a pulse width equal to the length of the first pulse signal. A control pulse generating circuit for generating a second control pulse signal having a pulse width equal to the length of the second period; and responsive to one of the first and second control pulse signals. A charge pump for charging the capacitor to increase the analog control voltage and discharging the capacitor to decrease the analog control voltage in response to the other signal. Then, the amount of delay of the variable delay circuit is controlled by the analog control voltage held in the capacitor so that the length of the first period substantially matches the length of the second period.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration example of a phase adjustment circuit according to the present invention. The phase adjustment circuit shown in FIG. 1 includes a variable delay circuit 10 for generating a delayed clock pulse (DCLK) signal obtained by delaying a clock pulse (CLK) signal by a variable delay amount, and a phase shifter between the CLK signal and the DCLK signal. A delay adjusting circuit 20 for measuring a phase difference and adjusting a delay amount of the variable delay circuit 10 according to a result of the measurement so that the CLK signal and the DCLK signal have a phase difference of substantially 180 degrees; It is provided with. Variable delay circuit 10
Includes a plurality of inverters 11 each having substantially the same unit delay Du and connected in cascade with each other to form one inverter chain, and a plurality of inverters 11 for changing the number of constituent stages of the inverter chain. And a switch 12. The number of the inverters 11 is four or more, and it is desirable that the number is as large as possible. Delay adjustment circuit 20
Has a phase-locked loop (PLL) circuit 30, a first latch circuit 40, a second latch circuit 50, and an arithmetic circuit 60.

The PLL circuit 30 includes a phase comparator 31, a low-pass filter (LPF) 32,
Voltage-controlled oscillator (V)
CO) 33, a frequency divider 34, and a counter 35, and are locked at a frequency several times as high as the CLK signal. VC
O33 is a ring oscillator composed of three inverters 36, 37, 38 each having substantially the same delay Du as the individual inverters 11 constituting the variable delay circuit 10. The output signals of the inverters 36, 37, and 38 are S1, S2, and S3, respectively. The unit delay Du of each inverter 11, 36, 37, 38 is LP
It is determined according to the control voltage V output from F22. The counter 35 has three inverters 3
The S3 signal is input so as to count the number of revolutions of the signal in the ring oscillator constituted by 6, 37 and 38.
The multi-bit output of the counter 35 is COUNT.

The first latch circuit 40 latches the S1, S2, S3 and COUNT outputs in response to the rising edge of the CLK signal. For this purpose, the first latch circuit 40 includes three flip-flops (FFs) 41, 42, 43 and one latch 44. In the following description, the outputs of these circuit elements 41, 42, 43, 44 are collectively referred to as a D1 signal.

The second latch circuit 50 latches the S1, S2, S3 and COUNT outputs in response to the rising edge of the DCLK signal. For this purpose, the second latch circuit 50 includes three flip-flops 51, 52, 53 and one latch 54. In the following description, these circuit elements 51, 52, 5
The outputs of 3, 54 are collectively called a D2 signal.

The arithmetic circuit 60 determines, based on the D1 signal and the D2 signal, how many times the length T1 of the first period from the rising edge of the CLK signal to the rising edge of the DCLK signal is greater than the unit delay Du. In addition, each of the lengths T2 of the second period from the rising edge of the DCLK signal to the next rising edge of the CLK signal is calculated as a multiple of the unit delay Du, and according to the result of the calculation, This is a circuit for controlling the number of cascaded inverters to be used for generating the DCLK signal among the plurality of inverters 11 constituting the variable delay circuit 10 so that T1 and T2 substantially match. Specifically, the D5 signal output from the arithmetic circuit 60 controls so that one of the switches 12 in the variable delay circuit 10 is turned on.

FIG. 2 shows a detailed configuration of the arithmetic circuit 60 in FIG. The arithmetic circuit 60 includes a first subtractor 61 for generating a D3 signal representing a difference between the D1 signal and the D2 signal.
And a register 62 for temporarily storing the D3 signal, and a second subtractor 63 for generating a D4 signal representing a difference between the D3 signal stored in the register 62 and the new D3 signal.
And a decoder 64 for converting the D4 signal to the D5 signal
And

FIG. 3 shows a state transition of the PLL circuit 30 in FIG. According to FIG. 3, in VCO cycle 1, S1 = 0, S2 = 1, S3 = 0, COUNT = n
(Integer). For example, “pattern number 0” is assigned to a combination of these values of the S1 to S3 signals. In VCO cycle 2, in response to the S3 signal, S1
As a result of the signal transitioning from 0 to 1, S1 = 1, S2 = 1,
S3 = 0. “Pattern No. 1” is assigned to a combination of these values of the S1 to S3 signals. In VCO cycle 3, the S2 signal changes from 1 to 0 in response to the S1 signal.
As a result, S1 = 1, S2 = 0, S3 = 0. “Pattern number 2” is assigned to a combination of these values of the S1 to S3 signals. In VCO cycle 4, as a result of the transition of the S3 signal from 0 to 1 in response to the S2 signal, S1 = 1, S2 = 0, S3 = 1, COUNT = n
It becomes +1. “Pattern number 3” is assigned to a combination of these values of the S1 to S3 signals. In the VCO cycle 5, the S1 signal changes from 1 to 0 in response to the S3 signal, resulting in S1 = 0, S2 = 0, and S3 = 1. S
“Pattern number 4” is assigned to a combination of these values of the 1 to S3 signals. In VCO cycle 6, S1
As a result of the transition of the S2 signal from 0 to 1 in response to the signal,
1 = 0, S2 = 1, and S3 = 1. “Pattern number 5” is assigned to a combination of these values of the S1 to S3 signals. In the VCO cycle 7, the S3 signal changes from 1 to 0 in response to the S2 signal, and as a result, the state returns to the state of pattern number 0 (S1 = 0, S2 = 1, S3 = 0).

The fact that there is a time difference of three times the unit delay Du between VCO cycles 1 and 4 in FIG. 3 can be known from the pattern number subtraction result (3-0 = 3). In addition, the unit delay D between VCO cycles 1 and 7
The fact that there is a time difference of 6 times u can be known based on the result of subtraction of the pattern number and the result of subtraction of the COUNT output. The first subtractor 61 in FIG. 2 performs such a subtraction.

FIG. 4 shows an operation example of the phase adjustment circuit of FIG. Here, it is assumed that the relationship of T1 <T2 holds. Hereinafter, the operation of each cycle of the CLK signal will be described.

In cycle 1, a D1 signal representing the up edge time t1 of the CLK signal and a D2 signal representing the up edge time t2 of the DCLK signal are obtained.

In cycle 2, a D1 signal representing the up edge time t3 of the CLK signal and a D2 signal representing the up edge time t4 of the DCLK signal are obtained. The D3 signal that is the output of the first subtractor 61 is T1 (= t2−t1).
Represents This D3 signal is temporarily stored in the register 62.

In cycle 3, the D3 signal becomes T2 (= t3
-T2). The second subtractor 63 generates a D4 signal representing T2-T1. The decoder 64 sets the delay amount to (T
A signal D5 indicating that the value should be increased by 2-T1) / 2 is supplied to the variable delay circuit 10.

As a result, in cycle 4, the length of the period from the rising edge of the CLK signal to the rising edge of the DCLK signal is adjusted to (T1 + T2) / 2. That is,
The CLK signal and the DCLK signal will have a phase difference of substantially 180 degrees.

The frequency of the CLK signal is 100 MHz.
, The length of the one cycle period is 10 ns. To generate an effective clock pulse signal with a duty ratio of 50% at this frequency, the CLK signal and the D signal
It is necessary to adjust the phase difference with the CLK signal with an accuracy of 1 ns. According to the above example, if the unit delay Du per inverter is set to several hundred ps, the required accuracy can be sufficiently satisfied. Since the effect of the accumulated error of the delay amount in the variable delay circuit 10 can be eliminated, it is OK even if the unit delay amount Du has a variation of about several tens ps.

FIG. 5 shows another example of the configuration of the phase adjustment circuit according to the present invention. The phase adjustment circuit of FIG. 5 includes a variable delay circuit 110 for generating a delayed clock pulse (DCLK) signal obtained by delaying a clock pulse (CLK) signal by a variable amount of delay, and a phase shifter between the CLK signal and the DCLK signal. The phase difference is measured, and according to the result of the measurement, CLK
And a delay adjusting circuit 120 for adjusting the amount of delay of the variable delay circuit 110 so that the signal and the DCLK signal have a phase difference of substantially 180 degrees. The variable delay circuit 110 includes an even number of inverters 111 cascaded together so as to form one inverter chain. It is desirable that the number of inverters 111 be as large as possible. The delay adjustment circuit 120 includes a control pulse generation circuit 130, a charge pump 140, and a capacitor 15
0.

The capacitor 150 is connected to the variable delay circuit 110
Is an element for holding the analog control voltage AV for controlling the delay amount.

The control pulse generating circuit 130 includes a first control pulse (UP) signal having a pulse width equal to the length T1 of a first period from the rising edge of the CLK signal to the rising edge of the DCLK signal, and the DCLK signal. And a second control pulse (DOWN) signal having a pulse width equal to the length T2 of the second period from the rising edge of the CLK signal to the next rising edge of the CLK signal.

The charge pump 140 operates to increase the analog control voltage AV in response to the UP signal.
This is a circuit for charging the capacitor 150 and discharging the capacitor 150 so as to reduce the analog control voltage AV in response to the DOWN signal. Therefore, the charge pump 14
Numeral 0 includes constant current sources 141 and 142, a first switch 143 that is on / off controlled by an UP signal, and a second switch 144 that is on / off controlled by a DOWN signal.

FIG. 6 shows an operation example of the phase adjustment circuit of FIG. In this case, the analog control voltage AV is updated according to the phase difference between the CLK signal and the DCLK signal.
The length of the period up to the rising edge of the signal is (T1 + T2)
/ 2. That is, the CLK signal and the DCLK signal have a phase difference of substantially 180 degrees.

[0029]

As described above, according to the present invention, a variable delay circuit for generating a second pulse signal obtained by delaying a first pulse signal by a variable delay amount;
A phase difference between the first pulse signal and the second pulse signal is measured, and according to a result of the measurement, the first and second pulse signals are varied so as to have a phase difference of substantially 180 degrees. Since the configuration including the delay adjustment circuit for adjusting the delay amount of the delay circuit is adopted, even if the delay amounts of the individual inverters constituting the variable delay circuit vary, the first and second pulse signals are not changed. Can have a phase difference of substantially 180 degrees.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a phase adjustment circuit according to the present invention.

FIG. 2 is a block diagram showing a detailed configuration of an arithmetic circuit in FIG.

FIG. 3 is a diagram showing a state transition of a PLL circuit in FIG. 1;

FIG. 4 is a timing chart illustrating an operation example of the phase adjustment circuit of FIG. 1;

FIG. 5 is a block diagram showing another configuration example of the phase adjustment circuit according to the present invention.

FIG. 6 is a timing chart illustrating an operation example of the phase adjustment circuit of FIG. 5;

[Explanation of symbols]

Reference Signs List 10 variable delay circuit 20 delay adjustment circuit 30 PLL circuit 31 phase comparator 32 low-pass filter 33 voltage controlled oscillator (ring oscillator) 34 frequency divider 35 counter 40 first latch circuit 50 second latch circuit 60 arithmetic circuit 110 variable delay Circuit 120 Delay adjustment circuit 130 Control pulse generation circuit 140 Charge pump 150 Capacitor CLK Clock pulse signal (first pulse signal) DCLK Delayed clock pulse signal (second pulse signal)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H03L 7/099 H03L 7/08 FF term (Reference) 5J001 BB02 BB12 BB14 BB20 BB21 BB24 BB25 CC00 DD06 DD09 5J039 JJ07 JJ11 JJ15 JJ20 KK01 KK04 KK10 KK13 KK16 KK20 KK23 KK24 KK27 KK33 MM06 NN06 5J098 AA14 AB04 AB12 AB15 AB22 AB23 AB25 AB31 AB36 AC04 AC09 AC21 AC27 AD03 FA03 FA09 5J106 AA03 CC01 DD21 DD13 DD32 DD JJ07 KK05 LL01 LL05

Claims (3)

[Claims] A variable delay circuit configured to generate a second pulse signal obtained by delaying a first pulse signal by a variable delay amount; Measuring a phase difference, and adjusting a delay amount of the variable delay circuit such that the first and second pulse signals have a phase difference of substantially 180 degrees according to a result of the measurement. A phase adjustment circuit comprising: a delay adjustment circuit. 2. The phase adjustment circuit according to claim 1, wherein the variable delay circuit includes a plurality of inverters each having substantially the same unit delay amount and cascaded with each other. A ring oscillator composed of an odd number of inverters each having substantially the same delay amount as an individual inverter constituting the variable delay circuit; anda circuit for counting the number of turns of a signal in the ring oscillator. A counter, a first latch circuit for latching an output of each of an odd number of inverters constituting the ring oscillator and an output of the counter in response to an edge of the first pulse signal; In response to the edge of the second pulse signal, the output of each of the odd number of inverters constituting the ring oscillator and the output of the counter are latched. A second latch circuit for performing a first latching operation from an edge of the first pulse signal to an edge of the second pulse signal based on a latch result of each of the first and second latch circuits. How many times the length of the period is the unit delay amount, and the length of the second period from the edge of the second pulse signal to the next edge of the first pulse signal is the unit delay The variable delay circuit is operated to calculate how many times the amount is, and according to the result of the operation, the length of the first period and the length of the second period are substantially equal. And a calculation circuit for controlling the number of cascaded stages of the inverters to be used for generating the second pulse signal among the plurality of inverters constituting the phase adjustment circuit. 3. The phase adjustment circuit according to claim 1, wherein the delay adjustment circuit includes: a capacitor for holding an analog control voltage for controlling a delay amount of the variable delay circuit; and an edge of the first pulse signal. A first control pulse signal having a pulse width equal to the length of a first period from the first pulse signal to an edge of the second pulse signal; and a second control signal following the first pulse signal from the edge of the second pulse signal. A control pulse generation circuit for generating a second control pulse signal having a pulse width equal to the length of a second period up to the edge of the control pulse signal; and one of the first and second control pulse signals A circuit for charging the capacitor to increase the analog control voltage in response to a signal and discharging the capacitor to decrease the analog control voltage in response to the other signal. A delay amount of the variable delay circuit is controlled by the analog control voltage held in the capacitor so that a length of the first period is substantially equal to a length of the second period. A phase adjustment circuit.