JP2000315765A - Semiconductor device and wiring board used for the same - Google Patents
Semiconductor device and wiring board used for the sameInfo
- Publication number
- JP2000315765A JP2000315765A JP12191699A JP12191699A JP2000315765A JP 2000315765 A JP2000315765 A JP 2000315765A JP 12191699 A JP12191699 A JP 12191699A JP 12191699 A JP12191699 A JP 12191699A JP 2000315765 A JP2000315765 A JP 2000315765A
- Authority
- JP
- Japan
- Prior art keywords
- electrode terminal
- semiconductor element
- wiring board
- hole
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、配線基板の外部接
続端子が形成された面の裏面に半導体素子を搭載して成
る半導体装置とそれに使用される配線基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor element mounted on a back surface of a wiring board on which external connection terminals are formed, and a wiring board used for the semiconductor device.
【０００２】[0002]
【従来の技術】従来、配線基板の外部接続端子が形成さ
れた面の裏面に半導体素子を搭載して成る半導体装置と
しては、本願出願人が出願した特開平１０−７４８６１
号に開示された半導体装置がある。この半導体装置５０
の概要構造を図８を用いて説明する。配線基板６０は、
貫通穴５２を有すると共に、一方の面（図８中の下面）
に、ランド部７２と貫通穴５２の開口縁部に形成された
第１ボンディング部５６とを備えた第１配線パターン５
８が形成されている。そしてこのランド部７２に外部接
続端子５４が接合されている。第１半導体素子６４は、
この配線基板６０の他方の面（図８中の上面）に電極端
子形成面を対向させて、この電極端子形成面に形成され
た第１電極端子６２が貫通穴５２の内側となるように接
着剤（一例としてエポキシ系）７４で接着されて搭載さ
れ、貫通穴５２を通して第１電極端子６２と第１ボンデ
ィング部５６とが第１ボンディングワイヤ６６により電
気的に接続されている。そして、貫通穴５２内部および
ボンディングワイヤ６６がポッティング剤等の樹脂６８
を用いて封止されている。なお、７０は、配線基板６０
の外部接続端子５４が形成された面に、この外部接続端
子５４を取り付けるランド部７２と第１ボンディング部
５６のみが露出するように塗布形成されたソルダレジス
ト層である。また、第１半導体素子６４は一例として、
第１電極端子６２が周縁部に形成されたペリフェラル型
半導体素子である。2. Description of the Related Art Conventionally, as a semiconductor device having a semiconductor element mounted on the back surface of a surface of a wiring board on which external connection terminals are formed, Japanese Patent Application Laid-Open No. 10-74861 filed by the present applicant has been proposed.
Has been disclosed. This semiconductor device 50
Will be described with reference to FIG. The wiring board 60
One surface (lower surface in FIG. 8) having a through hole 52
A first wiring pattern 5 including a land portion 72 and a first bonding portion 56 formed at an opening edge of the through hole 52.
8 are formed. The external connection terminal 54 is joined to the land 72. The first semiconductor element 64
The electrode terminal forming surface is opposed to the other surface (the upper surface in FIG. 8) of the wiring board 60, and the first electrode terminal 62 formed on the electrode terminal forming surface is bonded so as to be inside the through hole 52. The first electrode terminal 62 and the first bonding portion 56 are electrically connected to each other by the first bonding wire 66 through the through hole 52. Then, the inside of the through-hole 52 and the bonding wire 66 are made of resin 68 such as a potting agent.
And is sealed using 70 is the wiring board 60
Is a solder resist layer applied and formed so that only the land 72 and the first bonding portion 56 to which the external connection terminals 54 are attached are exposed on the surface on which the external connection terminals 54 are formed. The first semiconductor element 64 is, for example,
The first electrode terminal 62 is a peripheral-type semiconductor element formed on the periphery.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、最近で
はさらなる半導体素子の高密度実装化が半導体装置に対
して望まれるようになってきており、上記構造の半導体
装置では１つの半導体素子しか搭載できず、高密度化に
対応できないという課題がある。However, recently, there has been a demand for higher density mounting of semiconductor elements for semiconductor devices, and only one semiconductor element can be mounted on a semiconductor device having the above structure. However, there is a problem that it is impossible to cope with high density.
【０００４】従って、本発明は上記課題を解決すべくな
され、その目的とするところは、複数の半導体素子を配
線基板に少ないスペースで搭載可能として、半導体素子
の高密度実装が可能な半導体装置を提供することにあ
る。SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to solve the above-mentioned problem, and an object of the present invention is to provide a semiconductor device capable of mounting a plurality of semiconductor elements on a wiring board in a small space, thereby enabling high-density mounting of semiconductor elements. To provide.
【０００５】[0005]
【課題を解決するための手段】本発明は上記課題を解決
するために、請求項１記載の半導体装置は、貫通穴を有
すると共に、ランド部と前記貫通穴の開口縁部に形成さ
れた第１ボンディング部とを備えた第１配線パターンが
一方の面に形成された配線基板と、該配線基板の前記ラ
ンド部に接合された外部接続端子と、該配線基板の他方
の面に電極端子形成面を対向させて、該電極端子形成面
に形成された第１電極端子が前記貫通穴の内側となるよ
うに搭載され、貫通穴を通して第１電極端子と前記第１
ボンディング部とが第１ボンディングワイヤにより電気
的に接続された第１半導体素子と、前記貫通穴内部の第
１ボンディングワイヤを封止する樹脂と、前記配線基板
の他方の面に形成され、第２ボンディング部を備えると
共に、配線基板を貫通するスルーホールビアによって前
記第１配線パターン、前記第１ボンディング部または前
記外部接続端子と電気的に接続された第２配線パターン
と、前記第１半導体素子の背面に電極端子形成面を上に
して搭載され、該電極端子形成面の周縁部に形成された
第２電極端子と前記第２ボンディング部とが第２ボンデ
ィングワイヤにより電気的に接続された第２半導体素子
とを有し、前記第１半導体素子、第２半導体素子および
第２ボンディングワイヤを樹脂封止して成ることを特徴
とする。これによれば、第１半導体素子と第２半導体素
子とが積層された構造で配線基板に搭載することができ
るから、２つの半導体素子を配線基板に少ないスペース
で搭載可能として、半導体素子の高密度実装が可能とな
る。According to a first aspect of the present invention, there is provided a semiconductor device having a through-hole and a land formed on a land and an opening edge of the through-hole. A wiring board having a first wiring pattern having one bonding portion formed on one surface, an external connection terminal joined to the land portion of the wiring substrate, and forming an electrode terminal on the other surface of the wiring substrate. The first electrode terminal formed on the electrode terminal forming surface is mounted inside the through-hole with the surfaces facing each other, and the first electrode terminal is connected to the first electrode terminal through the through-hole.
A first semiconductor element electrically connected to a bonding portion by a first bonding wire, a resin sealing the first bonding wire inside the through hole, and a second semiconductor element formed on the other surface of the wiring board; A first wiring pattern, a second wiring pattern electrically connected to the first bonding portion or the external connection terminal by a through-hole via penetrating a wiring board; A second electrode, which is mounted on the back surface with the electrode terminal formation surface facing upward, and a second electrode terminal formed on a peripheral portion of the electrode terminal formation surface and the second bonding portion are electrically connected by a second bonding wire. And a semiconductor element, wherein the first semiconductor element, the second semiconductor element, and the second bonding wire are resin-sealed. According to this, since the first semiconductor element and the second semiconductor element can be mounted on the wiring board in a laminated structure, the two semiconductor elements can be mounted on the wiring board in a small space, thereby increasing the height of the semiconductor element. Density mounting becomes possible.
【０００６】また、請求項２記載の半導体装置は、前記
配線基板の他方の面に形成され、第３ボンディング部を
備えると共に、配線基板を貫通するスルーホールビアに
よって前記第１配線パターン、前記第１ボンディング部
または前記外部接続端子と電気的に接続された第３配線
パターンと、前記第２半導体素子の電極端子形成面に、
周縁部に第３電極端子が形成された電極端子形成面を上
にして搭載され、該第３電極端子と前記第３ボンディン
グ部とが第３ボンディングワイヤにより電気的に接続さ
れた第３半導体素子とを有し、前記第３ボンディングワ
イヤは、前記第１半導体素子、第２半導体素子および第
２ボンディングワイヤと共に樹脂封止されていることを
特徴とする。これによれば、第１半導体素子、第２半導
体素子および第３半導体素子が積層された構造で配線基
板に搭載することができるから、３つの半導体素子を配
線基板に少ないスペースで搭載可能として、半導体素子
のさらなる高密度実装が可能となる。A semiconductor device according to a second aspect of the present invention is provided with a third bonding portion formed on the other surface of the wiring substrate, the first wiring pattern being formed by a through-hole via penetrating the wiring substrate. A third wiring pattern electrically connected to one bonding portion or the external connection terminal, and an electrode terminal formation surface of the second semiconductor element,
A third semiconductor element mounted on a peripheral portion with an electrode terminal forming surface having a third electrode terminal formed thereon facing upward, and the third electrode terminal and the third bonding portion being electrically connected by a third bonding wire; Wherein the third bonding wire is resin-sealed together with the first semiconductor element, the second semiconductor element, and the second bonding wire. According to this, since the first semiconductor element, the second semiconductor element, and the third semiconductor element can be mounted on the wiring board in a laminated structure, the three semiconductor elements can be mounted on the wiring board in a small space. Further high-density mounting of semiconductor elements becomes possible.
【０００７】また、請求項３記載の配線基板は、貫通穴
が形成され、一方の面に、外部接続端子接続用のランド
部と前記貫通穴の開口縁部に形成された第１ボンディン
グ部とを備えた第１配線パターンが形成され、他方の面
に、第２ボンディング部を備えると共に、前記一方の面
から前記他方の面に貫通するスルーホールビアによって
前記第１配線パターン、前記第１ボンディング部または
前記外部接続端子と電気的に接続された第２配線パター
ンが形成されて成ることを特徴とする。この配線基板を
用いることによって、複数の半導体素子を少ないスペー
スで搭載可能として、半導体素子のさらなる高密度実装
が可能となる。According to a third aspect of the present invention, there is provided a wiring board, wherein a through hole is formed, and a land portion for connecting an external connection terminal and a first bonding portion formed at an opening edge of the through hole are formed on one surface. A first wiring pattern having a second bonding portion on the other surface, and a first bonding pattern formed by a through-hole via penetrating from the one surface to the other surface. And a second wiring pattern electrically connected to the external connection terminal or the external connection terminal. By using this wiring board, a plurality of semiconductor elements can be mounted in a small space, and further high-density mounting of semiconductor elements becomes possible.
【０００８】[0008]
【発明の実施の形態】以下、本発明に係る半導体装置の
好適な実施の形態を添付図面に基づいて詳細に説明す
る。なお、従来例で説明した半導体装置５０と同じ構成
については同じ符号を付し、詳細な説明は省略する。 （第１の実施の形態）半導体装置１０は、次の構成要素
を有する。第１半導体素子６４は、図２に示すように外
形が方形（正方形や直方形）に形成され、第１電極端子
６２が電極端子形成面Ａ上の周縁部、具体的には４つの
各縁部に列状（一例として２列）に配列されて形成され
たペリフェラル型の半導体素子である。なお、第１電極
端子６２は１列でも良いし、また第１半導体素子６４の
対向する１組の縁部に形成されるものでも良い。また、
後述するように電極端子形成面Ａ上の中央部に形成され
るものでも良い。Preferred embodiments of a semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings. Note that the same components as those of the semiconductor device 50 described in the conventional example are denoted by the same reference numerals, and detailed description is omitted. (First Embodiment) A semiconductor device 10 has the following components. As shown in FIG. 2, the first semiconductor element 64 is formed in a square (square or rectangular) outer shape, and the first electrode terminal 62 is formed on a peripheral portion on the electrode terminal formation surface A, specifically, each of four edges. Peripheral-type semiconductor elements formed in rows (for example, two rows). Note that the first electrode terminals 62 may be arranged in one row, or may be formed on a pair of opposing edges of the first semiconductor element 64. Also,
It may be formed at the center on the electrode terminal formation surface A as described later.
【０００９】第２半導体素子１２は、基本構成は第１半
導体素子６４と同様であり、第２電極端子１４が電極端
子形成面に配列されて形成されている。しかしながら、
後述するようにその第２電極端子１４を第２ボンディン
グワイヤ１６で配線基板６０の第２ボンディング部１８
と電気的に接続させる必要があるため、第２電極端子１
４が周縁部に配列されたペリフェラル型の半導体素子が
望ましい。中央部に第２電極端子１４が形成されている
と、ボンディング距離が長くなり、第２ボンディングワ
イヤ１６を張ることが困難になるからである。The second semiconductor element 12 has the same basic structure as the first semiconductor element 64, and is formed by arranging the second electrode terminals 14 on the electrode terminal forming surface. However,
As described later, the second electrode terminal 14 is connected to the second bonding portion 18 of the wiring board 60 with the second bonding wire 16.
To be electrically connected to the second electrode terminal 1
It is desirable to use a peripheral-type semiconductor element in which 4 are arranged on the periphery. This is because if the second electrode terminal 14 is formed at the center, the bonding distance becomes long, and it becomes difficult to stretch the second bonding wire 16.
【００１０】配線基板６０は図１や図３に示すように、
第１半導体素子６４に形成された第１電極端子６２の位
置に対応して貫通穴５２が形成されている。そして一方
の面（図１中の下面、図３中の前面）には、ランド部７
２と貫通穴５２の開口縁部に形成された第１ボンディン
グ部５６とを備えた第１配線パターン５８が形成されて
いる。このランド部７２に外部接続端子５４が接合され
ている。そして、さらに本実施の形態の配線基板６０の
場合には、他方の面（図１中の上面、図３中の後面）
に、第２ボンディンブ部１８を備えると共に、配線基板
６０を貫通するスルーホールビア２２によって第１配線
パターン５８、第１ボンディング部５６または外部接続
端子５４と電気的に接続された第２配線パターン２０が
形成されている。As shown in FIGS. 1 and 3, the wiring board 60
The through holes 52 are formed corresponding to the positions of the first electrode terminals 62 formed in the first semiconductor element 64. On one surface (the lower surface in FIG. 1 and the front surface in FIG. 3), a land portion 7 is provided.
2 and a first wiring pattern 58 including a first bonding portion 56 formed at an opening edge of the through hole 52. The external connection terminal 54 is joined to the land 72. Further, in the case of wiring substrate 60 of the present embodiment, the other surface (upper surface in FIG. 1, rear surface in FIG. 3)
A second wiring pattern 20 having a second bonding portion 18 and electrically connected to the first wiring pattern 58, the first bonding portion 56 or the external connection terminal 54 by the through-hole via 22 penetrating the wiring board 60. Are formed.
【００１１】そして半導体装置１０は、図１に示すよう
に、配線基板６０の他方の面（図１中の上面）に、まず
第１電極端子６２を有する第１半導体素子６４が、電極
端子形成面Ａを配線基板６０の他方の面に対向させ、第
１電極端子６２が貫通穴５２の内側となるように接着剤
７４で接着されて搭載される。そして、貫通穴５２から
覗く第１電極端子６２と第１ボンディング部５６とが貫
通穴５２を通して第１ボンディングワイヤ６６により電
気的に接続され、貫通穴５２内部および第１ボンディン
グワイヤ６６がポッティング剤等の樹脂材料６８を用い
て樹脂封止されている。ここまでの構成は従来の半導体
装置５０と同様である。In the semiconductor device 10, as shown in FIG. 1, a first semiconductor element 64 having a first electrode terminal 62 is formed on the other surface (upper surface in FIG. 1) of the wiring substrate 60 by first forming an electrode terminal. The surface A is opposed to the other surface of the wiring board 60, and the first electrode terminal 62 is attached with an adhesive 74 so as to be inside the through hole 52. The first electrode terminal 62 and the first bonding portion 56, which are viewed through the through hole 52, are electrically connected to each other by the first bonding wire 66 through the through hole 52, and the inside of the through hole 52 and the first bonding wire 66 are connected to a potting agent or the like. Is resin-encapsulated using the resin material 68 described above. The configuration so far is the same as that of the conventional semiconductor device 50.
【００１２】そして本実施の形態の特徴部分は、さらに
第１半導体素子６４の背面（図１中の上面）に、電極端
子形成面の周縁部に第２電極端子１４が形成された第２
半導体素子１２が、電極端子形成面を上にして、双方の
半導体素子６４，１２の背面同士が接着剤２４で接着さ
れて搭載されている。また、第２半導体素子１２の第２
電極端子１４は第２ボンディングワイヤ１６で配線基板
６０の他方の面に形成された第２ボンディング部１８に
電気的に接続される。そして、第１半導体素子６４、第
２半導体素子１２および第２ボンディングワイヤ１６
が、モールド剤等の封止用の樹脂２６を用いて封止され
る構造にある。なお、本実施の形態では配線基板６０の
他方の面が全体的に樹脂封止されているが、少なくとも
第１半導体素子６４、第２半導体素子１２および第２ボ
ンディングワイヤ１６が封止される構造であれば良い。The present embodiment is characterized in that the second electrode terminal 14 is formed on the back surface (the upper surface in FIG. 1) of the first semiconductor element 64 and on the periphery of the electrode terminal formation surface.
The semiconductor element 12 is mounted such that the back surfaces of the semiconductor elements 64 and 12 are adhered to each other with an adhesive 24 with the electrode terminal formation surface facing upward. Also, the second semiconductor element 12
The electrode terminal 14 is electrically connected to a second bonding portion 18 formed on the other surface of the wiring board 60 by a second bonding wire 16. Then, the first semiconductor element 64, the second semiconductor element 12, and the second bonding wire 16
However, there is a structure that is sealed using a sealing resin 26 such as a molding agent. In the present embodiment, the other surface of the wiring board 60 is entirely resin-sealed, but a structure in which at least the first semiconductor element 64, the second semiconductor element 12, and the second bonding wire 16 are sealed. Is fine.
【００１３】（第２の実施の形態）本実施の形態の半導
体装置２８の基本的な構成は、第１の実施の形態の半導
体装置１０と略同様であり、同じ構成については同じ符
号を付し、詳細な説明は省略する。相違する点は、図４
に示すように第１半導体素子６４の第１電極端子６２が
周縁部ではなく、中央部に形成されており、配線基板６
０の貫通穴５２もそれに対応して配線基板６０の中央部
に形成され、その形成個数が図４や図５に示すように１
個になっている点であり、他の構成は同じである。な
お、図５は図４の配線基板６０側から見た構成を説明す
るための説明図であり、図６は図４の第２半導体素子１
２側から見た構成を説明するための説明図である（な
お、樹脂モールドされる前の状態を示す）。(Second Embodiment) The basic configuration of a semiconductor device 28 according to the present embodiment is substantially the same as that of the semiconductor device 10 according to the first embodiment, and the same components are denoted by the same reference numerals. However, detailed description is omitted. The difference is in FIG.
As shown in the figure, the first electrode terminal 62 of the first semiconductor element 64 is formed not in the peripheral part but in the center part,
Zero through holes 52 are also formed in the center of the wiring board 60 correspondingly, and the number of the formed through holes 52 is one as shown in FIGS.
It is the point which is individual, and other composition is the same. FIG. 5 is an explanatory diagram for explaining the configuration as viewed from the wiring board 60 side in FIG. 4, and FIG. 6 is a second semiconductor element 1 in FIG.
FIG. 3 is an explanatory diagram for explaining a configuration viewed from two sides (shows a state before resin molding).
【００１４】（第３の実施の形態）本実施の形態の半導
体装置３０では、図７に示すように、第１の実施の形態
の半導体装置１０や第２の実施の形態の半導体装置２８
の第２半導体素子１２上にさらにもう一つ、第３半導体
素子３２を搭載している。図７には、一例として第１の
実施の形態の半導体装置１０に第３半導体素子３２を搭
載した構成を示すが、第２の実施の形態の半導体装置２
８にも同様に適用できる。(Third Embodiment) In a semiconductor device 30 of the present embodiment, as shown in FIG. 7, the semiconductor device 10 of the first embodiment and the semiconductor device 28 of the second embodiment
Another third semiconductor element 32 is mounted on the second semiconductor element 12. FIG. 7 shows a configuration in which the third semiconductor element 32 is mounted on the semiconductor device 10 according to the first embodiment as an example, but the semiconductor device 2 according to the second embodiment is shown in FIG.
8 as well.
【００１５】詳細な構成は、第２半導体素子１２の第２
電極端子１４が形成された面（電極端子形成面）の中央
部に、第２電極端子１４と干渉しない小さな外形に形成
され、周縁部に第３電極端子３４を有する第３半導体素
子３２がその電極端子形成面を上にして、背面が接着剤
３６で接着されて搭載されている。そして、配線基板６
０は、その他方の面に、さらに第３半導体素子３２の第
３電極端子３４と第３ボンディングワイヤ３８で電気的
に接続される第３ボンディング部４０を備えると共に、
配線基板６０を貫通するスルーホールビア２２によって
第１配線パターン５８、第１ボンディング部５６または
外部接続端子５４と電気的に接続される第３配線パター
ン４２が形成されている。なお、第３半導体素子３２の
第３電極端子３４の中に、供給される信号や電源が第２
半導体素子１２の第２電極端子１４と共通のものがある
場合には、この第３電極端子３４に接続される第３配線
パターンは、第２半導体素子１２用の第２ボンディング
部１８や第２配線パターン２０と接続される場合もあ
る。そして、第３ボンディングワイヤ３８は、第１半導
体素子６４、第２半導体素子１２および第２ボンディン
グワイヤ１６と共に樹脂２６で封止される。The detailed configuration is the same as that of the second semiconductor element 12.
A third semiconductor element 32 having a small outer shape formed so as not to interfere with the second electrode terminal 14 and having a third electrode terminal 34 at a peripheral portion is provided at the center of the surface (electrode terminal formation surface) on which the electrode terminal 14 is formed. With the electrode terminal forming surface facing upward, the back surface is mounted with an adhesive 36 bonded thereto. And the wiring board 6
0 further includes a third bonding portion 40 electrically connected to the third electrode terminal 34 of the third semiconductor element 32 by a third bonding wire 38 on the other surface,
The third wiring pattern 42 that is electrically connected to the first wiring pattern 58, the first bonding portion 56, or the external connection terminal 54 is formed by the through-hole via 22 penetrating the wiring board 60. A signal or power supplied to the third electrode terminal 34 of the third semiconductor element 32 is the second electrode terminal 34.
If there is a common one with the second electrode terminal 14 of the semiconductor element 12, the third wiring pattern connected to the third electrode terminal 34 is formed by the second bonding portion 18 for the second semiconductor element 12 or the second wiring pattern. It may be connected to the wiring pattern 20. Then, the third bonding wire 38 is sealed with the resin 26 together with the first semiconductor element 64, the second semiconductor element 12, and the second bonding wire 16.
【００１６】以上、本発明の好適な実施の形態について
種々述べてきたが、本発明は上述する実施の形態に限定
されるものではなく、例えばさらに第３の実施の形態の
半導体装置３０の第３半導体素子３２上にさらに１また
は２以上の半導体素子を積み重ねることも考えられる
等、発明の精神を逸脱しない範囲で多くの改変を施し得
るのはもちろんである。Although various preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments. For example, the present invention is not limited to the third embodiment of the semiconductor device 30 of the third embodiment. Of course, many modifications can be made without departing from the spirit of the invention, such as one or more semiconductor elements being stacked on the three semiconductor elements 32.
【００１７】[0017]
【発明の効果】本発明に係る半導体装置または配線基板
を用いると、複数の半導体素子を積層した構造で、配線
基板に搭載することができるから、複数の半導体素子を
配線基板に少ないスペースで搭載可能として、半導体素
子の高密度実装が可能となる。しかも、従来から一般的
に行われているワイヤボンディング法を用いて実現でき
るため、新規な設備投資も少なくてすみ、低コストで半
導体装置を製造できるという効果もある。When the semiconductor device or the wiring board according to the present invention is used, a plurality of semiconductor elements can be mounted on the wiring board in a structure in which a plurality of semiconductor elements are stacked, so that the plurality of semiconductor elements can be mounted on the wiring board in a small space. If possible, high-density mounting of semiconductor elements becomes possible. In addition, since the semiconductor device can be realized by using a wire bonding method which has been generally performed, there is an effect that a new capital investment can be reduced and a semiconductor device can be manufactured at low cost.
【図１】本発明に係る配線基板とそれを用いた半導体装
置の第１の実施の形態の構成を説明するための正面断面
図である。FIG. 1 is a front sectional view illustrating a configuration of a first embodiment of a wiring board and a semiconductor device using the same according to the present invention.
【図２】図１の第１半導体素子の電極端子形成面の第１
電極端子の配置を示す平面図である。FIG. 2 is a view showing a first example of an electrode terminal forming surface of the first semiconductor element of FIG. 1;
It is a top view showing arrangement of an electrode terminal.
【図３】図１の配線基板の外部接続端子側から見た平面
図である。FIG. 3 is a plan view of the wiring board of FIG. 1 as viewed from an external connection terminal side.
【図４】本発明に係る半導体装置の第２の実施の形態の
構成を説明するための正面断面図である。FIG. 4 is a front sectional view illustrating a configuration of a semiconductor device according to a second embodiment of the present invention;
【図５】図４の半導体装置を配線基板側から見た平面図
である。FIG. 5 is a plan view of the semiconductor device of FIG. 4 as viewed from a wiring board side.
【図６】図４の半導体装置を第２半導体素子側から見た
平面図である（モールドする前の状態）。FIG. 6 is a plan view of the semiconductor device of FIG. 4 as viewed from a second semiconductor element side (state before molding).
【図７】本発明に係る半導体装置の第３の実施の形態の
構成を説明するための正面断面図である。FIG. 7 is a front cross-sectional view illustrating a configuration of a semiconductor device according to a third embodiment of the present invention.
【図８】従来の半導体装置の構造を示す正面断面図であ
る。FIG. 8 is a front sectional view showing the structure of a conventional semiconductor device.
１０ 半導体装置 １２ 第２半導体素子 １４ 第２電極端子 １６ 第２ボンディングワイヤ １８ 第２ボンディング部 ２０ 第２配線パターン ２２ スルーホールビア ２４ 接着剤 ２６ 樹脂封止剤 ５２ 貫通穴 ５４ 外部接続端子 ５６ 第１ボンディング部 ５８ 第１配線パターン ６０ 配線基板 ６２ 第１電極端子 ６４ 第１半導体素子 ６６ 第１ボンディングワイヤ ６８ 樹脂 ７２ ランド部 DESCRIPTION OF SYMBOLS 10 Semiconductor device 12 2nd semiconductor element 14 2nd electrode terminal 16 2nd bonding wire 18 2nd bonding part 20 2nd wiring pattern 22 through-hole via 24 adhesive 26 resin sealant 52 through-hole 54 external connection terminal 56 1st Bonding part 58 First wiring pattern 60 Wiring board 62 First electrode terminal 64 First semiconductor element 66 First bonding wire 68 Resin 72 Land part
Claims (3)
貫通穴の開口縁部に形成された第１ボンディング部とを
備えた第１配線パターンが一方の面に形成された配線基
板と、 該配線基板の前記ランド部に接合された外部接続端子
と、 該配線基板の他方の面に電極端子形成面を対向させて、
該電極端子形成面に形成された第１電極端子が前記貫通
穴の内側となるように搭載され、貫通穴を通して第１電
極端子と前記第１ボンディング部とが第１ボンディング
ワイヤにより電気的に接続された第１半導体素子と、 前記貫通穴内部の第１ボンディングワイヤを封止する樹
脂と、 前記配線基板の他方の面に形成され、第２ボンディング
部を備えると共に、配線基板を貫通するスルーホールビ
アによって前記第１配線パターン、前記第１ボンディン
グ部または前記外部接続端子と電気的に接続された第２
配線パターンと、 前記第１半導体素子の背面に電極端子形成面を上にして
搭載され、該電極端子形成面の周縁部に形成された第２
電極端子と前記第２ボンディング部とが第２ボンディン
グワイヤにより電気的に接続された第２半導体素子とを
有し、 前記第１半導体素子、第２半導体素子および第２ボンデ
ィングワイヤを樹脂封止して成ることを特徴とする半導
体装置。A wiring board having a through hole, a first wiring pattern having a land portion and a first bonding portion formed at an opening edge of the through hole formed on one surface; An external connection terminal joined to the land portion of the wiring board, and an electrode terminal forming surface facing the other surface of the wiring board,
The first electrode terminal formed on the electrode terminal forming surface is mounted so as to be inside the through hole, and the first electrode terminal and the first bonding portion are electrically connected to each other by the first bonding wire through the through hole. A first semiconductor element, a resin for sealing a first bonding wire inside the through-hole, and a through-hole formed on the other surface of the wiring board and having a second bonding portion and penetrating the wiring board. A second electrically connected to the first wiring pattern, the first bonding portion or the external connection terminal by a via
A wiring pattern, and a second electrode formed on the back surface of the first semiconductor element, with the electrode terminal formation surface facing upward, and formed on the periphery of the electrode terminal formation surface.
An electrode terminal and the second bonding portion, a second semiconductor element electrically connected by a second bonding wire, and the first semiconductor element, the second semiconductor element, and the second bonding wire are resin-sealed. A semiconductor device comprising:
３ボンディング部を備えると共に、配線基板を貫通する
スルーホールビアによって前記第１配線パターン、前記
第１ボンディング部または前記外部接続端子と電気的に
接続された第３配線パターンと、 前記第２半導体素子の電極端子形成面に、周縁部に第３
電極端子が形成された電極端子形成面を上にして搭載さ
れ、該第３電極端子と前記第３ボンディング部とが第３
ボンディングワイヤにより電気的に接続された第３半導
体素子とを有し、 前記第３ボンディングワイヤは、前記第１半導体素子、
第２半導体素子および第２ボンディングワイヤと共に樹
脂封止されていることを特徴とする請求項１記載の半導
体装置。And a third bonding portion formed on the other surface of the wiring board, wherein the third bonding portion is provided, and the first wiring pattern, the first bonding portion, or the external connection terminal is connected to the wiring substrate by a through-hole via. A third wiring pattern that is electrically connected; and a third wiring pattern on the electrode terminal formation surface of the second semiconductor element,
The electrode terminal forming surface on which the electrode terminal is formed is mounted upward, and the third electrode terminal and the third bonding portion are connected to each other by the third bonding.
A third semiconductor element electrically connected by a bonding wire, wherein the third bonding wire is the first semiconductor element,
2. The semiconductor device according to claim 1, wherein the semiconductor device is sealed with a resin together with the second semiconductor element and the second bonding wire.
穴の開口縁部に形成された第１ボンディング部とを備え
た第１配線パターンが形成され、 他方の面に、第２ボンディング部を備えると共に、前記
一方の面から前記他方の面に貫通するスルーホールビア
によって前記第１配線パターン、前記第１ボンディング
部または前記外部接続端子と電気的に接続された第２配
線パターンが形成されて成ることを特徴とする配線基
板。3. A first wiring pattern including a through hole formed on one surface and a land portion for connecting an external connection terminal and a first bonding portion formed at an opening edge of the through hole. A second bonding portion is provided on the other surface, and the first wiring pattern, the first bonding portion or the external connection terminal is electrically connected to the first wiring pattern by a through-hole via penetrating from the one surface to the other surface. A second wiring pattern connected to the wiring board is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12191699A JP3615672B2 (en) | 1999-04-28 | 1999-04-28 | Semiconductor device and wiring board used therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12191699A JP3615672B2 (en) | 1999-04-28 | 1999-04-28 | Semiconductor device and wiring board used therefor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000315765A true JP2000315765A (en) | 2000-11-14 |
| JP3615672B2 JP3615672B2 (en) | 2005-02-02 |
Family
ID=14823096
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12191699A Expired - Fee Related JP3615672B2 (en) | 1999-04-28 | 1999-04-28 | Semiconductor device and wiring board used therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3615672B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002208656A (en) * | 2001-01-11 | 2002-07-26 | Mitsubishi Electric Corp | Semiconductor device |
| JP2002231881A (en) * | 2001-02-02 | 2002-08-16 | Oki Electric Ind Co Ltd | Semiconductor chip package |
| JP2007266567A (en) * | 2006-03-29 | 2007-10-11 | Hynix Semiconductor Inc | Semiconductor package with high speed and high performance |
| JP2009026792A (en) * | 2007-07-17 | 2009-02-05 | Hitachi Ltd | Semiconductor device |
| CN112864121A (en) * | 2021-01-14 | 2021-05-28 | 长鑫存储技术有限公司 | Chip structure, packaging structure and manufacturing method thereof |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102190382B1 (en) | 2012-12-20 | 2020-12-11 | 삼성전자주식회사 | Semiconductor package |
-
1999
- 1999-04-28 JP JP12191699A patent/JP3615672B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002208656A (en) * | 2001-01-11 | 2002-07-26 | Mitsubishi Electric Corp | Semiconductor device |
| JP2002231881A (en) * | 2001-02-02 | 2002-08-16 | Oki Electric Ind Co Ltd | Semiconductor chip package |
| JP4571320B2 (en) * | 2001-02-02 | 2010-10-27 | Ｏｋｉセミコンダクタ株式会社 | Semiconductor chip package |
| JP2007266567A (en) * | 2006-03-29 | 2007-10-11 | Hynix Semiconductor Inc | Semiconductor package with high speed and high performance |
| JP2009026792A (en) * | 2007-07-17 | 2009-02-05 | Hitachi Ltd | Semiconductor device |
| CN112864121A (en) * | 2021-01-14 | 2021-05-28 | 长鑫存储技术有限公司 | Chip structure, packaging structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3615672B2 (en) | 2005-02-02 |
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