JP2000315707A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accomplish a highly reliable semiconductor device on which the fatigue life of a solder bump can be extended. SOLUTION: The diameter of the area equal to the area of the part, which comes in contact with the pad 9 or the pad 10 of a lead-free solder bump 7, is set as A size and the diameter of the sphere of the cubic volume equal to the cubic volume of the lead-free solder bump 7 is set as B size. In this case, when the A size of the solder bump 7 is formed in the size which is 0.8 to 1.1 times of the B size, the contact surface of the solder bump 7 and the pads 9 and 10 is increased, and the intensity of junction interface is increased. Also, in proportion to the A-size becoming larger, it becomes cylindrical shape, the regidity of the solder bump 7 itself becomes higher, and the amount of thermal deformation added to the solder bump 7 becomes small.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device electrically and mechanically connected to a printed circuit board using solder bumps, and more particularly to a semiconductor device suitable for improving fatigue life when using lead-free solder. About.

[0002]

2. Description of the Related Art A semiconductor device electrically and mechanically connected to a wiring board by using solder bumps is disclosed in, for example, Japanese Patent Application Laid-Open No. 62-73639.

[0003] Conventionally, lead-containing solder has been mainly used for connecting electronic components to a substrate. However, there is a concern that lead ions contained in the solder will flow out of the discarded electronic equipment, causing contamination of groundwater veins and rivers, and furthermore, effects on human bodies.

[0004] Therefore, it has become necessary to perform connection using lead-free solder containing no lead. As a material for this lead-free solder, as a result of studying various aspects such as environmental load, bondability, cost, reliability, etc., based on tin silver eutectic solder, bismuth, copper, Materials having a composition to which indium or the like is added are becoming promising.

[0005]

However, the tin-silver eutectic solder described above has a connection reliability equal to or higher than that of the conventional tin-lead eutectic solder, but the material is harder than the tin-lead eutectic solder and the melting point is also higher. Since the temperature rises by about 40 ° C., heat resistance cannot be secured for some electronic components and wiring boards, and some of them may break down during solder mounting. Therefore, the mounting temperature of the lead-free solder is preferably equal to that of the conventionally used tin-lead eutectic solder.

In order to lower the melting point of the tin-silver eutectic solder,
Although the addition of bismuth is effective, the material tends to be hard and brittle with an increase in the amount of bismuth, and the low cycle fatigue life and the connection strength at the bonding interface are reduced.

In the mounting method using solder bumps, which has been increasing with the recent increase in the density of electronic components, destruction occurs near the interface between the solder bumps and the pads formed on the electronic component or the wiring board.

[0008] Lead-free solder is harder than conventional tin-lead eutectic solder, and the strength of the solder base material may be higher than the strength of the interface. Prevention is an important issue.

An object of the present invention is to realize a highly reliable semiconductor device with improved fatigue life of solder bumps.

[0010]

The above object can be achieved by optimizing the relationship between the area of the lead-free solder bump in contact with the pad formed on the electronic component and the wiring board and the volume of the lead-free solder bump. .

The above object can also be achieved by optimizing a contact angle between a lead-free solder bump and a pad formed on an electronic component or a wiring board.

That is, in order to achieve the above object, the present invention is configured as follows. (1) In a semiconductor device including a solder bump, an electronic component having the solder bump, and a wiring board on which one or more of the electronic component is mounted, the semiconductor device is formed on the solder bump, the electronic component, or the wiring board. The diameter of a circle having an area equal to the area of the portion in contact with the pad is 0.8 times or more the diameter of a sphere having a volume equal to the volume of the solder bump.
It is less than 1 time.

[0013] According to the above feature, the distortion generated near the interface between the solder bump and the pad due to thermal deformation can be reduced.
Thermal fatigue damage of the solder bumps can be suppressed.

(2) In a semiconductor device including a solder bump, an electronic component having the solder bump, and a wiring board on which one or more of the electronic component is mounted, the above-mentioned solder bump is in contact with the solder bump. The contact angle with the electronic component or the pad formed on the wiring board is 55
It is not less than 90 ° and not more than 90 °.

Thus, it is possible to prevent the concentration of strain near the joint end between the solder bump and the pad, and to suppress the fatigue breakdown of the solder bump.

(3) Preferably, the above (1) or (2)
, The material of the solder bump is lead-free solder.

[0017]

Embodiments of the present invention will be described below with reference to the accompanying drawings. (First Embodiment) FIG. 1 is a schematic sectional view of a semiconductor device according to a first embodiment of the present invention.

The semiconductor device according to the first embodiment of the present invention includes a BGA (ball grid array) 1 and a tape BGA.
2. An electronic component having a lead-free solder bump 7, such as a CSP (chip size package) 3, a WPP (wafer process package) 4, or a semiconductor element 5, connected to a wiring board 6 via the lead-free solder bump 7. It is.

Here, the material of the lead-free solder bump 7 is preferably a tin-silver eutectic solder having excellent thermal fatigue characteristics. The melting point of this alloy is about 220 ° C. In order to lower the melting point and improve the wettability, bismuth, indium,
Copper or the like may be added.

From the viewpoint of lowering the melting point, an alloy in which bismuth is added to a tin-silver binary eutectic alloy in an amount of 3% or more is preferable. That is, about 1 to 5% of silver, 3% or more of bismuth, and the rest are tin and 1% or less of trace addition elements. In order to further lower the melting point and improve the wettability, indium, copper, and the like may be added.

Specifically, Sn-3Ag-5Bi, Sn
-2.8Ag-15Bi, Sn-1Ag-57Bi, etc., which contain a trace addition element of 1% or less. Each melting point is about 210 ° C, about 180
° C, about 140 ° C. Further, although not preferable in view of the influence on the environment, a tin-lead eutectic alloy which is conventionally widely used and has excellent bonding properties and fatigue life characteristics may be used.

As a method of forming the lead-free solder bump 7, a lead-free solder is supplied onto the pad 9 of the electronic component 8 by a method such as solder ball, solder paste, or plating.
The entire electronic component is formed by heating to a temperature higher than the melting point of the lead-free solder by a method such as reflow heating.

The electronic components 1 to 5 are replaced with lead-free solder bumps 7
When the connection is made to the wiring board 6, the same type of lead-free solder is supplied to the pads 10 of the wiring board 6 by means such as paste or plating. Then, the position of the lead-free solder bump 7 is adjusted, and the lead-free solder bump 7 and the wiring board 6 are connected at an appropriate temperature.

Accordingly, the volume of the lead-free solder bump 7 after connection with the wiring board 6 is supplied to the pad 10 by means such as paste or plating at the time of connection and the amount of solder supplied when the lead-free solder bump 7 is formed. It is the sum of the solder amount.

Examples of the material of the wiring board 6 include a glass epoxy laminated board and a relatively inexpensive paper phenol board. In addition, there are a built-up board suitable for high-density mounting, a ceramic board having excellent solder connection reliability, and the like, and the material of the wiring board 6 is not particularly limited.

FIG. 2 is an enlarged view of the vicinity of the lead-free solder bump 7 of the semiconductor device according to the first embodiment of the present invention. The lead-free solder bumps 7 are connected to the pads 9 of the electronic component 8.
And the pad 10 of the wiring board 6. Electronic components 8
In addition, a solder resist 11 for protecting the wiring is applied on the pad existing surface side of the wiring board 6.

The solder bumps 7 and the pads 9 and 9 depend on the application area of the solder resist 11 and the size of the pads 9 and 10.
2 (a) to 2 (c) show the shapes in the vicinity of the connection interface with 10.
The shape is shown below. There is no problem even if the shape of the solder bump 7 near the pad connection interface is different between the electronic component 8 side and the wiring board 6 side.

FIG. 2A shows a case where the solder resist 11 covers a part (peripheral portion) of the pads 9 and 10.
There is an advantage that the bonding strength between the pads 9 and 10 and the wiring board 6 can be increased, but the strength of the interface between the solder bumps 7 and the pads 9 and 10 is somewhat weak.

FIG. 2B shows a case where the solder resist 11 does not cover the pads 9 and 10, and the lead-free solder 7 is wet to the side surfaces of the pads. Due to the wetting of the solder on the side surfaces of the pads, the strength of the interface between the solder bumps 7 and the pads 9, 10 is high, and the fatigue life is relatively good.

FIG. 2C shows a case where the solder resist 11 does not cover the pads 9 and 10, and the lead-free solder 7 does not wet the side surfaces of the pads.

Pad 9 or 1 of lead-free solder bump 7
FIG. 2 shows the diameter A (hereinafter, referred to as A dimension) of a circle having an area equal to the area of the portion in contact with 0. FIG. 2 shows the electronic component 8.
Although only the side is shown, the same applies to the wiring board 6 side.

In the case of FIG. 2A, the dimension A is substantially equal to the opening diameter of the solder resist 11. In the case of FIG. 2B, the dimension A is substantially equal to the diameter of the pad 9 or 10. In the case of FIG. 2C, the dimension A is the pad 9 or 1
0 is smaller than the diameter.

The diameter B of a sphere having a volume equal to the volume of the lead-free solder bump 7 is defined as B dimension. The present inventor has determined that the above three types of bump shapes (FIG. 2A,
For (b) and (c)), the results of examining the relationship between the fatigue life ratio of the lead-free solder bump and the value C obtained by dividing the A dimension by the B dimension (hereinafter referred to as C value) by experiments and numerical analysis. Is shown in FIG. Here, the fatigue life ratio is a value obtained by dividing the fatigue life at each C value (at the time when electrical disconnection occurs) by the allowable value of the fatigue life.

In any of the above three cases,
As shown in FIG. 3, the dimension A is at least 0.8 times the dimension B,
It was found that the fatigue life exceeded the allowable value. Further, C
It was found that when the value was 0.8 or more, the effect of improving the fatigue life of the C value was increased.

This is considered to be due to a combined effect of the following causes. That is, as the dimension A increases, the contact area between the lead-free solder bump 7 and the pads 9 and 10 increases, so that the strength of the bonding interface increases.

Further, as the dimension A increases, the difference between the dimension A and the maximum outer diameter of the solder bump 7 decreases, and the shape approaches a cylindrical shape having a large diameter and a small height. Therefore, the rigidity of the solder bump 7 itself increases,
The amount of thermal deformation assigned to the electronic component 8 and the wiring board 6 increases. As a result, the amount of thermal deformation applied to the solder bump 7 is reduced.

In order to avoid stress concentration on either the electronic component 8 or the wiring board 6, it is desirable that the A dimension of the solder bump 7 on the electronic component 8 side be equal to the A dimension on the wiring board 6 side. If different, the smaller of the A dimensions is B
What is necessary is just 0.8 times or more and 1.1 times or less of the dimension. This is because the smaller A dimension of the electronic component 8 or the wiring board 6 is smaller than the larger B dimension by 0.8 times the smaller dimension of the electronic component 8 or the wiring board 6 because the smaller dimension of the electronic component 8 tends to be broken first. At least 1.1 times.

The present inventor has clarified that when the dimension A is larger than 1.1 times the dimension B, the amount of solder supplied is small, so that a bump having a good shape cannot be formed.

As described above, according to the first embodiment of the present invention, the solder bump 7 is formed so that the dimension A is 0.8 times or more and 1.1 times or less the dimension B. The contact area between the pad 7 and the pads 9 and 10 increases, and the strength of the bonding interface increases. Also, as the A dimension increases,
As the shape approaches the column shape, the rigidity of the solder bump 7 itself increases, and the amount of thermal deformation applied to the solder bump 7 decreases.

Therefore, the fatigue life of the solder bump is improved, and a highly reliable semiconductor device can be realized.

(Second Embodiment) FIG. 4 is a sectional view of a main part of a semiconductor device according to a second embodiment of the present invention. The main part shown in FIG. 4 has the same shape of the solder bump 7 as that of FIG.
It is characterized in that the contact angle with 0 is 55 ° or more and 90 ° or less.

Here, the solder bumps 7 and the pads 9, 10
As shown in FIG. 4, the contact angle is defined at a position 50 μm away from the joint end between the lead-free solder bump 7 and the pad 9 or the pad 10. That is, the solder bump 7
If the point where a circle having a radius of 0.05 mm centered on the joint end O between the pad 9 and the pad 9 contacts the surface of the pad 9 or 10 is α, and the point where the circle contacts the solder bump 7 is β, a straight line is obtained. The angle between O-α and the straight line O-β is defined as a contact angle.

FIG. 5 is a graph showing the relationship between the fatigue life ratio and the above-mentioned contact angle, which were clarified by experiments and analysis by the present inventors. Here, the fatigue life ratio is a value obtained by dividing the fatigue life at each contact angle by the allowable value of the fatigue life.

The joint end is a stress singular field, and its singularity depends on the contact angle. However, the contact angle dependence of the stress singularity was not clear for a material such as lead-free solder which is liable to undergo plastic deformation.

As shown in FIG. 5, the study by the present inventor has revealed that in the case of lead-free solder, the specificity is reduced when the contact angle is 55 ° or more, and exceeds the allowable fatigue life. Further, it has been found that when the contact angle is 55 ° or more, the effect of improving the fatigue life of the contact angle increases.

Here, when the contact angle is 90 ° or more, since the strain concentration at the joint end is small, it is preferable from the viewpoint of fatigue life, but it is difficult to realize by a generally performed solder joint process.

As described above, the contact angle suitable for improving the fatigue life of the lead-free solder bump is 55 ° or more and 90 ° or less.

As described above, according to the second embodiment of the present invention, since the contact angle between the solder bump 7 and the pads 9 and 10 is formed to be 55 ° or more and 90 ° or less, the solder bump The fatigue life is improved, and a highly reliable semiconductor device can be realized.

The shape of the solder bumps 7 in the first and second embodiments of the present invention is determined by optimizing the amount of solder supplied, the bump pressing load, the solder resist opening diameter, the pad diameter, and the like. realizable.
The shape of the solder bump 7 is determined mainly by the balance between the surface tension of the molten solder and the external force applied to the bump 7.

Therefore, the shape of the solder bump can be predicted by an analysis based on the surface tension analysis of the liquid. This analysis technique is described in the following literature. Reference 1, Wassink, RJ, Takemoto et al., Soldering in Electronics, Chapter 2, (1986), Nikkan Kogyo Shimbun. Reference 2, Borgesen, P., et al., Mechanical Design Co
nsideration for AreaArray Solder Joints: IEEE Tran
sactions on Components, Hybrids and Manufacturing
Technology, Vol. 16, No. 5, 523 (1993).

Further, the shape obtained by combining the first and second embodiments of the present invention described above, that is, a portion in contact with the lead-free solder bump and the electronic component and the pad formed on the wiring board. The diameter of a circle having an area equal to the area of the ball is 0.8 to 1.1 times the diameter of a sphere having a volume equal to the volume of the lead-free solder bump, and the contact angle between the solder bump and the pad is 55 ° or more 90
° or less.

Further, the above-described example is an example in which the present invention is applied to lead-free solder. However, the present invention can be applied to lead-containing solder, and the fatigue life can be improved. it can.

[0053]

As described above, according to the present invention, by optimizing the volume of the solder bump and the area of the portion in contact with the pad formed on the electronic component and the wiring board, the solder bump is improved. It is possible to improve the fatigue life of the bump without increasing the cost.

Further, the fatigue life can be improved by optimizing the contact angle between the solder bump and the pad formed on the electronic component and the wiring board.

As a result, the fatigue life of the solder bump is improved, and a highly reliable semiconductor device can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is an enlarged view near a solder bump of the semiconductor device according to the first embodiment;

FIG. 3 is a graph showing the effect of the relationship between the area of a lead-free solder bump in contact with a pad and the volume of the lead-free solder bump on fatigue life.

FIG. 4 is a sectional view showing a solder bump structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a graph showing the effect of a contact angle between a lead-free solder bump and a pad on fatigue life.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 electronic component (BGA) 2 electronic component (tape BGA) 3 electronic component (CSP) 4 electronic component (WPP) 5 electronic component (semiconductor element) 6 wiring board 7 lead-free solder bump 8 electronic component 9 electronic component pad 10 wiring Substrate pad 11 Solder resist

Continuing from the front page (72) Inventor Kiyomi Kojima 502, Kandachicho, Tsuchiura-shi, Ibaraki Pref. Machinery Research Laboratories, Hitachi, Ltd. (72) Inventor Naotaka Tanaka 502 Kandachi-cho, Tsuchiura-shi, Ibaraki F-term in Machinery Research Laboratory, Hitachi, Ltd. (Reference) 5F044 KK01 KK11 LL01 QQ02 RR01

Claims (3)

[Claims] 1. A semiconductor device comprising: a solder bump; an electronic component having the solder bump; and a wiring board on which one or more of the electronic component is mounted. A semiconductor device, wherein a diameter of a circle having an area equal to an area of a portion in contact with a formed pad is 0.8 to 1.1 times a diameter of a sphere having a volume equal to the volume of the solder bump. . 2. A semiconductor device comprising a solder bump, an electronic component having the solder bump, and a wiring board on which one or more of the electronic component is mounted, wherein the solder bump is in contact with the electronic component. A semiconductor device, wherein a contact angle with a component or a pad formed on the wiring board is 55 ° or more and 90 ° or less. 3. The semiconductor device according to claim 1, wherein the material of the solder bump is a lead-free solder.