JP2000315661A - Manufacture for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To fine a semiconductor device by a method, wherein a gate electrode itself is reduced, and a space between the gate electrodes is narrowed. SOLUTION: In this manufacture, masking cobalt silicide films 7a, 7b, until a surface of a silicon oxide film 2 is exposed, sidewall silicon oxide films 9a, 9b, a silicon oxide film 4, and a polycrystalline silicon film 3 are etched and removed. Thus, a gate electrode composed of a polycide film containing the cobalt silicide films 7a, 7b and polycrystalline silicon films 3a, 3b is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device having a polycide wiring.

[0002]

2. Description of the Related Art Conventionally, miniaturization and densification of semiconductor elements have been promoted, and further miniaturization and densification of semiconductor elements will tend to continue. Currently,
2. Description of the Related Art Semiconductor devices such as memory devices and logic devices designed according to the size rule of 0.15 μm to 0.25 μm have been developed and manufactured. In such a semiconductor device, reducing the width of the gate electrode, the interval between the gate electrodes, and reducing the thickness of the gate electrode are important issues.

However, when the thickness of the gate electrode is reduced, the resistance of the gate electrode is naturally increased. Therefore, in order to form a gate electrode having a low resistance even when the film thickness is reduced, a technique of using a polycide material containing a low-resistance metal having a low resistance as a material for the gate electrode becomes important.

Here, a method of manufacturing a semiconductor device using a conventional polycide wiring will be described with reference to FIGS. In a conventional method of manufacturing a semiconductor device, first, a LOCOS (LOCal Oxidation of Silico) is formed on a silicon substrate 101.
An element isolation region (not shown) is formed by an n) method or a trench isolation method.

Next, the silicon substrate 101 in the element formation region
The silicon oxide film 102 is formed by thermal oxidation from the surface of the substrate to a depth of 5 nm to 10 nm. Thereafter, a phosphorus-doped polycrystalline silicon film 103 having a film thickness of 50 nm to 200 nm is formed on the silicon oxide film 102 by a chemical vapor deposition method, that is, CVD (Chemical Vapor Depositio).
Formed by the n) method.

Then, a tungsten silicide film 1 having a thickness of 50 nm to 200 nm is formed on the polycrystalline silicon film 103.
07 is formed. Next, the tungsten silicide film 10
7, a silicon oxide film 104 having a thickness of about 100 nm
Then, a silicon nitride film 110 is formed. Thereafter, a photolithography process is performed to form resist films 105a and 105b having a predetermined pattern on the silicon nitride film 110, so as to be in a state as shown in FIG.

[0007] Next, as shown in FIG.
05a, 105b as a mask, silicon oxide film 104
And silicon nitride film 110 with predetermined patterns of silicon oxide films 104a and 104b and silicon nitride film 11
Dry etching is performed on 0a and 110b. Thereafter, using the predetermined silicon oxide films 104a and 104b and the silicon nitride films 110a and 110b as a hard mask, the polycrystalline silicon film 103 and the tungsten silicide film 107 are used.
24, polycrystalline silicon films 103a and 103b and tungsten silicide films 107a and 107b having predetermined patterns are formed as shown in FIG. Thereby, the polycrystalline silicon films 103a, 103
b and tungsten silicide films 107a and 107b
Electrodes 137a and 137b of a polycide film made of
Is formed. Next, as shown in FIG. 25, the interlayer oxide film 108 is buried so as to bury the gate electrodes 137a and 137b.
Is deposited on the silicon oxide film 102.

[0008]

In the method of forming the gate electrodes 137a and 137b as described above, the gate electrode 13
7a and 137b, a silicon oxide film 104 is formed on the tungsten silicide films 107a and 107b.
a, 104b and silicon nitride films 110a, 110b
Is formed in a state where the silicon oxide film 108 remains, that is, the interlayer insulating film 108 is buried in a gap having a large aspect ratio. Therefore, if the distance between the gate electrode 137a and the gate electrode 137b is small, as shown in FIG. 25, the oxide film 108 is not buried between the gate electrode 137a and the gate electrode 137b, and a void 108a is formed. An undesired phenomenon occurs. The void 108a adversely affects transistor characteristics and a layer deposited in a later step. As a result, the gate electrodes 137a,
The restriction that the interval between the 137b is not less than a predetermined width is imposed, which hinders miniaturization of the semiconductor device.

In the above-described method of forming a gate electrode, a gate electrode having a width smaller than the minimum width of the resist films 105a and 105b cannot be formed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to reduce the size of a gate electrode itself and the size of a space between gate electrodes so as to reduce the size of a semiconductor device. This is to achieve miniaturization.

[0011]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of:
The selectivity under the predetermined etching condition is the first on the film.
Forming a second film larger than the film, etching the second film in a predetermined region until the upper surface of the first film is exposed,
Forming a predetermined opening, depositing a refractory metal film so as to cover at least the exposed surface of the first film, and reacting the first film with the refractory metal film to form a refractory metal silicide film And removing the unreacted refractory metal film and etching and removing the second film and the first film using the refractory metal silicide film as a mask.

By using such a manufacturing method,
Since the second film and the first film are etched using the refractory metal silicide film as a mask, a wiring layer or a gate made of a polycide film is left without leaving a film serving as a hard mask on the polycide film including the refractory metal silicide film. Electrodes can be formed. Accordingly, in the case of a pattern in which two or more wiring layers or gate electrodes are formed close to each other, compared to a conventional manufacturing method in which a film serving as a hard mask remains on the wiring layer or gate electrode. In addition, the aspect ratio of the buried portion between the wiring layers or the gate electrodes can be reduced. Therefore, in the step of forming an interlayer insulating film that embeds the wiring layer or the gate electrode, between the wiring layer or the gate electrode, which occurs due to an increase in the aspect ratio of the gap between the wiring layer or the gate electrode. An undesired phenomenon that a film to be an interlayer insulating film is not buried and a void is formed is suppressed. as a result,
Even when the distance between the wiring layers or the gate electrodes is small, the subsequent steps of forming the interlayer insulating film can be performed accurately, so that it is possible to form a miniaturized semiconductor device as compared with the related art. Become.

According to a second aspect of the present invention, in the method for manufacturing a semiconductor device according to the present invention, the second film having a higher selectivity under a predetermined etching condition than the first film is formed on the first film containing silicon.
The step of forming a film, the step of etching the second film in a predetermined region until the upper surface of the first film is exposed, and the step of forming a predetermined opening; A step of forming a third film larger than the first film, a step of etching the third film until a surface of the first film is exposed, and forming a side wall film on a side wall of the second film; Depositing a refractory metal film so as to cover the exposed surface, reacting the first film with the refractory metal film to form a refractory metal silicide film, and removing unreacted refractory metal film And a step of etching and removing the second film, the side wall film, and the first film using the refractory metal silicide film as a mask.

By using such a manufacturing method,
Since the refractory metal silicide film is formed with the sidewall film, the refractory metal silicide film can be formed in a pattern having a width smaller than the minimum width of the pattern that can be formed using the opening pattern formed in the second film. . Therefore, the wiring layer or the gate electrode can be miniaturized. as a result,
The semiconductor device can be miniaturized as compared with the case where the sidewall film is not used.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect, in the step of forming the predetermined opening, the predetermined opening is formed so as to have an adjacent opening region. Is formed.

As described above, when the predetermined openings for forming the wiring layers or the gate electrodes are formed adjacent to each other, the above-described manufacturing method is used to reduce the distance between the wiring layers or the gate electrodes. In addition, the following operation and effect can be obtained in addition to the operation and effect similar to the method of manufacturing a semiconductor device according to the above-mentioned claim 1 in which the subsequent steps after the formation of the interlayer oxide film can be performed accurately.

That is, according to the manufacturing method of the third aspect, the width of the wiring layer or the gate electrode can be made smaller by the width of the side wall film, so that the wiring layer or the gate electrode can be formed closer to each other. In addition, the semiconductor device can be further miniaturized as compared with the case where the sidewall film is not used.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the second aspect, wherein the third film has a selectivity under a predetermined etching condition higher than that of the second film. After the step of forming the side wall film on the side wall of the first film using a large material, before the step of depositing the refractory metal, a step of removing the side wall film in a part of the opening is further provided. .

By using such a manufacturing method,
Since the selectivity of the third film under the predetermined etching condition is larger than that of the second film, only the third film in the predetermined region is removed by etching. Therefore, since the refractory metal silicide film is formed in the wiring layer or the gate electrode formed in the region other than the predetermined region with the side wall film, the width is smaller than the minimum width in which the pattern of the first film can be formed. A refractory metal silicide film is formed in a width pattern. Therefore, a wiring layer or a gate electrode formed in a region other than the predetermined region is miniaturized as compared with a case where no sidewall film is provided. In the predetermined region, the refractory metal film is formed in a state where the side wall film is removed, so that the refractory metal silicide film is formed to have the same width as the opening pattern is formed in the second film, and the etching is performed. Is performed. Thereby, the wiring layer or the gate electrode is formed with the width of the opening pattern formed in the silicon nitride film. Therefore, when the semiconductor device has a plurality of element formation regions, wiring layers or gate electrodes with different widths can be formed in each region in one step. As a result, wiring layers or gate electrodes having different widths can be simultaneously formed in different regions, so that the number of manufacturing steps of the semiconductor device is reduced.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) A method of manufacturing a semiconductor device according to Embodiment 1 of the present invention will be described with reference to FIGS. In the method of manufacturing a semiconductor device according to the present embodiment, first, an element isolation region (not shown) is formed on a silicon substrate 1 by a LOCOS method or a trench isolation method.

Next, a silicon oxide film 2 is formed by thermal oxidation from the surface of the silicon substrate 1 in the element formation region to a depth of 5 nm to 10 nm. Then, the silicon oxide film 2
A polycrystalline silicon film 3 doped with phosphorus having a thickness of 50 nm to 200 nm is formed thereon by a chemical vapor deposition method,
It is formed by the VD method.

Next, TEOS (Tetra Etyle Ortho S)
ilicate) on the polycrystalline silicon film 3 to be used as salicide protection and having a higher etching rate than the polycrystalline silicon film 3 under predetermined etching conditions, that is, a film having a large selectivity. A silicon oxide film 4 having a thickness of 50 nm is formed. Thereafter, a photolithography process is performed to form a resist film 5 having a predetermined pattern having an opening formed close to the silicon oxide film 4. Next, the silicon oxide film 4 is dry-etched using the resist film 5 as a mask, an opening having a predetermined pattern is provided, and the upper surface of the polycrystalline silicon film 3 is exposed to obtain the state shown in FIG. After that, the resist film 5 is removed.

Next, as shown in FIG. 2, a cobalt film 6, which is a refractory metal, is deposited by a sputtering method so as to cover the surfaces of the polycrystalline silicon film 3 and the silicon oxide film 4.
Thereafter, by performing RTA (Rapid Thermal Anneal), the polycrystalline silicon film 3 and the cobalt film 6 react with each other to form cobalt silicide films 7a and 7b. Thereafter, the unreacted cobalt film 6 present on the surface of the silicon oxide film 4 is removed by using a mixed solution of phosphoric acid, acetic acid and ammonia to obtain the state shown in FIG. Next, the resistance of the cobalt silicide films 7a and 7b is reduced by performing RTA again.

Then, as shown in FIG. 4, the silicon oxide film 2 is formed using the cobalt silicide films 7a and 7b as a mask.
The silicon oxide film 4 and the polycrystalline silicon film 3 are removed by etching until the surface of the semiconductor device is exposed, thereby forming gate electrodes 37a and 37b made of a polycide film including the cobalt silicide films 7a and 7b and the polycrystalline silicon films 3a and 3b. I do. Next, as shown in FIG. 5, the gate electrodes 37a,
An interlayer oxide film 8 is deposited on the silicon oxide film 2 so as to bury 37b.

By using such a manufacturing method,
Gate electrodes 37a and 37b can be formed on polycrystalline silicon films 3a and 3b and cobalt silicide films 7a and 7b without leaving a film serving as a hard mask. Thus, in the case of the present embodiment in which the gate electrodes 37a and 37b are formed close to each other by two or more, the gate electrode 3
As compared with the conventional manufacturing method in which a film serving as a hard mask remains on the gate electrodes 37a and 37b,
The aspect ratio of the buried portion between 7b can be reduced. Therefore, in the step of forming the interlayer oxide film 8 that buries the gate electrodes 37a and 37b, the film that becomes the interlayer oxide film 8 is not buried between the gate electrodes 37a and 37b, and there is an inconvenience that a void is formed. The phenomenon is suppressed. As a result, even when the distance between the gate electrodes 37a and 37b is small, the subsequent steps after the formation of the interlayer oxide film 8 can be performed accurately, so that the semiconductor device can be further miniaturized.

(Embodiment 2) Next, a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention will be described with reference to FIGS. In the method of manufacturing a semiconductor device according to the present embodiment, the steps up to the step of dry-etching silicon oxide film 4 with resist film 5 to form an opening close to a predetermined pattern and exposing the upper surface of polycrystalline silicon film 3 are performed. The same steps as in the first embodiment are performed.

Next, after removing the resist film 5 in the state of FIG. 1, as shown in FIG. 6, the selectivity is higher than that of the polycrystalline silicon film 3 so as to cover the polycrystalline silicon film 3 and the silicon oxide film 4. A large silicon oxide film 9 is deposited. Thereafter, as shown in FIG. 7, the silicon oxide film 9 is etched back until the surface of the polycrystalline silicon film 3 is exposed, and sidewall silicon oxide films 9a and 9b are formed on the sidewalls of the opening formed in the silicon oxide film 4. Form. Next, as shown in FIG. 8, a cobalt film 6, which is a refractory metal, is deposited so as to cover the surfaces of the polycrystalline silicon film 3, the silicon oxide film 4, and the side wall silicon oxide films 9a and 9b. Thereafter, by performing RTA, the polycrystalline silicon film 3 and the cobalt film 6 are reacted to form cobalt silicide films 7a and 7b.

Next, as shown in FIG. 9, the unreacted cobalt film 6 existing on the surfaces of the silicon oxide film 4 and the side wall silicon oxide films 9a and 9b is removed using a mixed solution of phosphoric acid, acetic acid and ammonia. Remove. Thereafter, the resistance of the cobalt silicide films 7a and 7b is reduced by performing RTA again. Next, as shown in FIG. 10, using the cobalt silicide films 7a and 7b as a mask, the silicon oxide film 4 and the polycrystalline silicon film 3 are removed by etching until the surface of the silicon oxide film 2 is exposed.
Gate electrode 3 made of a polycide film including cobalt silicide films 7a and 7b and polycrystalline silicon films 3a and 3b
7a and 37b are formed. Next, as shown in FIG.
An interlayer oxide film 8 is deposited on the silicon oxide film 2 so as to bury the gate electrodes 37a and 37b.

By using such a manufacturing method,
As in the first embodiment, the gate electrodes 37a, 37b
The aspect ratio of the buried portion between them becomes smaller.
As a result, the film that becomes the interlayer oxide film 8 is not buried between the gate electrodes 37a and 37b, and an undesired phenomenon such as formation of a void is suppressed. As a result, the gate electrodes 37a and 37b can be formed close to each other, so that a miniaturized semiconductor device can be formed.

Further, since the cobalt silicide films 7a and 7b are formed with the side wall oxide films 9a and 9b, the cobalt silicide film has a pattern narrower than the minimum width of the pattern that can be formed using the silicon oxide film 4. 7a, 7
b can be formed. Therefore, since the polysilicon films 3a and 3b are etched using the narrow cobalt silicide films 7a and 7b, the gate electrode 3 made of a polycide film is used.
7a and 37b can be further miniaturized. As a result, the semiconductor device can be further miniaturized as compared with the case where the side wall films 9a and 9b are not used.

(Embodiment 3) Next, a method of manufacturing a semiconductor device according to Embodiment 3 of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. First, LOCOS is applied to the silicon substrate 1.
An element isolation region (not shown) is formed by a method or a trench isolation method.

Next, a silicon oxide film 2 including a gate oxide film is formed to a depth of 5 nm to 100 nm from the surface of the silicon substrate 1 in the element formation region. Thereafter, a polycrystalline silicon film 3 doped with phosphorus having a thickness of 50 nm to 200 nm is formed on the silicon oxide film 2 by a chemical vapor deposition method, that is, a CVD method.

Next, a silicon nitride film 10 having a higher selectivity than the polycrystalline silicon film 3 used as salicide protection is formed on the polycrystalline silicon film 3. Thereafter, photolithography is performed to form a resist film 5 having a predetermined pattern on the silicon nitride film 10. Next, the silicon nitride film 10 is dry-etched with the resist film 5 to form two openings having a predetermined pattern close to each other, exposing the upper surface of the polycrystalline silicon film 3 to the state shown in FIG. Next, the resist film 5 is removed. Thereafter, as shown in FIG. 13, a silicon oxide film 9 having a higher selectivity than silicon nitride film 10 and polycrystalline silicon film 3 is deposited so as to cover the surfaces of polycrystalline silicon film 3 and silicon nitride film 10. Thereafter, as shown in FIG. 14, the silicon oxide film 9 is etched back until the surface of the polycrystalline silicon film 3 is exposed, and side wall silicon oxide films 9a and 9b are formed on the side walls of the opening of the silicon nitride film 10.

Next, as shown in FIG. 15, the polycrystalline silicon film 3, which forms one of the two opening patterns, the silicon oxide film 9b, and the surface of the silicon nitride film 10 near the silicon oxide film 9b are covered. A resist film 11 is formed. Then, utilizing the fact that the etching rate of the silicon oxide film 9a is higher than the etching rate of the silicon nitride film 10, the silicon oxide film 9a is removed by wet etching using hydrofluoric acid as shown in FIG. In this state, the resist film 11 as shown in FIG. 17 is removed.

Next, as shown in FIG. 18, a cobalt film 6 of refractory metal is formed so as to cover the surfaces of the polycrystalline silicon film 3, the silicon nitride film 10 and the side wall silicon oxide film 9b.
Is deposited. Thereafter, by performing RTA, the polycrystalline silicon film 3 and the cobalt film 6 are reacted to form cobalt silicide films 7a and 7b. Next, the silicon nitride film 10 is formed using a mixed solution of phosphoric acid, acetic acid and ammonia.
The cobalt film 6 on the surface is removed to obtain a state shown in FIG. Thereafter, the RTA is again applied to the cobalt silicide film 7.
To reduce the resistance. Next, using the cobalt silicide films 7a and 7b as a mask, the silicon nitride film 10 and the polycrystalline silicon film 3 are removed by etching until the surface of the silicon oxide film 2 is exposed,
As shown in FIG. 20, the cobalt silicide films 7a and 7b
Then, gate electrodes 37a and 37b made of polycrystalline silicon films 3a and 3b are formed. Next, as shown in FIG. 21, an interlayer oxide film 8 is deposited on the silicon oxide film 2 so as to bury the gate electrodes 37a and 37b.

By using such a manufacturing method,
As in the first or second embodiment, the gate electrode 37
The aspect ratio of the buried portion between a and 37b is reduced. As a result, the film that becomes the interlayer oxide film 8 is not buried between the gate electrodes 37a and 37b, and an undesired phenomenon such as formation of a void is suppressed. As a result, the gate electrodes 37a and 37b can be formed close to each other, so that the semiconductor device can be miniaturized.

The silicon oxide film is formed of a resist film 11
Since the selectivity is higher than that of the silicon nitride film 10, only the silicon oxide film 9a in the region not covered with the resist film 11 is removed by etching. Therefore, the gate electrode 37b formed in a region other than the region covered by the resist film 11 is formed using the cobalt silicide film 7b which is processed to have a narrow width with the sidewall oxide film 9b as a mask. Thereby, gate electrode 37b is formed in a pattern having a width smaller than the minimum width in which the pattern of silicon nitride film 10 can be formed. Therefore, the gate electrode 37b formed in a region other than the region covered with the resist film 11 is further miniaturized. In the region covered with the resist film 11, the cobalt silicide film 7a is formed in a state where the side wall oxide film 9a is removed, so that the cobalt silicide film 7a has a width equal to the width when the opening pattern is formed in the silicon nitride film 10. Is formed and etching is performed. Thereby, gate electrode 37a is formed with the width of the opening pattern formed in silicon nitride film 10. Therefore, in the case where the semiconductor device has a plurality of element formation regions, gate electrodes 37a and 37b having different widths are provided in each region by one.
It can be formed in a process. As a result, gate electrodes 37a and 37b having different widths can be simultaneously formed in different regions, and the number of manufacturing steps of the semiconductor device is reduced.

In the present embodiment, an example in which the gate electrodes are close to each other has been described. However, even in the case where the gate electrodes are formed in separate regions on the semiconductor wafer, the semiconductor device according to the above-described embodiment may be used. By using the manufacturing method, gate electrodes having different widths can be formed in the same step.

In the first to third embodiments,
Although a silicon oxide film or a silicon nitride film is used as the salicide protective film, another material may be used as long as the material has a higher selectivity than the polycrystalline silicon film. Although a silicon oxide film is used as a sidewall film for forming a narrow gate electrode, other materials may be used as long as the material has a higher selectivity than the salicide protective film. In the above embodiment, a polycrystalline silicon film is used to form a high-melting metal silicide film. However, an amorphous silicon film or a single crystal silicon film may be used as long as a silicide film can be formed. Further, although cobalt is used as the high melting point metal, other metals such as tungsten or titanium may be used as long as they can form silicide by reacting with silicon.

In this embodiment, the gate electrode is formed by etching using a self-aligned refractory metal silicide film. However, any other conductive layer made of a polycide film may be used. The wiring or the like may be formed by etching using a refractory metal silicide film.

In the first to third embodiments, the case where a plurality of openings for forming the gate electrode exist has been described. However, a plurality of gates formed by one opening and connected so as to be branched. Even in the case where the electrodes are provided adjacent to each other, similar effects can be obtained by using the method of manufacturing a semiconductor device described in Embodiments 1 to 3.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0044]

According to the method of manufacturing a semiconductor device according to the first aspect of the present invention, even when the distance between the wiring layers or the gate electrodes is small, the steps after the formation of the interlayer insulating film are accurate. Therefore, it is possible to form a miniaturized semiconductor device as compared with the related art.

According to the method of manufacturing a semiconductor device according to the second aspect of the present invention, since the refractory metal silicide film is formed with the side wall film, the opening pattern formed in the second film is used. Since the refractory metal silicide film can be formed with a pattern having a width smaller than the minimum width of the pattern that can be formed, the semiconductor device can be miniaturized as compared with a case where the sidewall film is not used.

According to the third aspect of the present invention, the width of the wiring layer or the gate electrode can be made smaller by the film width of the side wall film, so that the wiring layer or the gate electrode can be brought closer to each other. Accordingly, the semiconductor device can be further miniaturized as compared with a case where the side wall film is not used.

According to the method of manufacturing a semiconductor device according to the present invention, when the semiconductor device has a plurality of element formation regions, wiring layers or gate electrodes having different widths are formed in each region by one step. Since it is possible to simultaneously form wiring layers or gate electrodes having different widths in different regions, the number of manufacturing steps of the semiconductor device is reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention, in which a silicon oxide film is dry-etched by a photoengraving technique using a resist film as a mask to expose a polycrystalline silicon film; It is a figure showing the state of.

FIG. 2 is a diagram showing a state of a cross section immediately after depositing a cobalt film on surfaces of a polycrystalline silicon film and a silicon oxide film by a sputtering method in the method of manufacturing a semiconductor device according to the first embodiment of the present invention; .

FIG. 3 shows a state of a cross section immediately after a polycrystalline silicon film and a cobalt film are reacted by heat treatment and an unreacted cobalt film is removed in the method of manufacturing a semiconductor device according to the first embodiment of the present invention. FIG.

FIG. 4 is a diagram illustrating a state of a cross section immediately after etching a silicon oxide film and a polycrystalline silicon film using a cobalt silicide film as a mask in the method of manufacturing a semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a diagram showing a state of a cross section immediately after an interlayer oxide film covering a gate electrode is formed in the method of manufacturing a semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a cross-sectional view immediately after forming a silicon oxide film so as to cover a silicon oxide film and a polycrystalline silicon film in which a predetermined opening is formed in the method for manufacturing a semiconductor device according to the second embodiment of the present invention; It is a figure showing a state.

FIG. 7 is a diagram showing a state of a cross section immediately after a sidewall silicon oxide film is formed on an opening sidewall of a silicon oxide film in the method for manufacturing a semiconductor device according to the second embodiment of the present invention;

FIG. 8 is a diagram showing a state of a cross section immediately after depositing a cobalt film by a sputtering method in the method of manufacturing a semiconductor device according to the second embodiment of the present invention;

FIG. 9 is a diagram showing a state of a cross section immediately after a polycrystalline silicon film and a cobalt film are reacted by heat treatment in the method of manufacturing a semiconductor device according to the second embodiment of the present invention;

FIG. 10 shows a state of a cross section immediately after etching a silicon oxide film, a side wall silicon oxide film, and a polycrystalline silicon film using a cobalt silicide film as a mask in the method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG.

FIG. 11 is a diagram showing a state of a cross section immediately after an interlayer oxide film covering a gate electrode is formed in the method for manufacturing a semiconductor device according to the second embodiment of the present invention;

FIG. 12 is a diagram showing a state of a cross section immediately after an opening having a predetermined pattern is formed in a silicon nitride film using a resist film as a mask in the method for manufacturing a semiconductor device according to the third embodiment of the present invention;

FIG. 13 is a diagram showing a state of a cross section immediately after a silicon oxide film is formed so as to cover surfaces of a silicon nitride film and a polycrystalline silicon film in the method for manufacturing a semiconductor device according to the third embodiment of the present invention; is there.

FIG. 14 is a diagram showing a state of a cross section immediately after a sidewall oxide film is formed on a sidewall of an opening of a silicon nitride film in the method for manufacturing a semiconductor device according to the third embodiment of the present invention;

FIG. 15 is a diagram showing a state of a cross section immediately after a resist film is formed so as to cover a predetermined opening formation region in the method for manufacturing a semiconductor device according to the third embodiment of the present invention;

FIG. 16 is a diagram showing a state of a cross section immediately after etching a sidewall silicon oxide film using hydrofluoric acid in the method for manufacturing a semiconductor device according to the third embodiment of the present invention;

FIG. 17 is a diagram showing a state of a cross section immediately after a resist film is removed in the method of manufacturing a semiconductor device according to the third embodiment of the present invention;

FIG. 18 is a diagram showing a state of a cross section immediately after depositing a cobalt film by a sputtering method in the method for manufacturing a semiconductor device according to the third embodiment of the present invention;

FIG. 19 is a diagram showing a state of a cross section immediately after a polycrystalline silicon film and a cobalt film are reacted by heat treatment in the method of manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 20 shows a state of a cross section immediately after etching a sidewall silicon oxide film, a silicon nitride film, and a polycrystalline silicon film using a cobalt silicide film as a mask in the method for manufacturing a semiconductor device according to the third embodiment of the present invention. FIG.

FIG. 21 is a diagram showing a state of a cross section immediately after forming an interlayer oxide film covering a gate electrode in the method of manufacturing a semiconductor device according to the third embodiment of the present invention;

FIG. 22 is a diagram showing a state of a cross section immediately after a resist film is patterned on a silicon nitride film in a conventional method for manufacturing a semiconductor device.

FIG. 23 is a view showing a state of a cross section immediately after a silicon nitride film and a silicon oxide film are etched using a resist film as a mask in a conventional method for manufacturing a semiconductor device.

FIG. 24 is a view showing a state of a cross section immediately after a tungsten silicide film and a polycrystalline silicon film are etched using a silicon nitride film and a silicon oxide film as a hard mask in a conventional method for manufacturing a semiconductor device.

FIG. 25 is a diagram showing a state of a cross section immediately after an interlayer oxide film covering a gate electrode is formed in a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

1 semiconductor substrate, 2 silicon oxide film, 3, 3a, 3b
Polycrystalline silicon film, 4 silicon oxide film, 5 resist film, 6 cobalt film, 7a, 7b cobalt silicide film, 8 interlayer oxide film, 9 silicon oxide film, 9a, 9b
Side wall silicon oxide film, 10 silicon nitride film, 11
Resist film, 37a, 37b Gate electrode.

Front page of the continued F-term (reference) 4M104 AA01 BB01 CC05 DD04 DD08 DD16 DD32 DD37 DD43 DD64 DD71 DD80 DD84 FF14 GG14 HH14 5F033 HH04 HH05 HH06 HH25 HH26 HH27 HH28 MM07 PP06 PP15 QQ08 QQ11 QQ27 QQ30 QQ31 QQ35 QQ37 QQ70 QQ73 QQ82 RR04 RR06 TT06 TT07 VV06 XX03 5F040 DB01 DC01 EC01 EC07 EC13 FC19 FC22 FC28 5F048 AA01 AC01 BB05 BB08 BB12 BG11

Claims (4)

[Claims] A step of forming a second film having a selectivity greater than that of the first film under a predetermined etching condition on the first film containing silicon; and a step of forming a second film until the upper surface of the first film is exposed. Forming a predetermined opening by etching the second film in the region of step (b), depositing a refractory metal film so as to cover at least the exposed surface of the first film, Reacting the high-melting-point metal film to form a high-melting-point metal silicide film; removing the unreacted high-melting-point metal film;
Removing the film and the first film by etching. A step of forming a second film having a selectivity greater than that of the first film under a predetermined etching condition on the first film containing silicon; and a step of forming a second film until the upper surface of the first film is exposed. Forming a predetermined opening by etching the second film in the region of; and forming a third film having a selectivity under a predetermined etching condition larger than the first film so as to cover the opening. Etching the third film until the surface of the first film is exposed to form a side wall film on the side wall of the second film; and a refractory metal film covering at least the exposed surface of the first film. Depositing; a step of reacting the first film with the high melting point metal film to form a high melting point metal silicide film; a step of removing the unreacted high melting point metal film; Using the silicide film as a mask, The second
A step of etching and removing the film, the side wall film and the first film. 3. The method according to claim 2, wherein, in the step of forming the predetermined opening, the predetermined opening is formed so as to have an adjacent opening region. 4. A material having a higher selectivity under predetermined etching conditions than that of the second film as the third film, and after the step of forming a side wall film on the side wall of the first film, a high melting point metal is used. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of removing the sidewall film in a part of the opening before the step of depositing a film.