JP2000311941A - Method and apparatus for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a multilayer interconnection semiconductor device which uses a low dielectric constant inter-layer film without the use of a photoresist mask. SOLUTION: On a semiconductor substrate 1, a first wiring 48 and a first alignment wiring 49 embedded in a first low dielectric constant film 47 are formed, and a substrate 30, where a conductor protruding pattern comprising an alignment electrode 45 and a wiring original mold 46 is formed, faces a substrate where a polymer film 50, on which a low dielectric constant film resin is formed, is formed, for rough alignment. Based on the electric characteristics provided, when a protruding pattern alignment conductor part contacts the alignment wiring, a position where the protruding pattern is press- fitted is decided, so that a conductor is embedded in the low dielectric constant film resin.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for manufacturing a semiconductor device, and more particularly, to a wiring method for connecting transistors formed on a semiconductor substrate and a method and an apparatus for manufacturing the same. It is.

[0002]

2. Description of the Related Art In recent years, with the advance of microfabrication technology, it has become possible to form ultra-small transistors having a minimum size of 0.1 μm on a silicon substrate surface layer. Further, formation of an ultra-large-scale integrated circuit (ULSI) including tens of millions of these extremely small transistors has been studied.

[0003] To realize such an ULSI, wiring for connecting tens of millions of transistors is required. By the way, the performance of a single transistor itself is improved by reducing the parasitic capacitance due to miniaturization, but the signal transmission performance of wiring (wiring delay) is degraded. The causes of the increase in the wiring delay include an increase in the wiring resistance caused by the reduction in the wiring width due to the miniaturization of the wiring, and an increase in the wiring capacitance due to a decrease in the distance between adjacent wirings.

In order to prevent the wiring performance from deteriorating, it is effective to introduce a low resistance metal film or a low dielectric constant interlayer insulating film. In addition,
It is also effective to increase the effective wiring density in a two-dimensional plane by forming a multilayer structure, instead of slightly loosening (widening) the wiring width and interval. For example, in a 0.1 μm generation ULSI in which a micro transistor having a minimum dimension of 0.1 μm is used,
It has been calculated that wiring of up to 10 layers is required.

In order to form a wiring, two photolithography steps and a dry etching step are required for forming a wiring pattern and forming a via hole for connecting to an underlying wiring layer per layer. According to this step, forming a 10-layer wiring requires 20 photolithography steps and 20 dry etching steps. Exactly ULSI
Most of the manufacturing process of device formation is spent on forming multilayer wiring.

Furthermore, when a low dielectric constant interlayer insulating film is used as the wiring interlayer insulating film, it takes time to perform patterning by dry etching. This is because it is difficult to dry-etch the low-k interlayer insulating film using the photoresist as a mask because the chemical properties of the photoresist and the low-k interlayer insulating film are similar.

Here, a first conventional example using a photolithography process is disclosed in the technical digest, p777, of the 1997 International Electron Device Meeting.
This technique is a process of forming a copper damascene wiring on a low dielectric constant interlayer film, and the process will be described below with reference to FIGS. Here, a conventional example in which a hydrogenated silica film (HSQ film) is used as the low dielectric constant interlayer insulating film.

First, as shown in FIG. 25A, a silicon oxide film 2 is formed on a semiconductor substrate 1, and a low dielectric constant interlayer film (hydrogenated silica film) is formed on the silicon oxide film 2 by spin coating. Grow 3.

Further, an etching mask layer for forming a wiring groove pattern is grown on the hydrogenated silica film 3. Here, a 100-nm-thick silicon oxide film is grown as the first mask film 4, and a 100-nm-thick titanium nitride film (TiN film) is grown on the first mask film 4 as the second mask film 5.

A photoresist 6 is formed on the second mask film 5.
Is applied and formed into a film.
The wiring groove pattern 7 is formed.

Next, using the photoresist 6 as a mask,
Dry etching is performed on the titanium nitride film as the second mask film 5 with a chlorine plasma gas to form a wiring groove pattern 7a in the second mask film 5 (FIG. 25B). At this time, the silicon oxide film serving as the first mask film 4 functions as an etching stop layer.

After patterning the wiring groove pattern 7a in the second mask film 5, the photoresist 6 is removed by oxygen plasma (FIG. 25C). At this time, since the low dielectric constant interlayer film 3 is covered with the first mask film 4, no decomposition reaction to the low dielectric constant interlayer film 3 due to oxygen plasma occurs.

Thereafter, using the second mask film 5 as a mask,
Dry etching using an oxygen-added fluorine-based plasma gas is performed to form a wiring groove pattern 7b in the first mask film 4 and the low dielectric constant interlayer film 3 (FIG. 25D).

Then, after forming a TiN film (not shown) as a barrier film, MOCVD (Metal Organic Chemical Vapor) is performed.
A Cu film 8 is grown by a por deposition method (FIG. 25).
(E)).

[0015] CMP using an alumina slurry (Chemic
al Mechanical Polishing) to perform the first mask film 4
The upper second mask film 5 (TiN film) and the Cu film 8 are removed (FIG. 25F). As a result, the Cu film in which the Cu film is embedded is formed in the wiring groove 7b formed in the structure in which the surface of the low dielectric constant interlayer film 3 is covered with the first mask film (silicon oxide film) 4.
The damascene wiring 9 is formed.

As described above, particularly when a conventional photolithography process is used to form a wiring on an interlayer film having a low dielectric constant, the number of steps is increased only by forming a single-layer wiring, which is a great obstacle in forming a multilayer wiring. Become.

On the other hand, in the following second to fourth conventional examples, methods not using a photolithography step have been proposed.

As a second conventional example, SYChou et al., "Impr
int of 25nm vias and trenches in polymers ”, Appl
ied Physics Lettter, Vol. 67 (21), 20, November, 19
There is a prior art disclosed in U.S. Pat. No. 95, p3114-3116. The process is described below with reference to FIGS. 26 (a) to (g).

First, a convex pattern 11 is formed on a mold 10 (FIG. 26A). On the semiconductor substrate 1 on which the silicon oxide film 2 is formed, a polymethyl methacrylate (PMM) which is a thermoplastic resin layer 12 is formed on the silicon oxide film 2.
A) Spin coat the film.

Thereafter, the temperature of the PMMA film is raised to 200 ° C., which is higher than the glass transition temperature of 105 ° C.
And the semiconductor substrate 1 are made to face each other (FIG. 26B).

Then, the mold 10 is brought into close contact with the PMMA film 12, and a pressure of about 10 MPa is applied (FIG. 26).
(C)).

Thereafter, when the mold 10 is removed by cooling, the convex pattern formed on the mold 10 is transferred to the PMMA film 12 as a concave pattern 13 (FIG. 26D).

Further, the PMMA film remaining at the bottom of the recess formed in the PMMA film is removed by oxygen plasma (FIG. 2).
6 (e)).

Next, a metal film 14 is formed on the PMMA film 12 (FIG. 26F), and the PMMA film 12 is removed together with the metal film 14 in a solvent to form a metal film pattern 15. (FIG. 26 (g)).

As a third conventional example, Japanese Patent Application Laid-Open No.
Japanese Patent Application Publication No. 96808 discloses an invention called “fine pattern forming method”. The present invention is a method of transferring a pattern formed on a silicon carbide plate 16, and the process is described below with reference to FIGS. 27 (a) to 27 (d).

Here, a metal film 14 of gold, silver, aluminum or the like is directly formed on the semiconductor substrate 1 on which the silicon oxide film 2 is formed on the upper surface, and the silicon carbide plate 16 on which the convex pattern 11 is formed. Are opposed to each other (FIG. 27A).

Then, the silicon carbide plate is set to 40 to 5
It is brought into close contact with a pressure of 0 MPa (FIG. 27B).

Thereafter, when the silicon carbide plate is removed, a concave pattern 17 is formed on the metal film 14 (FIG. 27).
(C)).

The metal film 14 remaining on the bottom of the concave pattern 17 formed on the metal film 14 is removed by ion milling to form a metal film pattern 15 on the silicon oxide film 2 (FIG. 27 ( d)).

As a fourth conventional example, Japanese Patent Application Laid-Open No.
Japanese Patent No. 1572 discloses an invention called "a method for manufacturing a printed wiring board and a method for manufacturing a multilayer printed wiring board".
The present invention provides a method for manufacturing a printed wiring board in a simple process without generating a large amount of waste liquid in which copper is dissolved. The process is described below with reference to FIGS.

First, in a vacuum vessel, a fluorine resin substrate 20 with a copper foil having a copper foil 19 adhered to the surface of a fluorine resin substrate 18 is provided.
Next, the mold 10 having the convex pattern 11 formed on the surface thereof is opposed to the mold 10 (FIG. 28A).

Next, the pressure inside the vacuum vessel is reduced to 10 torr, and the mold 10 is heated to 270 ° C.
0 is lowered to the fluororesin substrate 20 with copper foil and brought into contact therewith, and the mold 10 is heated and pressed on the fluororesin substrate 20 with copper foil for 20 seconds under the condition of a pressure of 3 kg / cm ² (FIG. 28).
(B)).

As a result, a copper foil concave pattern 21 is formed in which the copper foil 19 in contact with the convex pattern of the mold 10 is embedded in the fluorine resin substrate 18.

Thereafter, the mold 10 is raised, and the fluorine resin substrate 20 with the copper foil on which the copper foil concave pattern 21 is formed is taken out of the vacuum vessel (FIG. 28 (c)).

Then, while flowing water on the copper foil forming surface side,
The copper foil part 22 which becomes the convex part of the fluororesin substrate 20 with copper foil,
Grinding and removing with a drum around which sandpaper is wound, the fluorine resin substrate 18 in which the copper foil circuit pattern 23 is embedded is formed (FIG. 28D).

As a fifth conventional example, Japanese Patent Laid-Open Publication No.
Japanese Patent No. 60890 discloses an invention called “a method for manufacturing a printed wiring board”. The present invention aims at effective use of copper and reduction of etching steps in the manufacture of a printed wiring board, and is an example of wiring formation by an electroless plating method. The process is described below with reference to FIGS.

Here, first, an ink containing a chemical plating catalyst core 24 and an adhesive (not shown) is applied to the surface of the convex pattern 11 of the mold 10 (FIG. 29A).

Next, the mold 10 is pressed against the resin substrate 25, and a portion of the resin substrate 25 that comes into contact with the convex pattern of the mold 10.
Then, a concave pattern 13 is formed (FIG. 29B).

Thereafter, when the mold 10 is raised, the catalyst nuclei 24 for chemical plating are selectively formed on the bottom of the concave pattern 13 of the resin substrate 25 (FIG. 29C).

The resin substrate is immersed in a copper chemical plating solution 26, and a copper film is selectively grown inside the concave pattern 13 of the resin substrate 25 by the chemical plating catalyst core 24 (FIG. 29).
(D)).

At this time, an unnecessary copper film 27 is deposited on a part of the surface of the resin substrate 25 other than inside the concave pattern 13.

Thereafter, unnecessary copper film 27 on the resin substrate is removed by blade 28 (FIG. 29 (e)), whereby copper circuit pattern 29 in which the copper film is embedded only in concave pattern portion 13 of resin substrate 25. (FIG. 29 (f)).

As another related art, Japanese Patent Publication No. Hei 8-31522 discloses an invention called "a method for forming a multilayer conductor / insulator coplanar thin film using a photosensitive polyimide polymer composition". . The present invention provides a method for forming a multilayer metal insulator coplanar thin film on a substrate.

In addition, Japanese Patent Application Laid-Open No. 8-186376 discloses an invention entitled "High-density thin-film multilayer wiring board, its mounting structure and its manufacturing method". An object of the present invention is to provide a high-density thin-film multilayer wiring board having a simplified configuration with a high wiring density and a high reliability without lowering the transmission speed.

[0045]

However, the above-mentioned 1997 International Electronic Device Conference (1997 Interna
SIG Electron Device Meeting) Technical Digest, p777, SYChou et al., “Impr
int of 25nm vias and trenches in polymers ”, Appli
ed Physics Lettter, Vol. 67 (21), 20, November, 199
5, p3114-3116.
The conventional wiring forming methods disclosed in Japanese Unexamined Patent Application Publication Nos. 9-96808, 5-41572 and 57-60890 have the following problems.

First, the first conventional example shown in p777, a technical digest of the 1997 International Electron Device Meeting, is a conventional example in which a copper damascene wiring is formed on a low dielectric constant interlayer film. However, since the low dielectric constant interlayer film cannot be dry-etched directly with the photoresist film, a laminated mask film composed of a silicon oxide film (first mask film) and a titanium nitride film (second mask film) is used. Therefore, the number of manufacturing steps is greatly increased due to the growth of the multilayer structure mask film and the patterning by dry etching.

In the 0.1 μm generation ULSI, multilayer wiring of about 10 layers is required, and it is essential to reduce at least the number of manufacturing steps of each wiring layer. This first conventional example meets this technical requirement. Contrary.

SYChou et al., “Imprint of 25 nm vias and trenche, which does not directly use a photolithography process.
s in polymers ”, Applied Physics Lettter, Vol. 67
(21), 20, Novemberr, 1995, p3114-3116. In a second conventional example, a mold 10 having a convex pattern 11 formed on a thermoplastic resin film 12 (PMMA film) as a mask material is pressed. By applying, the PMMA film 12 is patterned. Thereafter, a metal film 14 is formed on the PMMA film 12 (FIG. 26 (f)), and the PMMA film 12 is removed together with the metal film 14 thereon in a solvent to form a metal film pattern 15. .

In this case, the patterning process using a photoresist by exposure and development is merely replaced by a PMMA film patterning process by press-fitting a mold, which does not lead to a substantial reduction in the number of processes.

In order to apply the present invention to a multi-layer wiring forming process, it is necessary to perform a step of aligning the base wiring layer and forming a connection hole (via hole) in the base wiring layer, but these steps are not described at all. However, it cannot be applied to formation of a multilayer wiring.

In a third conventional example disclosed in Japanese Patent Application Laid-Open No. 10-96808, a metal film 1 on a silicon oxide film is used.
By pressing the silicon carbide plate 16 directly on the metal film 4, a pattern is formed on the metal film 14.

In this case, a pressure as large as 40 to 50 MPa is required to directly compress and deform the metal film.
Assuming that wiring is formed on a silicon device, the pressure causes cracks and crystal transition defects in the underlying silicon single crystal.

Also, in the present method, the step of aligning with the underlying wiring layer and the formation of connection holes (via holes) in the underlying wiring layer are not clear, and cannot be applied to the multilayer wiring forming process. Even if the step of aligning with the underlying wiring layer is performed by an optical method, the position of the underlying pattern must be detected via the metal film 14, and it is difficult to align an extremely fine pattern.

In a fourth conventional example disclosed in Japanese Patent Application Laid-Open No. Hei 5-41572, a fluorine resin substrate 20 with a copper foil is used in which a copper foil 19 is laminated on a fluorine resin substrate 18 which is easily deformed by heat. Then, the copper foil is pushed into the concave portion of the fluororesin substrate by utilizing the fact that the fluororesin is deformed by pressing the mold 10 on which the convex pattern 11 is formed.

In this case, it is apparent that Japanese Patent Application Laid-Open No.
No. 8 discloses a third conventional example.
Less pressure is required for mold crimping.

By the way, the fourth prior art, which is disclosed in
According to the description in paragraph [0166] of JP-A-41572, a single-layer copper wiring is formed on a fluororesin substrate by die pressing, the fluororesin substrate is bonded after the copper wiring is formed, and each copper wiring layer is connected by spot welding. ing.

As described above, the fourth conventional example is a technique for forming a single-layer wiring on a fluorine resin substrate, and is not a technique for directly forming a multi-layer wiring by die compression. Therefore, there is no description about the method of alignment with the underlying wiring layer or the formation of a connection hole (via hole) in the underlying wiring layer.
It is difficult to apply to a process of forming a multilayer wiring on a device.

Further, in order to remove unnecessary copper foil on the fluororesin substrate, it is ground and removed by a drum around which sandpaper is wound. At this time, scratches are made on the surface of the fluororesin or the surface of the copper wiring embedded in the concave portion. It cannot be applied to the formation of multi-layer wiring for ULSI devices that need to form wiring on the order of submicrons.

In the fifth conventional example disclosed in Japanese Patent Application Laid-Open No. 57-60890, after a catalyst core 24 for chemical plating in which an adhesive is mixed with a convex pattern 11 of a mold 10 is applied,
It is characterized in that a concave pattern is formed by pressing against a thermoplastic resin, and the catalyst nuclei 24 for chemical plating are transferred to the bottom of the concave pattern.

Although the fifth conventional example does not disclose a method of forming a connection hole (via hole) in the underlying wiring layer, the following problem can be easily guessed. That is,
In the multilayer wiring of the 0.1 μm generation ULSI device, the via hole with the underlying wiring layer is 0.25 μm or less on each side, and it is indispensable to minimize the contact resistance in this part.

However, when the wiring layer is formed by the method according to the conventional example, it is inevitable that a part of the adhesive compounded in the catalyst core 24 for chemical plating adheres to the surface of the underlying wiring layer. As a result, the contact resistance increases.
There is also no specific description on the method of alignment with the underlying wiring layer, and it is difficult to apply a 0.1 μm generation ULSI device to multilayer wiring.

An object of the present invention is to provide a method of manufacturing a semiconductor device and a multilayer wiring structure for efficiently forming a multilayer wiring using a low dielectric constant interlayer film without using a photoresist mask.

Another object of the present invention is to provide a manufacturing apparatus and a manufacturing method used in the above-described semiconductor manufacturing method.

[0064]

According to the present invention, there is provided an insulating layer forming step of forming an insulating layer on a semiconductor substrate, and a wiring including an alignment conductor in the insulating layer. A wiring layer embedding step of embedding the layer, a concave pattern forming step of forming a low dielectric layer on the insulating layer and pressing a convex pattern to form a concave pattern in the low dielectric layer, wherein the convex pattern is formed. Has a convex pattern alignment conductor, and determines the position where the convex pattern is to be crimped based on the electrical characteristics obtained when the convex pattern alignment conductor and the alignment conductor are brought into contact with each other. A low dielectric constant layer is formed of a low dielectric constant film having a lower dielectric constant than a silicon oxide film or a silicon nitride film, and a conductor embedding step of embedding a conductor in a concave pattern is provided. That.

In the above-described method for manufacturing a semiconductor device, the element may be provided on the semiconductor substrate, and the alignment conductor may be electrically connected to the element.

In the above-described method for manufacturing a semiconductor device, the insulating layer may be formed of a low dielectric constant film.

In the method of manufacturing a semiconductor device described above, the step of forming a concave pattern includes the step of applying a prepolymer on the insulating layer at a temperature lower than the polymerization temperature, wherein the prepolymer is a polymerized temperature. When heated as described above, a polymerization reaction occurs to become a low dielectric constant polymer,
A pattern forming step of crimping the convex pattern to form a concave pattern in the prepolymer, and the position at which the convex pattern is crimped was such that the convex pattern alignment conductor portion was brought into contact with the alignment conductor portion. The low dielectric constant film is formed based on the electrical characteristics obtained at times, and the prepolymer having the concave pattern formed by the pattern forming step is heated to a temperature higher than the polymerization temperature to form a low dielectric constant film made of a low dielectric constant polymer. Forming a low dielectric constant film, wherein the low dielectric constant film has a lower dielectric constant than a silicon oxide film or a silicon nitride film.

In the above-described method for manufacturing a semiconductor device, the step of forming a concave pattern includes the step of arranging a convex pattern on an insulating layer, and the step of arranging the convex pattern includes the step of arranging a convex pattern alignment conductor. The prepolymer having a temperature lower than the polymerization temperature is determined based on the electrical characteristics obtained when the conductive layer is brought into contact with the alignment conductor, and is provided between the convex pattern and the insulating layer arranged in the arrangement step. When the prepolymer is heated to a temperature higher than the polymerization temperature, a polymerization reaction occurs to become a low dielectric constant polymer, and the prepolymer injected by the injection step is heated to a polymerization temperature. Heating to form a low-k film made of a low-k polymer, wherein the low-k film is a silicon oxide film or a silicon oxide film. Than emissions nitride film can be characterized in that the dielectric constant is low.

According to the present invention, a low dielectric constant layer is formed on a semiconductor substrate provided with elements, and a convex pattern is pressed to form a concave pattern on the low dielectric layer. A concave pattern forming step to be formed, wherein the convex pattern has a convex pattern alignment conductor, and based on the electrical characteristics obtained when the convex pattern alignment conductor and the element are brought into contact with each other. The position where the convex pattern is pressed is determined, and the low dielectric constant layer is made of a low dielectric constant film having a lower dielectric constant than a silicon oxide film or a silicon nitride film, and the conductive film is embedded in the concave pattern. And a method for manufacturing a semiconductor device.

In the above method for manufacturing a semiconductor device, the step of forming a concave pattern includes the step of applying a prepolymer on a semiconductor substrate, wherein the prepolymer comprises:
When heated to a temperature higher than the polymerization temperature, a polymerization reaction occurs to become a low dielectric constant polymer, and a convex pattern is pressed to form a concave pattern in the prepolymer. The crimping position is determined based on the electrical characteristics obtained by bringing the convex pattern alignment conductor into contact with the alignment conductor, and the prepolymer having the concave pattern formed by the pattern forming step. A low-k film forming step of forming a low-k film made of a low-k polymer by heating to a temperature higher than or equal to the polymerization temperature, wherein the low-k film is smaller than a silicon oxide film or a silicon nitride film. It can be characterized by a low dielectric constant.

In the method of manufacturing a semiconductor device described above, the step of forming a concave pattern includes the step of arranging a convex pattern on a semiconductor substrate. An injection step of injecting a prepolymer into a gap between the convex pattern and the semiconductor substrate, which is determined based on electrical characteristics obtained at the time of contacting with the alignment conductor portion and is arranged by the arrangement step, When the prepolymer is heated to a temperature higher than the polymerization temperature, a polymerization reaction occurs to become a low dielectric constant polymer, and the prepolymer injected in the injection step is heated to a temperature higher than the polymerization temperature to have a low dielectric constant. Forming a low-k film made of a polymer, wherein the low-k film is more induced than a silicon oxide film or a silicon nitride film. It is possible, wherein the rate is low.

In the above method for manufacturing a semiconductor device, the prepolymer is not lower than room temperature and lower than the polymerization temperature, and
When heated to a plastic temperature having a predetermined temperature range, the resin exhibits thermoplasticity, and the pattern forming step may further include a heating step of heating the prepolymer to a plastic temperature.

In the above-described method for manufacturing a semiconductor device, the prepolymer is not lower than room temperature and lower than the polymerization temperature, and
When heated to a plastic temperature having a predetermined temperature range, the resin exhibits thermoplasticity, and the pouring step may further include a heating step of heating the prepolymer to a plastic temperature.

In the above method for manufacturing a semiconductor device, the prepolymer can be made of any of divinylsiloxane benzocyclobutene monomer, polyimide monomer and allyl ether monomer.

In the above method for manufacturing a semiconductor device, the prepolymer may be made of divinylsiloxane benzocyclobutene monomer, and the polymerization temperature may be 150 degrees Celsius.

In the method of manufacturing a semiconductor device described above, the convex pattern can include a two-layer pattern including a first convex pattern and a second convex pattern provided on the first convex pattern. is there.

In the above-described method for manufacturing a semiconductor device, the convex pattern alignment conductor can be formed of a two-layer pattern.

In the above-described method for manufacturing a semiconductor device, the electrical characteristic may be characterized by a current value obtained when a voltage is applied to the convex pattern alignment conductor.

According to another aspect of the present invention, there is provided a semiconductor device for forming a concave pattern in a low dielectric constant layer or an insulating layer provided on a lower layer having a matching conductor portion. A plurality of convex portions provided on the substrate and electrically disconnected from each other, and a convex pattern alignment conductor comprising two or more convex portions among the plurality of convex portions. And a pair of lead-out wirings that are electrically connected individually to a pair of protrusions of each of the convex pattern alignment conductors, and a position where the concave pattern is formed. The present invention also provides an apparatus for manufacturing a semiconductor device in which a matching portion is electrically connected via a matching conductor portion and is determined based on electrical characteristics measured via a pair of lead wirings.

In the above-described apparatus for manufacturing a semiconductor device, the plurality of projections include a first projection pattern provided on the substrate and a second projection pattern provided on the first projection pattern.
It is possible to include a layer pattern.

In the above-described apparatus for manufacturing a semiconductor device, the two or more projections forming the alignment portion may be formed of a two-layer pattern.

In the above-described apparatus for manufacturing a semiconductor device, it is possible to further provide a hole penetrating the substrate and extending from the bottom of the substrate to the convex portion.

In the above-described apparatus for manufacturing a semiconductor device, a heating unit for heating the substrate may be further provided.

In the above-described apparatus for manufacturing a semiconductor device, the electric characteristic may be a current value obtained when a voltage is applied to a pair of lead wirings.

Further, according to the present invention, there is provided a semiconductor device for forming a concave pattern in a low dielectric constant layer or an insulating layer provided on a lower layer having a matching conductor portion. In the manufacturing apparatus, an opening forming step of forming an opening in the insulating film formed on the substrate,
A conductor film embedding step of embedding the conductor film in the opening, and a removing step of selectively removing the insulating film, wherein the conductor film becomes a plurality of protrusions that are not electrically connected,
For each of the alignment conductive projections formed of at least one set of the plurality of projections, a lead-out wiring is formed that penetrates the substrate from the lower surface of the substrate and reaches each of the alignment projections. And a method for manufacturing a semiconductor device manufacturing apparatus, comprising:

In the above method of manufacturing a semiconductor device manufacturing apparatus, the substrate is formed of a metal conductor substrate or a semiconductor substrate, and the step of embedding the conductor film includes embedding a conductor film so as not to be electrically connected to the substrate. In the drawing wiring forming step, the drawing wiring may be formed so as not to be electrically connected to the substrate.

According to the present invention, there is provided a semiconductor device for forming a concave pattern on a low dielectric constant layer or an insulating layer provided on a lower layer having a conductor portion for alignment. In a manufacturing apparatus, an insulating film forming step of forming an insulating film for wiring on a substrate made of an insulating material;
An opening forming step of forming an opening in the wiring insulating film, a conductor film embedding step of embedding a conductive film in the opening, and a removing step of selectively removing the wiring insulating film; Is composed of a plurality of protrusions that are not electrically connected to each other, and among the plurality of protrusions, for each of the alignment conductive protrusions formed of at least one set of protrusions, penetrates the substrate from the lower surface of the substrate, A method for manufacturing a semiconductor device manufacturing apparatus, comprising: a lead wiring forming step of forming lead wiring reaching each of the conductive protrusions for alignment.

In the above method of manufacturing a semiconductor device, an upper insulating film forming step of forming an upper insulating film covering the insulating film and the conductive film, and forming an upper opening reaching the conductive film in the upper insulating film. Forming an upper opening, and embedding an upper conductor film in the upper opening. The removing step may include a step of selectively removing the insulating film and the upper insulating film.

In the above-described method for manufacturing a semiconductor device manufacturing apparatus, the upper opening forming step includes the step of forming the upper opening reaching the conductor film on the upper insulating film on the conductor film to be the conductive protrusion for alignment. It can further include forming.

In the method of manufacturing a semiconductor device, it is possible to further include a step of forming a hole extending from the back surface of the substrate to the convex pattern through the substrate.

In the above-described method of manufacturing a semiconductor device manufacturing apparatus, it is possible to further include a heating unit forming step of forming a heating unit for heating the substrate.

[0092]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method and an apparatus for manufacturing a semiconductor device according to the present invention will be described for forming a multilayer wiring in which a metal (conductor film) is embedded in a resin film on a silicon substrate on which a base wiring is formed. An embodiment will be described with respect to an applied example.

First, a mold substrate used for forming a multilayer wiring, which is an apparatus for manufacturing a semiconductor device according to the present invention, will be described below with reference to FIG.

FIG. 1 shows a mold substrate according to the present invention.

Referring to FIG. 1, the mold substrate according to the present invention has the following configuration.

A surface insulating film 31 is formed on a substrate 30. Here, the substrate 30 may be a semiconductor substrate made of silicon, an insulator substrate made of an insulator such as a silicon oxide film, or a conductor substrate made of metal.

On the surface insulating film 31, a base electrode 32 and an electrode insulating film 33 are formed. Part of the base electrode 32 reaches the surface of the upper surface of the electrode insulating film 33 that has been subjected to the planarization process.

On the base electrode 32 and the electrode insulating film 33, conductor convex patterns 42 and 42 'are formed. Here, the conductor convex patterns 42 and 42 ′ are the same as the first convex patterns 40 and 40 ′ provided on the base electrode 32 and the electrode insulating film 33.
The second convex pattern provided on the first convex pattern 40, 40 '
Are formed from the convex patterns 41 and 41 ′. In addition, a part 40 ′ of the first convex pattern 40, 40 ′ is
2 and are electrically connected to the second convex patterns 41 and 4.
Part 41 ′ of 1 ′ is electrically connected to part 40 ′ of the first convex pattern.

Further, an electrode lead-out hole 43 is formed from the lower surface of the substrate 30 to penetrate the substrate 30 and the surface insulating film 31 and reach the base electrode 32.

A lower surface insulating film 30a is formed to cover the side surface of the electrode lead hole 43 and the lower surface of the substrate 30.

Further, lead electrodes 44a, 44 electrically connected to base electrode 32 through electrode lead holes 43.
b is formed. The extraction electrodes 44a, 44b
Has a configuration not electrically connected to the substrate 30. Further, the respective base electrodes 32 connected to the respective lead electrodes 44a and 44b are not electrically connected in the mold substrate.

Here, the configuration having the surface insulating film 31 and the lower surface insulating film 30a described above is indispensable when the substrate 30 is a semiconductor substrate made of silicon or a conductor substrate made of metal. However, if the substrate 30 is not electrically connected to the base electrode 32 and the lead electrodes 44a and 44b, the surface insulating film 31 and the lower insulating film 3
It is not limited to the configuration having 0a.

When the substrate 30 is made of an insulating substrate made of an insulator such as a silicon oxide film, the surface insulating film 31 and the lower surface insulating film 30a described above are provided because the substrate 30 itself has insulating properties. It becomes unnecessary.

FIG. 2 shows a modification of the mold substrate according to the present invention.

As shown in FIG. 2, the structure in which the heating plate 75 is provided on the lower surface of the substrate 30 or / and the conductor convex patterns 42, 4
A configuration in which a through hole 77 reaching 2 ′ is provided is also possible. Here, although a configuration having both the heating plate 75 and the through hole 77 is shown in the drawing, the heating plate 75 or the through hole 77 is used.
A configuration having only one of them is also possible.

As shown in the following embodiment, this through hole 77 is formed so that a prepolymer can be injected from the lower surface of the substrate 30 into the upper surface on which the conductor convex patterns 42 and 42 'are provided. It is configured to penetrate the whole.

Further, in order to prevent the injected prepolymer from flowing out of the predetermined wiring formation region, the outflow prevention wall 421 formed by a part of the conductor convex patterns 42 and 42 'is used.
Is provided. This outflow prevention wall 421
Is a first convex pattern 40, 40 ′, and a second convex pattern 41 provided on the first convex pattern 40, 40 ′.
41 '. In particular, in the step of forming a concave pattern in the low-k film shown below, the pre-polymer is adhered to the lower layer of the low-k film to be formed so that the injected prepolymer does not flow out to the other through the adhered portion. It is configured. Further, it is desirable that the outflow prevention wall 421 be formed such that in the above-mentioned prepolymer injection, the adhesion at the contact portion is increased so that the prepolymer can be injected by a vacuum injection method. Specifically, the outflow prevention wall 421 has a structure having elasticity such as rubber, and when the mold substrate is brought into close contact with the lower layer of the low dielectric constant film,
It is desirable that the tip of the outflow prevention wall 421 be deformed so as to increase the adhesion at the contact portion. In addition, it is desirable that the outflow prevention wall 421 has elasticity and is longer than the length of the surrounding conductor convex patterns 42 and 42 '.

In addition, the number of the through holes 77 is not limited to one, and at least one through hole may be formed.

Next, a method of manufacturing a mold substrate according to the present invention will be described below with reference to the drawings.

FIGS. 3 (a) to 3 (c) and FIGS. 4 (a) to 4 (c) are views showing steps for manufacturing a mold substrate according to the present invention.

FIG. 3 shows a method of manufacturing a mold substrate according to the present invention.
This is shown below with reference to FIGS. 3A to 3C and FIGS. 4A to 4C.

First, as shown in FIG. 3A, a base electrode 32 and an electrode insulating film 33 are formed on a substrate 30 on which a surface insulating film 31 has been formed. Here, the substrate 30 may be a semiconductor substrate made of silicon, an insulator substrate made of an insulator such as a silicon oxide film, or a conductor substrate made of metal. Further, a part of the base electrode 32 reaches the surface layer on the upper surface of the electrode insulating film 33 which has been subjected to the planarization process.

Next, as shown in FIG. 3B, a first insulating film 34 is formed by growing the first insulating film 34 on the base electrode 32 and the electrode insulating film 33, and the first insulating film 34 is formed on the first insulating film 34. One opening 35 is formed.

Next, a conductor film is formed so as to cover the whole. By selectively removing the formed conductive film on the first insulating film 34 by a chemical mechanical polishing method or the like, the first opening 35 as shown in FIG. A structure in which the first conductor films 36 and 36 'are embedded is obtained. First
A portion 36 ′ of the conductive film is electrically connected to the base electrode 32.

Further, as shown in FIG. 4A, a second insulating film 34 and second conductive films 36 and 36 '
Is formed, and a second opening 38 reaching the first conductor film 36 is formed.

Next, a conductor film is formed so as to cover the whole. At this time, the conductor film is embedded in the second opening 38. Next, the second insulating film 3 is formed by a chemical mechanical polishing method or the like.
7 is selectively removed. As a result, a structure in which the second conductor films 39 and 39 'are embedded in the second opening 38 as shown in FIG. 4B is obtained. A portion 39 'of the second conductor film is electrically connected to the base electrode 32 via a portion 36' of the first conductor film.

Next, as shown in FIG. 4C, when the first insulating film 34 and the second insulating film 37 are selectively removed, a first conductive film is formed on the surface insulating film 31 of the substrate 30. Body membrane 36, 3
6 ′, and second convex patterns 41, 4 composed of the second conductive films 39, 39 ′.
1 ', the conductor convex patterns 42, 42'
Is obtained.

Further, an electrode lead-out hole 43 is formed from the lower surface of the substrate 30 through the substrate 30 and the surface insulating film 31 to reach the base electrode 32. Next, a lower surface insulating film 30a is formed on the entire surface from the lower surface of the substrate 30. Next, the electrode extraction hole 4
3 The lower surface insulating film 30a at the bottom is removed by anisotropic etching or the like, and the base electrode 32 is
To expose. Next, lead electrodes 44a and 44b that are electrically connected to the base electrode 32 are formed on the back surface of the substrate 30, and the mold substrate shown in FIG. 1 is obtained. Here, a portion 42 ′ of the conductor convex pattern has a structure in which it is electrically connected to the lead electrodes 44 a and 44 b via the base electrode 32, but the lead electrode 44 a and the lead electrode 44 a are formed on the substrate 30. It is characterized in that there is no route connecting between 44b. In this state, the extraction electrode 44a and the extraction electrode 44
No current flows even if a voltage is applied to b.

Here, when the substrate 30 is made of an insulating substrate made of an insulator such as a silicon oxide film, the surface insulating film 31 shown above is used because the substrate 30 itself has insulating properties.
It is not necessary to provide the lower surface insulating film 30a. Since the substrate 30 is an insulator, no current flows even when a voltage is applied to the extraction electrodes 44a and 44b without the surface insulating film 31 and the lower surface insulating film 30a in the above state. That's why.

In FIG. 1, the electrode lead-out holes 43 are formed in the substrate 30. However, as shown in FIG. 5, lead-out electrodes 44a and 44b may be formed on the side wall of the substrate 30. At this time, the substrate 30 and the lead electrodes 44a and 44b are not electrically connected. As an example, the substrate 30 and the extraction electrodes 44a and 44b are insulated by an insulating film (not shown).

Here, the extraction electrodes 44a and 44b are
The present embodiment is not limited as long as the structure can apply a voltage to the conductor convex pattern 42 'formed on the mold substrate.

In this way, the substrate 30 used for forming the multilayer wiring is manufactured.
A series of patterns including the conductor convex pattern 42 ′ connected to 4 b is the alignment electrode 45, and the other conductor convex patterns 42 are wiring base patterns 46.

Also, after the end of the manufacturing process shown in FIG. 4C, before forming the electrode lead holes 43 in the substrate 30, a step of forming or attaching a heating plate 75 for heating the entire substrate is included. It is also possible. Further, FIG.
After the end of the manufacturing process shown in FIG.
Through the entire substrate, and the conductive convex pattern 4 on the upper part of the substrate.
It is also possible to include a step of forming a through hole 77 reaching 2, 42 '. FIG. 2 shows an example of a mold substrate formed by adding the above steps. Here, although not shown,
A mold substrate obtained through a manufacturing process of forming only one of the heating plate 75 and the through hole 77 is also possible.

As shown in the following embodiment, this through hole 77 is formed so that a prepolymer can be injected from the lower surface of the substrate 30 into the upper surface on which the conductor convex patterns 42 and 42 'are provided. It is configured to penetrate the entire substrate.

Further, when the substrate 30 includes the through-hole 77, in the step of forming the conductor convex patterns 42 and 42 ', the substrate 30 is formed of a part of the conductor convex patterns 42 and 42' and the other conductor convex patterns 42 and 42 'are formed. , 42 'is provided with an outflow prevention wall 421 surrounding the outer peripheral portion. The outflow prevention wall 421 is composed of the first convex patterns 40 and 40 ′ and the first convex patterns 40 and 4 ′.
It is composed of second convex patterns 41, 41 'provided on 0'.

The outflow prevention wall 421 is formed when the prepolymer is injected from the through hole 77 into the region where the concave pattern is formed in the low dielectric constant film forming step described below.
It has a function of preventing the prepolymer from flowing out of the region where the concave pattern is formed. In particular,
In the step of forming a concave pattern on the low dielectric constant film described below, first, in the step of pressing the substrate 30 including the through hole 77, the outflow prevention wall 421 surrounds a region where the concave pattern is formed. At this time, the outflow prevention wall 421 and the lower layer of the low dielectric constant film to be formed are in close contact with each other, and the lower layer of the low dielectric constant film and the through hole 77 are formed in the next step to form a concave pattern. This prevents the prepolymer injected between the substrate and the containing substrate 30 from flowing out of the region where the concave pattern is to be formed due to the close contact portion between the outflow prevention wall 421 and the lower layer of the low dielectric constant film.

In addition, the number of the through holes 77 is not limited to one, and at least one through hole may be formed.

Next, a first embodiment of the method of manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings. The first embodiment of the method for manufacturing a semiconductor device according to the present invention is a multilayer wiring manufacturing process using the above-described mold substrate.

FIGS. 6A, 6B, 7A,
FIGS. 8B, 8A, 8B, 9A, 9B, and 10 are cross-sectional views showing the manufacturing steps of the first embodiment in the method for manufacturing a semiconductor device of the present invention. It is.

FIGS. 6A, 6B, 7A,
A first embodiment of a method of manufacturing a semiconductor device according to the present invention will be described below with reference to (b), FIGS. 8 (a), (b), FIGS. 9 (a), (b), and FIG.

First, as shown in FIG. 6A, a first substrate is formed on a semiconductor substrate 1 on which a transistor (not shown) is formed.
A first wiring 48 and a first alignment wiring 49 embedded in the low dielectric constant film 47 are formed.

On the first low dielectric constant film 47, a prepolymer film 50 for forming a low dielectric constant resin is grown (FIG. 6B). The prepolymer forming the prepolymer film 50 is fluid (or thermoplastic) at a temperature _TLV or higher.
It is shown, but polymerization reaction occurs at a higher temperature _{T P (T P> T LV} ), with features having the property of changing the low dielectric constant film resin. The prepolymer film 50 is usually spin-coated with a solvent in a state of being dissolved in a volatile solvent, and the solvent is volatilized at a temperature _TLV or lower, thereby forming a film on the first low dielectric constant film 47.

Next, as shown in FIG. 7A, a conductor convex pattern 4 composed of an alignment electrode 45 and a wiring base 46 is placed on the semiconductor substrate 1 on which the prepolymer film 50 is formed.
The substrate 30 on which 2, 42 'is formed is placed in a vacuum vessel (not shown) in a state where the substrates 30 are opposed to each other. At this time, coarse alignment between the substrate 30 and the semiconductor substrate 1 is performed using an optical means or the like.

Next, a temperature T _{S equal to} or higher than the temperature T _{LV at} which the fluidity of the prepolymer film 50 increases (provided that T _LV <T _S <
_TP ), the semiconductor substrate 1 is heated, and the substrate 30 is pressed,
The first alignment wiring 49 and the first wiring 48 formed on the semiconductor substrate 1 are brought into contact with the alignment electrode 45 and the wiring base mold 46 formed on the substrate 30, respectively.

In this state, a voltage is applied between the extraction electrodes 44a and 44b, and the extraction electrode 44b → the underlying electrode 32 →
The current A flowing from the alignment electrode 45 → the first alignment wiring 49 → the alignment electrode 45 → the base electrode 32 → the extraction electrode 44a is measured.

At this time, due to misalignment (Δx), the contact area between the alignment electrode 45 and the first alignment wiring is reduced, and the resistance between the extraction electrodes 44a and 44b changes. That is, since the current A is a function of the amount of misalignment (Δx), the position where the current value A shows the minimum value has a positional relationship without misalignment (FIG. 7B).

Here, the contact resistance between the first alignment wiring 49 formed on the semiconductor substrate 1 side and the alignment electrode 45 formed on the substrate 30 was measured. The characteristics of the element may be measured via the alignment electrode 45 formed on the substrate 30, and the positional relationship without misalignment may be obtained based on the measurement result.

It is important that the electrical characteristics of wirings and semiconductor elements formed on the semiconductor substrate 1 be measured via alignment electrodes 45 formed on the substrate 30 during alignment.
That is, it is used as eye alignment position information. If the measurement result of the semiconductor element is used, it can be used for determining whether or not there is a characteristic abnormality of the semiconductor element during the multilayer wiring forming process. In this case, at least a part of the first alignment wiring 49 must be connected to a semiconductor element (not shown) formed on the semiconductor substrate 1.

[0139] Then, by heating the mold substrate, the temperature of the prepolymer film 50 and the temperature T _P. At this temperature _TP , a polymerization reaction occurs in the propolymer film 50, and the fluidity of the prepolymer film 50 decreases. In this state, the substrate 3
8 is separated from the semiconductor substrate 1, the wiring groove pattern 5 corresponding to the first convex pattern formed on the mold substrate is formed on the prepolymer film 50 ′ having reduced fluidity as shown in FIG.
2 and a via hole pattern 51 corresponding to the second convex pattern
Are transferred and formed.

After the substrate 30 and the semiconductor substrate 1 are taken out of the vacuum vessel, the silicon substrate is heated to a temperature of Tp or higher to cause a polymerization reaction, and the prepolymer film 50 ′ having reduced fluidity is removed. 2 (see FIG. 8B). In addition, at the bottom of the via hole pattern 51,
A part of the changed second low dielectric constant film 53 of the prepolymer film 50 may remain. Therefore, after heating the prepolymer film 50 to polymerize, the via hole pattern 51 is formed.
It is recommended that a cleaning step be performed on the bottom of the bed.

Thereafter, a first wiring conductor film 54 is grown on the second low dielectric constant film 53 so as to embed the wiring groove pattern 52 and the via hole pattern 51, and is selectively polished by a chemical mechanical polishing method or the like. As a result, the first low dielectric constant film
The second wiring 55 in which the wiring conductor film 54 is embedded and the second alignment wiring 56 are formed (FIG. 9A). The second wiring 55 is connected to a part of the first wiring 48 located on the base via the via hole pattern 51, and the second alignment wiring 56 is connected to the first alignment wiring 49 located on the base. It is connected.

Thereafter, if necessary, as shown in FIG. 9B, a second prepolymer film 57 is grown, and the second mold substrate 58 on which the second conductor convex pattern 59 is formed is formed. To form a second via hole pattern 60 and a second wiring groove pattern 61 in the second prepolymer film 57.
At this time, a voltage is applied between the extraction electrodes 44a 'and 44b' formed on the second mold substrate 58, and the alignment electrode 45 'made of the second conductor convex pattern 59 and the second alignment The contact resistance with the wiring 56 is measured, and alignment is performed based on the measurement result.

Further, by embedding the second wiring conductor film 63 in the second via hole pattern 60 and the second wiring groove pattern 61, the third wiring 64 and the third alignment wiring 6 are formed.
5, and a multilayer wiring is formed on the semiconductor substrate 1 on which the semiconductor element (not shown) shown in FIG. 10 is formed.

In the above-described embodiment, the alignment wires 49, 56, and 65 are shown at only one location on the silicon substrate. However, as shown in FIG. By forming a matching wire on the substrate 30 and measuring the contact resistance with the matching electrodes formed at two or more places on the substrate 30, complete matching in a two-dimensional plane can be performed. There is no limitation on the number of the alignment wires, but if the number is too large, the effective chip area is reduced. Therefore, it is recommended that a total of about three locations are provided, one each near three sides of the quadrilateral chip. .

Further, as shown in FIG. 12, the configuration of the mold substrate used for forming the wiring may be such that the tip of the alignment electrode 45 projects beyond the tip of the wiring base mold 46.

The mold substrate shown in FIG. 12 is a second modification of the mold substrate shown in FIG. 1, and a method of manufacturing the same will be described below.

In the method of manufacturing the mold substrate shown in FIG. 1, a structure in which the second conductor films 39 and 39 'are buried in the second openings 38 shown in FIG. 4B was obtained. Later, a third insulating film covering the whole is formed. Next, a third opening reaching a part 39 'of the second conductor film is formed in the third insulating film. Here, part 3 of the second conductor film
9 'indicates a portion to be the alignment electrode 45. Next, a conductive film is formed so as to cover the entirety, and the formed conductive film is selectively removed by a CMP method, an etch-back method, or the like, so that a portion embedded in the third opening is removed. Only the third convex pattern is left. Next, by selectively removing the first insulating film 34, the second insulating film 37, and the third insulating film, the first convex pattern 40 including the first conductive films 36 and 36 'is formed. 40 'and the second conductor film 3
As a result, there is obtained a structure composed of the conductor convex patterns 42, 42 'constituted by the second convex patterns 41, 41' composed of 9, 39 'and the third convex pattern composed of the third conductor film. Here, the portion to be the alignment electrode 45 is the wiring base mold 4.
A structure protruding from the portion 6 is obtained. The steps after the formation of the conductor convex patterns 42 and 42 'are the same as those in the method of manufacturing the mold substrate shown in FIG.

In the other method of manufacturing the mold substrate shown in FIG. 12, a process for obtaining a structure in which the portion serving as the alignment electrode 45 protrudes from the portion serving as the wiring mold 46 will be described below. In the method for manufacturing a mold substrate shown in FIG.
As shown in FIG. 4C, the conductor convex patterns 42, 42 '
After the structure composed of is formed, the conductive convex pattern 42 serving as the wiring base mold 46 is subjected to anisotropic etching, so that the part serving as the alignment electrode 45 protrudes from the part serving as the wiring base mold 46. The structure is obtained.

Further, among the other methods of manufacturing the mold substrate shown in FIG. 12, a process for obtaining a structure in which the portion serving as the alignment electrode 45 protrudes from the portion serving as the wiring base mold 46 will be described below. In the method of manufacturing a mold substrate shown in FIG. 1, as shown in FIG.
A second insulating film is formed on the conductive films 36 and 36 ′, and a second opening 38 reaching the first conductive film 36 is formed. Next, a conductor film is formed so as to cover the whole. At this time, the conductor film is embedded in the second opening 38.
Next, the conductor film on the second insulating film 37 is selectively removed by a chemical mechanical polishing method or the like. At this time, the upper part of the part 36 of the first conductor film is connected to the other part 3 of the first conductor film.
Excessive polishing from the upper part of the first conductor film 6 ′ causes the upper part of the other part 36 ′ of the first conductor film to become part 3 of the first conductor film.
6 to obtain a raised structure. Thereafter, FIG.
As shown in (c), when the first insulating film 34 and the second insulating film 37 are selectively removed, the surface insulating film 31 of the substrate 30 is removed.
On the upper side, there are formed first convex patterns 40, 40 'composed of first conductive films 36, 36' and second convex patterns 41, 41 'composed of second conductive films 39, 39'. Was
The conductor convex patterns 42 and 42 ′
A structure is obtained in which the portion that becomes 5 protrudes from the portion that becomes the wiring base mold 46.

As a second embodiment of the present invention, a multi-layer wiring manufacturing process using this substrate 30 'is described with reference to FIG.
(A), (b) and FIGS. 14 (a), (b) are shown below.

First, as shown in FIG. 13A, the substrate 30 'shown in FIG. In this case, the alignment electrode 4 formed on the substrate 30 '
5 and the first alignment wiring 4 formed on the semiconductor substrate 1
Only 9 contacts. At this time, fine adjustment is performed to align the substrate 30 ′ with the semiconductor substrate 1 so that the current value between the extraction electrodes 44 is minimized. Therefore, there is a feature that no scratch is generated on the wiring surface.

Next, as shown in FIG. 13B, the substrate 30 'is separated from the semiconductor substrate 1. At this time, a via hole pattern 51 and a wiring groove pattern 52 are formed in the prepolymer film 50, but the via hole pattern 51 does not reach the first wiring 48.

Next, as shown in FIG. 14A, the semiconductor substrate 1 is heated to polymerize the prepolymer film 50 into the second low dielectric constant film 53, and the entire surface is etched back. The via hole pattern 51 reaches the first wiring 48 located on the base.

Further, as shown in FIG.
By embedding the wiring conductor film 53 in the opening, the second wiring 55 and the second alignment wiring 56 can be provided with the second low dielectric constant 53.
Is formed.

Further, a third embodiment of the method of manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.

The third embodiment of the method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in the case where the mold substrate shown in FIG. 2 is used. This method of manufacturing a semiconductor device is characterized in that it includes a step of forming a low dielectric constant film by injecting a prepolymer after performing pressure bonding and alignment of a mold substrate.

FIGS. 15A, 15B, and 16 are views showing the manufacturing process of the third embodiment in the method of manufacturing a semiconductor device according to the present invention.

First, the first low dielectric constant film 47 is formed on the substrate 1.
Is formed, and a first wiring 48 and a first alignment wiring 49 are formed in the first low dielectric constant film 47.

Thereafter, the substrate 30 on which the conductor convex pattern 42 is formed as shown in FIG. A part of the conductor convex pattern 42 is a registration electrode 45, and the other is a wiring base mold 46. Further, an outflow prevention wall 421 is provided on the outer peripheral portion of the mold substrate to form the low dielectric constant film between the substrate 30 and a lower layer of the low dielectric constant film to be formed in a later step. It has the function of preventing the outflow of the prepolymer injected into the container.

The contact resistance between the alignment electrode 45 of the substrate 30 and the alignment wiring 49 provided on the substrate 1 is measured via the lead-out electrode 44, and the mold substrate is set so that the resistance value is minimized. 1 is slightly moved to perform the alignment.

Thereafter, as shown in FIG. 15A, air between the substrate 30 and the substrate 1 is exhausted through the through hole 77 to reduce the pressure between the substrate 30 and the substrate 1.

[0162] After evacuation of the air, as shown in FIG. 15 (b), from the through-hole 77, there is above the temperature T _LV, injecting prepolymer fluidized by heating to a temperature below T _P Thus, a prepolymer film 50 is formed between the substrate 30 and the substrate 1. Here, the prepolymer to be injected has fluidity at a temperature _TLV or higher, like the prepolymer forming the prepolymer film 50 used in the first embodiment of the method for manufacturing a semiconductor device of the present invention. Or thermoplastic), but at or above the temperature T _P (T _P >
T _LV ), a polymerization reaction occurs, and the polymer has a property of changing to a low dielectric constant film resin.

When a plurality of through holes 77 are provided, the above-described air exhausting step and the prepolymer injecting step may be performed simultaneously. At this time, for each through hole 77,
The one used in the air exhausting step and the one used in the prepolymer injecting step are defined.

After the formation of the prepolymer film 50, the mold substrate is heated by a heating plate provided on the substrate 30 to polymerize the prepolymer film 50, and then the substrate 30 is peeled off.

As shown in FIG. 16, the wiring groove pattern 52 and the via hole pattern 51 are transferred and formed on the low dielectric constant film 53 by the series of steps.

Thereafter, copper is buried in the wiring groove pattern 52 and the via hole pattern 51 at a time to form a multilayer wiring.

Here, in the third embodiment of the method of manufacturing a semiconductor device according to the present invention, since the substrate 30 and the substrate 1 do not always need to be placed in a vacuum vessel, the manufacturing equipment can be simplified.

As described above, according to the present invention, the mold substrate on which the conductor convex pattern is formed is transferred to the prepolymer film having high fluidity on the silicon substrate, and the via hole pattern and the wiring groove pattern are simultaneously formed. They are formed collectively.

The number of steps is greatly reduced as compared with the conventional method using a conventional photolithography step and a dry etching step. In addition, since a prepolymer film having a high fluidity is used, a large pressure is not required when the mold substrate is pressed.

Further, the method of minimizing the contact resistance between the alignment electrode formed on the mold substrate and the alignment wiring which is a part of the underlying wiring, by the method for adjusting the alignment accuracy between the die substrate and the silicon substrate. Improvements are being made.

That is, the present invention has a remarkable feature that the alignment is performed while measuring the electrical characteristics of the base substrate when the die substrate is pressed.

The first embodiment of the present invention will be described below with reference to the drawings. Here, as the prepolymer film, divinylsiloxane benzocyclobutene (DVS-BCB) monomer (hereinafter referred to as “DVS-BCB”) shown in Chemical Formula 1 is used.
Monomer ").

[0173]

Embedded image The chemical structure change from the DVS-BCB monomer to the DVS-BCB resin film is shown below. The DVS-BCB monomer is composed of two benzocyclobutenes each having a benzene ring and a four-membered ring (a cyclobutene group (a chemical formula is shown in [Chemical Formula 2])) as shown in [Chemical Formula 1]. And a vinyl siloxane comprising a vinyl group (chemical formula is represented by Chemical Formula 3) and a siloxane (chemical formula is represented by Chemical Formula 4). This DVS-BCB monomer is liquid at room temperature.

[0174]

Embedded image

[0175]

Embedded image

[0176]

Embedded image

[0177]

Embedded image When the DVS-BCB monomer is heated, first, a ring-opening reaction of the 4-membered ring of cyclobutene occurs to form two vinyl groups on the benzene ring (reaction formula is shown in [Formula 6]). Next, the vinyl group causes a polymerization reaction with the vinylsiloxane group of another DVS-BCB monomer to form tetrahydronaphthalene (reaction formula is shown in [Chemical Formula 7]), and a three-dimensional network polymer structure is formed. The resulting DVS-BCB resin film is formed (chemical formula is shown in [Chemical Formula 8]). DVS
-The heat resistance of the BCB resin film is 375 degrees Celsius or higher, and the relative dielectric constant of the BCB resin film is 2.7.

[0178]

Embedded image

[0179]

Embedded image

[0180]

Embedded image FIG. 17 shows DVS-BCB monomer and its DVS-B
The relationship between the temperature and the viscosity of each monomer in the partially crosslinked monomer that has been partially polymerized by heating the CB monomer, and the temperature required to be added to each monomer and the corresponding monomer are required to gel. It is a graph which shows the relationship with the gel time which shows time.

First, the DVS-BCB monomer is a liquid having a viscosity of 80 cP at room temperature. As the temperature rises, the viscosity decreases and changes to a low-viscosity flowing liquid of about 5 cP at 100 degrees Celsius. Although the viscosity decreases as the temperature further rises, at a temperature of 150 ° C. or more, the viscosity rapidly increases due to the progress of the polymerization reaction and gels (immobilizes).

Thus, the DVS-BCB monomer is 2
It has two characteristic temperatures (T _LV : fluidization temperature, T _P : gelation temperature). T _LV and T _P are each 100 degrees Celsius
Degrees and 150 degrees Celsius. These two characteristic temperatures can be controlled by heating and partially cross-linking the monomer. Referring to FIG. 17, partially crosslinked monomers, the absolute value of viscosity with temperature as indicated by T _LV increases also rises, the temperature indicated by T _P is slightly reduced. Here, as described for Example in the case of using the DVS-BCB monomer, and _{T LV} as a prepolymer film T
It is important to appropriately control _P and _P.

Next, using the DVS-BCB monomer,
FIGS. 18 and 19A show a first specific example of a method of manufacturing a semiconductor device according to the present invention when applied to the formation of a multilayer wiring on a MOSFET formed on a silicon substrate.
(B), FIG. 20, FIG. 21, FIG. 22 (a), and FIG.

First, an element isolation oxide film 6 is formed on a semiconductor substrate 1.
6 to form the MOSFET 67 separated. Next, the whole is covered with a BPSG film used as an inorganic interlayer insulating film 69, and its surface is flattened using a chemical mechanical polishing method (CMP method).

By penetrating the inorganic interlayer insulating film 69, the MOSF
After forming a contact hole reaching ET67, Ti (10
nm) / TiN barrier film (50 nm) is grown by a collimated sputtering method, and a tungsten film (60 nm) is formed by a thermal CVD method.
0 nm), and the contact plug 68 is formed by selectively removing tungsten on the surface of the BPSG film by a tungsten-CMP method.

Inorganic interlayer insulating film 69 and contact plug 6
A local wiring 70 is formed on the substrate 8 and a 1 μm thick SiO 2 used as an inorganic interlayer insulating film 69 ′ so as to cover the whole.
After growing the F film, the inorganic interlayer insulating film 69 ′ is formed by using the CMP method.
Is flattened. The thickness of the SiOF film after the planarization is about 0.6 μm.

The SiOF which is the inorganic interlayer insulating film 69 '
A first via hole made of tungsten reaching the local wiring 70 is formed in the film. On the SiOF film of the formed inorganic interlayer insulating film 69 ', a DBS-
After growing the BCB monomer film, it is heated at 300 degrees Celsius to polymerize, and the first low dielectric constant film 47 has a thickness of 0.6 μm.
The DVS-BCB resin film 73 of the degree is obtained.

Thereafter, a wiring groove photoresist pattern is formed in a photolithography process, and the formed photoresist and the DVS-BCB film 73 are etched back at a constant speed by a CHF ₃ -O ₂ plasma gas to obtain a first resist. Is formed in the DVS-BCB film 73.

Further, TaN / Ta is applied so as to cover the whole.
After a barrier film (10 nm / 5 nm) is grown by sputtering, a Cu film is formed to a thickness of 0.8 μm by MOCVD.
m on the DVS-BCB film 73 and Cu / Ta /
The TaN film is selectively removed by using the CMP method to form a first wiring 48 and a first alignment wiring 49 in which a Cu film (Ta / TaN film is not shown) is embedded in the first wiring groove. I do. In the CMP method used here, the polishing pressure was 0.2 kg while the alumina slurry was dropped at 50 ml / min.
/ Cm ² , substrate rotation 40 rpm, polishing pad rotation 60
rpm. After the execution of the CMP, alumina abrasive particles were removed by scrub cleaning using electrolytic ionized water.

Then, DVS-B was used as a prepolymer film.
The CB monomer film 72 was spin-coated. DVS-BCB
The thickness of the monomer film 72 is about 1 μm. Through the above-described steps, the semiconductor device shown in the cross-sectional view of the first specific example in the method for manufacturing a semiconductor device of the present invention shown in FIG. 18 is obtained.

On the other hand, as shown in FIG. 19A, a substrate 30 having a tungsten conductive pattern formed on a silicon substrate was formed.

A method for manufacturing the substrate 30 shown in FIG. 19A will be described below.

First, after forming a surface insulating film 31 on a silicon substrate, a base electrode 32 (thickness: 1 μm) of an aluminum alloy was formed, and an electrode insulating film 33 having a thickness of 1.5 μm was grown.

Thereafter, the surface of the electrode insulating film 33 is set to 0.5 μm
Is flattened by the CMP method, and
Expose part of

Thereafter, a silicon oxide film is grown to a thickness of 0.5 μm as a first insulating film, and a first opening is formed in the first insulating film by photolithography and dry etching.

After the Ti / TiN sputtering, tungsten as the first conductor film 36 is buried by W-CVD and W-CMP to form a first conductor pattern.
This first conductor pattern corresponds to DVS- shown in FIG.
An original pattern corresponding to the wiring groove formed in the BCB film 72 is obtained. A conductor is buried in this wiring groove in a later step. The conductor embedded in the wiring groove is the first wiring 5
It becomes 4.

Thereafter, silicon oxide is further grown to a thickness of 0.5 μm as a second insulating film, and a second opening is formed in the second insulating film by photolithography and dry etching.

The bottom surface of the second opening reaches the surface of the above-mentioned tungsten-embedded pattern, and the Ti / T
After the iN sputtering, tungsten as the second conductive film 39 is buried in the second opening by the W-CVD method and the W-CMP method to form a second conductive pattern. This second conductor pattern corresponds to the DVS-BCB film 7 shown in FIG.
2 is an original pattern corresponding to the via hole pattern to be formed. Here, the first conductor pattern and the second conductor pattern are electrically connected.

Thereafter, the silicon substrate is placed on CHF ₃
Expose in plasma. CHF _{3 in} plasma gas or C
F ₄ in the plasma gas, the etching of the silicon oxide selectively occurs. As a result, the first insulating film and the second insulating film are selectively etched, and the second conductive film 39 (on the first convex pattern 40 made of the first conductive film 36 (tungsten)) is formed. The conductor convex pattern 42 is formed by stacking the second convex patterns 41 made of tungsten).
In this specific example, the height of the first convex pattern 40 (tungsten) is 0.5 μm, and the height of the second convex pattern 41 (tungsten) is 0.5 μm. Here, the height of the first convex pattern 40 to be formed and the second convex pattern 41
Is not limited to this specific example, and is arbitrarily determined in accordance with the height that the wiring to be formed in a later step should have.

[0200] Then, 500 [mu] m ^□ (square) from the back surface of the silicon substrate is a substrate 30 about electrode extraction port 43
Is formed, and an aluminum extraction electrode is further formed. Further, a heating plate 75 for heating the substrate 30 is attached.

Incidentally, among the conductor convex patterns 42,
What is formed on the periphery of the base electrode 32 is the alignment electrode 45, and what is formed in the other area is the wiring base mold 46.

Next, the substrate 30 and the semiconductor substrate 1 on which the DVS-BCB monomer film 72 has been applied are placed in a vacuum vessel in a state where they face each other. At this time, coarse adjustment of the substrate 30 and the semiconductor substrate 1 is performed by an optical method. Thereafter, the pressure inside the vacuum vessel is reduced to about 1 torr, and the semiconductor substrate 1 is heated to about 120 degrees Celsius.

As shown in FIG. 17, above 100 ° C., the viscosity of the DVS-BCB monomer film shows a fluidity of 10 cP or less.

Thereafter, as shown in FIG. 19B, the substrate 30 on which the tungsten conductive pattern 42 is formed is pressed. The applied pressure is 0.01 to 0.5 kg / cm ²
It is about. At this time, the contact resistance between the alignment electrode 45 formed on the substrate 30 and the first alignment wiring 49 formed on the semiconductor substrate 1 is measured via the extraction electrode 44, and the contact resistance value is determined. The alignment is performed by slightly moving the substrate 30 and the semiconductor substrate 1 until the minimum value is reached.

Thereafter, the DVS-BC is passed through the heating plate 75.
The B monomer film 72 is heated at 200 degrees Celsius for several minutes, and the substrate 30 is separated. As shown in FIG. 17, at 200 degrees Celsius, the DVS-BCB monomer film 72 gels (immobilizes) in a few minutes.

As a result, as shown in FIG.
The wiring groove 52 to which the first convex pattern 40 is transferred and the via hole pattern 51 to which the second convex pattern 41 is transferred are formed in the BCB monomer film 72, and are stably maintained.

In practice, as shown in FIG.
The size of the substrate 30 is smaller than that of the semiconductor substrate 1.
Is repeated to transfer a plurality of opening patterns.

In the case of this specific example, the wiring groove depth is 0.5 μm
Thus, the depth of the via hole from the bottom of the wiring groove to the first wiring 48 is 0.5 μm. To form a deep wiring groove or via hole having a large aspect ratio, the substrate 30
In this case, the height of the conductor convex pattern to be formed may be increased.

After transferring the convex pattern formed on the mold substrate to almost the entire surface of the semiconductor substrate 1, the semiconductor substrate 1 is moved to 30 degrees Celsius.
By heating to about 0 degrees, the DVS-BCB monomer film 72 is completely polymerized, and the second low dielectric constant film 53 made of the DVS-BCB resin film is obtained. This complete polymerization reaction may be performed in the vacuum vessel, or may be performed after being taken out of the vacuum vessel.

Thereafter, oxygen plasma at a pressure of 10 mtorr was irradiated for several tens of seconds using an ECR plasma RIE apparatus.
The DVS-BCB resin film remaining on the bottom of the via hole pattern 51 is removed.

Thereafter, the substrate is exposed to H ₂ plasma while the substrate is heated to 250 degrees Celsius, and the first wiring 48 made of copper is formed.
The oxide film on the surface is removed, and TaN / T
a Barrier film (thickness: 10 nm / 5 nm: not shown) is grown, and a Cu film is grown to a thickness of about 1 μm by MOCVD.

Thereafter, the Cu / Ta / TaN film on the second low dielectric constant film 53 made of a DVS-BCB resin film is
The second wiring 55 and the second alignment wiring 56 in which copper is embedded are selectively removed by using the P method (FIG. 22).
(A)). The CMP method used here employs a polishing pressure of 0.2 while dropping an alumina slurry at 50 ml / min.
Polishing is performed at a substrate rotation of 40 rpm and a polishing pad rotation of 60 rpm at kg / cm ² . After this polishing, the alumina abrasive particles were removed by scrub cleaning using electrolytic ionized water.

Further, by repeating the steps of coating and forming a DVS-BCB monomer film and press-bonding, aligning and peeling steps of the mold substrate, as shown in FIG. 22B, a third film made of a DVS-BCB resin film is formed. It is possible to obtain a multilayer wiring in which a third wiring 64 and a third alignment wiring 65 in which copper is embedded are formed in the low dielectric constant film 62 of FIG.

In the above specific example, DVS-BCB is used as the prepolymer. However, a polyimide monomer or an allyl ether monomer may be used as the prepolymer.

Next, a second specific example of the method for manufacturing a semiconductor device according to the present invention will be described below.

In the first specific example, after a DVS-BCB monomer film, which is a prepolymer film, was formed on a silicon substrate by coating, a die substrate was subjected to pressure bonding / registration / separation steps.

In the second specific example, FIG.
(B) As shown in FIG. 24, the prepolymer is injected after performing the press-fitting and aligning steps of the mold substrate.

First, as shown in FIG. 23A, a DVS-BC as a first low dielectric constant film 47 is formed on a semiconductor substrate 1.
A first wiring 48 and a first alignment wiring 49 are formed by forming a B resin film and embedding copper in a first low dielectric constant film 47.

After that, the substrate 30 on which the conductor convex pattern 42 is formed is made to face. A part of the conductor convex pattern 42 is a registration electrode 45, and the other is a wiring base mold 46.
Further, the outermost peripheral portion of the present mold substrate is surrounded by a conductor convex pattern 42.

The contact resistance between the alignment electrode 45 of the substrate 30 and the first alignment wiring 49 on the semiconductor substrate 1 is measured via the lead-out electrode 44, and a metal mold is formed so that the resistance value is minimized. The alignment is performed by slightly moving the substrate 1.

Thereafter, air is exhausted from the through hole 77 formed in the substrate 30 to reduce the pressure between the substrate 30 and the semiconductor substrate 1.

Thereafter, the DBS-BCB monomer fluidized by heating to about 100 degrees Celsius is injected from the through-hole 77, thereby forming the substrate 30 and the semiconductor substrate 1 as shown in FIG. The DVS-BCB monomer film 72 is filled in between.

Thereafter, the DVS-BCB is heated by heating the mold substrate to 200 degrees Celsius with a heating plate provided on the substrate 30.
The monomer film 72 is polymerized to form a low dielectric constant film D
After forming the VS-BCB resin film 73, the substrate 30 is peeled off.

By the above series of steps, as shown in FIG. 24, the wiring groove pattern 52 and the via hole 51 can be transferred and formed on the DVS-BCB resin film 73. Thereafter, copper is buried in the wiring groove pattern 52 and the via hole pattern 51 at a time to form a multilayer wiring.

In the case of the second specific example, the substrate 3
Since there is no need to put the semiconductor substrate 1 and the semiconductor substrate 1 in a vacuum container, the manufacturing equipment can be simplified.

As described above, in the present invention, the mold substrate on which the conductor convex pattern is formed is transferred to a fluid prepolymer film on a silicon substrate, and the via hole pattern and the wiring groove pattern are transferred. Are simultaneously and collectively formed. Compared with the conventional method using a conventional photolithography process and a dry etching process, the number of processes is greatly reduced.

In addition, since a prepolymer film having a high fluidity is used, a large pressure is not required when the mold substrate is pressed. From this,
Damage and destruction to the substrate can be reduced.

Further, the method of minimizing the contact resistance between the alignment electrode formed on the mold substrate and the alignment wiring which is a part of the underlying wiring, improves the alignment accuracy between the mold substrate and the silicon substrate. Is planned.

That is, the present invention has a remarkable feature that the alignment is performed while measuring the electrical characteristics of the base substrate when the die substrate is pressed.

As a result, a multilayer wiring using a low dielectric constant interlayer film can be efficiently formed without using a photoresist mask, and the manufacturing cost and connection reliability of the multilayer wiring can be greatly improved.

[0231]

The present invention has the effect of reducing the number of steps as compared with the conventional method using a conventional photolithography step and a dry etching step.

Further, it has the effect of improving the accuracy of alignment between the mold substrate and the silicon substrate.

Further, there is an effect that a multilayer wiring using a low dielectric constant interlayer film is formed without using a photoresist mask.

[Brief description of the drawings]

FIG. 1 is a view showing a mold substrate which is a semiconductor device manufacturing apparatus according to the present invention.

FIG. 2 is a view showing a modified example of a mold substrate which is an apparatus for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a view showing a manufacturing process of a mold substrate which is an apparatus for manufacturing a semiconductor device according to the present invention.
(C) is a cross-sectional view of the manufacturing process of the mold substrate according to the present invention.

FIG. 4 is a view showing a manufacturing process of a mold substrate which is a semiconductor device manufacturing apparatus according to the present invention, which is shown in FIGS.
(C) is a cross-sectional view of the manufacturing process of the mold substrate according to the present invention.

FIG. 5 is a view showing a modified example of a mold substrate which is an apparatus for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a sectional view showing a manufacturing step according to the first embodiment in the method for manufacturing a semiconductor device of the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing step according to the first embodiment in the method for manufacturing a semiconductor device of the present invention.

FIG. 8 is a cross-sectional view showing a manufacturing step according to the first embodiment in the method for manufacturing a semiconductor device of the present invention.

FIG. 9 is a cross-sectional view showing a manufacturing step according to the first embodiment in the method for manufacturing a semiconductor device of the present invention.

FIG. 10 shows a first example of the semiconductor device manufacturing method according to the present invention.
It is sectional drawing which shows the manufacturing process by 2nd Embodiment.

FIG. 11 is a top view of a semiconductor chip showing a position where a registration wiring pattern is formed according to the present invention. It is sectional drawing.

FIG. 12 is a view showing a second modified example of a mold substrate which is a semiconductor device manufacturing apparatus according to the present invention.

FIG. 13 shows a second example of the method of manufacturing a semiconductor device according to the present invention.
It is sectional drawing which shows the manufacturing process by 2nd Embodiment.

FIG. 14 shows a second example of the method of manufacturing a semiconductor device according to the present invention.
It is sectional drawing which shows the manufacturing process by 2nd Embodiment.

FIG. 15 shows a third example of the method of manufacturing a semiconductor device according to the present invention.
It is sectional drawing which shows the manufacturing process by 2nd Embodiment.

FIG. 16 shows a third example of the method of manufacturing a semiconductor device according to the present invention.
It is sectional drawing which shows the manufacturing process by 2nd Embodiment.

FIG. 17 is a diagram showing temperature characteristics of a DVS-BCB monomer film which is a prepolymer film.

FIG. 18 shows a first example of the method of manufacturing a semiconductor device according to the present invention.
It is sectional drawing which shows the process of a specific example.

FIG. 19 is a diagram illustrating a first example of the method of manufacturing a semiconductor device according to the present invention;
It is sectional drawing which shows the process of a specific example.

FIG. 20 shows a first example of the method of manufacturing a semiconductor device according to the present invention.
It is sectional drawing which shows the process of a specific example.

FIG. 21 is a top view of a semiconductor substrate in a method of manufacturing a semiconductor device according to the present invention.

FIG. 22 shows a first example of the method of manufacturing a semiconductor device according to the present invention.
It is sectional drawing which shows the process of a specific example.

FIG. 23 shows a second example of the method for manufacturing a semiconductor device of the present invention.
It is sectional drawing which shows the process of a specific example.

FIG. 24 shows a second example of the method of manufacturing a semiconductor device according to the present invention.
It is sectional drawing which shows the process of a specific example.

FIG. 25 is a process sectional view illustrating the first related art.

FIG. 26 is a process cross-sectional view illustrating a second conventional technique.

FIG. 27 is a process cross-sectional view illustrating a third conventional technique.

FIG. 28 is a process cross-sectional view illustrating a fourth conventional technique.

FIG. 29 is a process cross-sectional view illustrating a fifth conventional technique.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 silicon oxide film 3 low dielectric constant interlayer film 4 first mask film (silicon oxide film) 5 second mask film (titanium nitride film) 6 photoresist 7, 7a, 7b, 7c, 7d wiring groove 8 Cu film Reference Signs List 9 Cu damascene wiring 10 Mold 11 Convex pattern 12 Thermoplastic resin film (PMMA film) 13 Concave pattern 14 Metal film 15 Metal film pattern 16 Silicon carbide plate 17 Concave pattern transferred to metal film 18 Fluororesin substrate 19 Copper foil Reference Signs List 20 Fluororesin substrate with copper foil 21 Copper foil concave pattern 22 Copper foil part to be convex 23 Copper foil circuit pattern 24 Catalyst core for chemical plating 25 Resin substrate 26 Chemical plating solution 27 Unnecessary copper film 28 Blade 29 Copper circuit pattern 30 , 30 'substrate 30a lower surface insulating film 31 surface insulating film 32 base electrode 33 electrode insulating film 34 first insulating film 35 first opening 36, 36 ′ First conductive film 37 Second insulating film 38 Second opening 39, 39 ′ Second conductive film 40, 40 ′ First convex pattern 41, 41 ′ Second convex pattern 42, 42 'Conductor convex pattern 421 Outflow prevention wall 43 Electrode extraction hole 44, 44a, 44b, 44a', 44b 'Extraction electrode 45, 45' Coupling electrode 46 Wiring element type 47 First low dielectric constant film 48 First 1 wiring 49 first alignment wiring 50, 50 ′ prepolymer film 51 via hole pattern 52 wiring groove pattern 53 second low dielectric constant film 54 first wiring conductor film 55 second wiring 56 second eye Matching wiring 57 Second prepolymer film 58 Second mold substrate 59 Second conductor convex pattern 60 Second via hole pattern 61 Second wiring groove pattern 62 Third low dielectric constant film 63 Second wiring Conductor film 64 Third wiring 65 Third alignment wiring 66 Device isolation oxide film 67 MOSFET 68 Contact plug 69, 69 'Inorganic interlayer insulating film 70 Local wiring 71 First via hole plug 72 DVS-BCB monomer film 73 DVS-BCB resin film 75 Heating plate 76 Opening pattern formed by pressing and peeling process of mold substrate 77 Through hole

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E344 AA01 AA22 BB06 CC23 DD08 EE23 5F033 HH11 HH21 HH32 JJ11 JJ21 JJ32 KK09 KK18 KK19 KK33 MM01 PP11 PP15 PP22 QQ09 QQ11 QQ31 QQ37 QQ48 RQ04 RR11 RRRR

Claims (28)

[Claims] An insulating layer forming step of forming an insulating layer on a semiconductor substrate; a wiring layer embedding step of embedding a wiring layer including a matching conductor portion in the insulating layer; Forming a concave pattern, forming a concave pattern on the low dielectric constant layer by compressing a convex pattern, and wherein the convex pattern has a convex pattern alignment conductor portion, Based on the electrical characteristics obtained when the convex pattern alignment conductor portion and the alignment conductor portion are brought into contact, the position where the convex pattern is pressed is determined, and the low dielectric layer is A conductor embedding step of embedding a conductor in the concave pattern, the conductor embedding step being made of a low dielectric constant film having a lower dielectric constant than a silicon oxide film or a silicon nitride film. 2. The semiconductor device according to claim 1, wherein an element is provided on the semiconductor substrate, and the alignment conductor is electrically connected to the element. Production method. 3. The method according to claim 1, wherein the insulating layer is made of the low dielectric constant film. 4. The step of forming a concave pattern includes a step of applying a prepolymer on the insulating layer at a temperature lower than a polymerization temperature, wherein the prepolymer is heated to a temperature higher than the polymerization temperature. Then, a polymerizing reaction occurs to become a low dielectric constant polymer, a pattern forming step of pressing a convex pattern to form a concave pattern on the prepolymer, and a position where the convex pattern is pressed. Is determined based on the electrical characteristics obtained when the convex pattern alignment conductor is brought into contact with the alignment conductor, and the prepolymer in which the concave pattern is formed by the pattern forming step is Forming a low dielectric constant film made of a low dielectric constant polymer by heating to a temperature higher than the polymerization temperature, wherein the low dielectric constant film is formed. 4. The method according to claim 1, wherein the film has a lower dielectric constant than a silicon oxide film or a silicon nitride film. 5. 5. The step of forming a concave pattern, the step of arranging a convex pattern on the insulating layer;
Here, the arrangement of the convex patterns is determined based on electrical characteristics obtained when the convex pattern alignment conductor is brought into contact with the alignment conductor, and is arranged by the arrangement step. Injecting a prepolymer at a temperature lower than the polymerization temperature into the gap between the convex pattern and the insulating layer, wherein the prepolymer is heated to the polymerization temperature or higher, A low dielectric constant polymer is formed by causing a polymerization reaction to form a low dielectric constant polymer, and heating the prepolymer injected by the injection step to a temperature higher than the polymerization temperature to form a low dielectric constant film made of the low dielectric constant polymer. 4. The method according to claim 1, further comprising the step of forming a low dielectric constant film, wherein the low dielectric constant film has a lower dielectric constant than a silicon oxide film or a silicon nitride film. The method of manufacturing a semiconductor device according. 6. A concave pattern forming step of forming a low dielectric constant layer on a semiconductor substrate provided with elements and pressing a convex pattern to form a concave pattern in the low dielectric constant layer; The convex pattern has a convex pattern alignment conductor, and a position where the convex pattern is crimped based on electrical characteristics obtained when the convex pattern alignment conductor and the element are brought into contact with each other. Wherein the low dielectric constant layer is made of a low dielectric constant film having a lower dielectric constant than a silicon oxide film or a silicon nitride film, and a conductive film burying step of burying a conductive film in the concave pattern. Device manufacturing method. 7. The step of forming a concave pattern includes a step of coating a prepolymer on the semiconductor substrate, wherein the prepolymer is heated to a temperature higher than a polymerization temperature. And forming a concave pattern on the prepolymer by pressing a convex pattern to form a concave pattern, wherein a position at which the convex pattern is pressed is determined by the convex pattern registration conductor section. Is brought into contact with the alignment conductor portion, determined based on the electrical characteristics obtained at that time, and heating the prepolymer on which the concave pattern is formed by the pattern forming step to a temperature equal to or higher than the polymerization temperature. Forming a low-k film made of a low-k polymer, wherein the low-k film is a silicon oxide film or a low-k film. The method according to claim 6, wherein the semiconductor device has a lower dielectric constant than the silicon nitride film. 8. The step of forming a concave pattern includes the step of arranging a convex pattern on the semiconductor substrate, and the step of arranging the convex pattern includes the step of aligning the convex pattern registering conductor portion with the semiconductor substrate. An injection step of injecting a prepolymer into a gap between the convex pattern and the semiconductor substrate, which is determined based on electrical characteristics obtained at the time of contact with the conductor portion, and When the prepolymer is heated to a polymerization temperature or higher, a polymerization reaction occurs to become a low dielectric constant polymer, and the prepolymer injected by the injection step is heated to the polymerization temperature or higher. Forming a low-k film made of a low-k polymer, wherein the low-k film is a silicon oxide film or a silicon oxide film. The method for manufacturing a semiconductor device according to claim 6, wherein the dielectric constant is lower than that of the con-nitride film. 9. The prepolymer exhibits thermoplasticity when heated to a plastic temperature having a predetermined temperature range from a room temperature or higher to a temperature lower than the polymerization temperature, and the pattern forming step includes: The method for manufacturing a semiconductor device according to claim 4, further comprising a heating step of heating the semiconductor device to the plastic temperature. 10. The prepolymer exhibits a thermoplasticity when heated to a plastic temperature having a predetermined temperature range from a room temperature or higher to a temperature lower than the polymerization temperature, and the injecting step includes: The method of manufacturing a semiconductor device according to claim 4, further comprising a heating step of heating to the plastic temperature. 11. The semiconductor device according to claim 4, wherein the prepolymer is made of any one of a divinylsiloxane benzocyclobutene monomer, a polyimide monomer, and an allyl ether monomer. Production method. 12. The prepolymer according to claim 4, wherein the prepolymer is composed of divinylsiloxane benzocyclobutene monomer, and the polymerization temperature is 150 degrees Celsius. A method for manufacturing a semiconductor device. 13. The convex pattern according to claim 1, wherein the convex pattern includes a two-layer pattern including a first convex pattern and a second convex pattern provided on the first convex pattern. 13. The method for manufacturing a semiconductor device according to item 5. 14. The method of manufacturing a semiconductor device according to claim 13, wherein the convex pattern registration conductor portion is formed of the two-layer pattern. 15. The semiconductor device according to claim 1, wherein the electric characteristic is a current value obtained when a voltage is applied to the convex pattern alignment conductor. Manufacturing method. 16. A semiconductor device manufacturing apparatus for forming a concave pattern on a low dielectric constant layer or an insulating layer provided on a lower layer having a conductor portion for alignment, comprising: A plurality of convex portions which are not connected to each other, and at least one of the plurality of convex portions has a convex pattern alignment conductor portion composed of two or more convex portions.
A pair of lead wires individually and electrically connected to a pair of protrusions of the respective convex pattern alignment conductors;
Here, the position at which the concave pattern is formed is based on the electrical characteristics of the mating portion electrically connected to the mating portion via the matching conductor portion and measured through the pair of lead-out wires. Defined semiconductor device manufacturing equipment. 17. The method according to claim 17, wherein the plurality of convex portions include a two-layer pattern including a first convex pattern provided on the substrate and a second convex pattern provided on the first convex pattern. An apparatus for manufacturing a semiconductor device according to claim 16. 18. The apparatus for manufacturing a semiconductor device according to claim 17, wherein said two or more projections forming said alignment portion are made of said two-layer pattern. 19. The apparatus for manufacturing a semiconductor device according to claim 16, further comprising a hole penetrating the substrate and extending from the bottom of the substrate to the projection. 20. The semiconductor device manufacturing apparatus according to claim 16, further comprising a heating unit for heating said substrate. 21. The semiconductor device according to claim 16, wherein the electric characteristic is a current value obtained when a voltage is applied to the pair of lead wires. apparatus. 22. An apparatus for manufacturing a semiconductor device for forming a concave pattern on a low dielectric constant layer or an insulating layer provided on a lower layer having a conductor portion for alignment, comprising the steps of: forming an insulating film on a substrate; An opening forming step of forming an opening; a conductor film embedding step of embedding a conductive film in the opening; a removing step of selectively removing the insulating film; wherein the conductive film is electrically A plurality of projections that are not connected to each other; and among the plurality of projections, for each of the alignment conductive projections including at least one set of projections, the alignment is performed by penetrating the substrate from the lower surface of the substrate. A lead wiring forming step of forming a lead wiring reaching each of the conductive projections for use in a semiconductor device. 23. The substrate, comprising a metal conductor substrate or a semiconductor substrate, wherein the step of embedding the conductor film comprises a step of embedding a conductor film so as not to be electrically connected to the substrate. 23. The method of manufacturing a semiconductor device manufacturing apparatus according to claim 22, wherein a lead wiring is formed so as not to be electrically connected to the substrate. 24. An apparatus for manufacturing a semiconductor device for forming a concave pattern on a low dielectric constant layer or an insulating layer provided on a lower layer having a conductor portion for alignment, comprising the steps of: An insulating film forming step of forming an insulating film; an opening forming step of forming an opening in the wiring insulating film; a conductor film embedding step of embedding a conductor film in the opening; and selecting the wiring insulating film. A removing step for removing the target;
Here, the conductive film includes a plurality of protrusions that are not electrically connected to each other. Of the plurality of protrusions, each of the alignment conductive protrusions including at least one set of protrusions is A lead wiring forming step of forming a lead wiring extending from the lower surface of the substrate to each of the conductive protrusions for alignment by penetrating the substrate, and a method of manufacturing a semiconductor device manufacturing apparatus, comprising: 25. An upper insulating film forming step for forming an upper insulating film covering the insulating film and the conductor film, and an upper opening forming step for forming an upper opening reaching the conductor film in the upper insulating film. 25. The method according to claim 22, further comprising: embedding an upper conductive film in the upper opening, wherein the removing step comprises a step of selectively removing the insulating film and the upper insulating film. 13. A method of manufacturing a semiconductor device manufacturing apparatus according to any one of 26. The step of forming an upper opening, further comprising: forming an upper opening reaching the conductor film in the upper insulating film on the conductor film to be the conductive protrusion for alignment. 26. The method of manufacturing a semiconductor device manufacturing apparatus according to claim 25, comprising: 27. The method according to claim 22, further comprising a step of forming a hole extending from the back surface of the substrate to the convex pattern through the substrate. 28. The method of manufacturing a semiconductor device manufacturing apparatus according to claim 22, further comprising a heating unit forming step of forming a heating unit for heating said substrate.