JP2000307109A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a protective element to be formed by a method wherein a semiconductor layer whose conductivity type is opposite to that of the primary surface of a semiconductor substrate is formed on a gap on the primary surface of the substrate where an insulating film is formed in a prescribed region. SOLUTION: Diodes serving as protective elements are provided separate from each other by a gap in a region where filed insulating films 3 are formed. Diodes or N+-type polycrystalline silicon layers 17a and P-type polycrystalline silicon layers 17b are alternately arranged on field insulating films 3 which surround the wirings of gate 4. A punch-through structure where rectangular rings 16 of floating P-type diffusion layers are arranged around a source wiring which serves as the terminal of a chip, and a depletion layer extends outwards from the inner rings before an avalanche breakdown starts with an increase in an applied voltage is provided. By this setup, a parasitic MISFET is prevented from being formed, a semiconductor element of this constitution can be prevented from deteriorating in withstand voltage, a P-type layer usually provided under an insulating film can be dispensed with, and manufacturing processes can be reduced in number.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and, more particularly, to a technology effective when applied to a semiconductor device provided with a protection element for preventing the destruction of the element due to, for example, an external surge voltage.

[0002]

2. Description of the Related Art In a MISFET having an insulated gate structure, a thin insulating film blocks the gate and the source. When a silicon oxide film having a thickness of 50 nm to 100 nm is used as the insulating film, the withstand voltage is approximately 40 V to 60 V. Then, when a voltage exceeding the breakdown voltage is applied between the gate and the source due to an external surge voltage or the like, the insulating film is broken, and does not function as an FET. In order to prevent such destruction, a semiconductor device equipped with a protection element is often used.

As such a protection element, a diode formed of polycrystalline silicon has an n-channel power MISF.
An example in which the ET is mounted between the gate and the source will be described with reference to FIGS. FIG. 1 shows a chip plane layout of a power MISFET on which a diode formed of polycrystalline silicon is mounted, FIG. 2 shows an enlarged view of a portion shown by a broken line in FIG. 1, and FIG. 3 shows a longitudinal section taken along line a. In FIG. 2, a metal wiring layer serving as a source electrode or a gate pad is omitted to facilitate understanding.

This power MISFET has a configuration in which a plurality of vertical MISFET cells are integrated on a main surface of a semiconductor substrate and connected in parallel. The drain region of each cell is shared and connected to the drain electrode formed on the back surface of the semiconductor substrate, and the source region is connected in parallel by the source electrode. The gates are connected to each other, connected to a gate wiring at an outer peripheral portion of the cell region, and the gate wiring is connected to a gate pad. The diode formed between the gate and the source is formed so as to surround the gate pad. The termination of these chips is FLR (Field Limiting Ri
ng).

[0005] The MISFET is formed on an n + type semiconductor substrate 1 made of, for example, single crystal silicon, and on a semiconductor substrate on which an n− type layer 2 is formed by, for example, epitaxial growth. These MISFETs are configured by regularly arranging a plurality of cells in a cell region surrounded by a field insulating film 3 provided in a rectangular ring shape having an arcuate corner along the outer periphery of a semiconductor substrate. I have.

The gate 4 of each cell is provided on the main surface of the semiconductor substrate with a gate insulating film 5 interposed therebetween, adjacent gates 4 are continuously provided, and connected to the gate wiring 6 at the outer periphery of the cell region. . The gate wiring 6 is connected to a gate pad 7 serving as a connection region of the gate 4. In each cell, the n− type layer 2 formed on the n + type semiconductor substrate 1 becomes a drain region, the p type layer 8 formed on the n− type layer 2 becomes a base region where a channel is formed, The n + type layer 9 formed in the type layer 8 is a vertical FET serving as a source. The source electrode 11 provided in the cell region is connected to the n + type layer 9 serving as a source via an interlayer insulating film 10. In addition to the n + -type layer 9, the source electrode 11 includes a p + -type layer 12 provided in the p-type layer 8 for keeping the base potential constant.
It is also electrically connected.

[0007] Around the field insulating film 3, a source wiring 14 is provided in a rectangular ring shape.
It is connected to the p-type layer 13. The source wiring 14 is shown in FIG.
As is apparent from FIG.

An FLR having a plurality of rectangular annular rings 16 made of a floating p-type diffusion layer is provided around a source wiring 14 serving as a terminal of the chip. In this FLR, as the applied voltage increases, the inner ring 16 moves to the outer ring 1 before avalanche breakdown occurs.
6, a depletion layer extends to punch through. Although two rings are shown, a required withstand voltage can be obtained by changing the number of stages. If the withstand voltage is about 60 V or less, the floating ring 16 may not be provided.

A diode 17 serving as a protection element is provided on the field insulating film 3. One end of the diode 17 is electrically connected to the gate pad 7, and the other end is connected to the source electrode 11 or the source wiring 14. It is electrically connected.

The diode 17 is formed by alternately arranging n + -type layers 17a and p-type layers 17b using, for example, polycrystalline silicon. In the illustrated example, four stages of pn junctions are formed bidirectionally, but a desired breakdown voltage can be obtained by changing the number of stages. p
Assuming that the breakdown voltage of one stage of the n-junction is 7V, a four-stage diode is a bidirectional diode that breaks down at 28V. For example, in a power MISFET having a gate insulating film thickness of 100 nm, when a voltage generated between the gate and the source becomes about 60 V or more due to an external surge voltage or the like, the gate insulating film is broken. However, when this diode is mounted between the gate and the source, the diode breaks down when the voltage generated between the gate and the source reaches about 28 V due to an external surge voltage or the like, and the diode becomes a bypass. No further voltage is applied between the gate and source,
Destruction of the gate insulating film can be prevented.

Further, a p-type semiconductor layer 15 is formed below the field insulating film 3, and the semiconductor layer 15 is connected to a p-type layer 18 connected to the source wiring 14. This field insulating film 3 has a parasitic M
It is provided to prevent the formation of an ISFET. If the field insulating film 3 is not provided, that is, if the base insulating film of the protection diode 17 is thin as much as the thickness of the gate insulating film, the impurity concentration voltage is applied to the gate while the source and the drain are grounded. Is applied, the lower surface of the p-type layer 17b in contact with the field insulating film 3 becomes n-type inverted and becomes a channel, and a parasitic MISFET having the n + -type layer 17a as a source region and a drain region is formed in the protection diode 17. I will.

If the underlying insulating film of the protection diode 17 is thin and the p-type layer 15 is not provided, when a positive voltage is applied to the drain 2 and the gate 4 with the source 11 grounded, the field The lower surface of the p-type layer 17b in contact with the insulating film 3 becomes n-type inverted and forms a channel, and a parasitic MISFET having the n + -type layer 17a as a source region and a drain region is formed in the protection diode 17. In order to prevent such a parasitic operation, an insulating film thicker than the gate insulating film is required as a base of the protection diode 17.

As a protection element, on a field insulating film,
For example, a device mounted with a diode formed of polycrystalline silicon is disclosed in Japanese Patent Publication No. 5-63919, and a device mounted with a diode and a resistor formed of polycrystalline silicon is disclosed in Japanese Patent Application Laid-Open No. 10-125907. I have. In each case, a semiconductor layer of the opposite conductivity type to the main surface of the semiconductor substrate is formed under the field insulating film on which the protection element is formed.

Next, the p-type layer 15 formed under the insulating film provided with the diode and the power MISFE
The relationship between T and the breakdown voltage will be described with reference to FIGS. In FIG. 4, the semiconductor layer 15 formed under the field insulating film 3 is a main junction connected to GND,
The FLR is formed on the outer periphery. The main junction is a p-type fixed to the source potential (GND) of the power MISFET.
Type diffusion layer. The FLR is one in which rings 16 of floating p-type diffusion layers are arranged at appropriate intervals. FIG. 4 shows the semiconductor layer 15 in the power MISFET.
Are simplified for easy understanding.

First, the breakdown voltage of the main junction and the FLR will be described. With an increase in the applied voltage, P0 (main junction of GND) is first depleted (shown by a dashed line). As the applied voltage is further increased, the depletion layer extends to FLR,
Punch through to ring P1 before avalanche breakdown occurs at junction 0. And, as the voltage further increases, P
Punch-through is sequentially performed on P2 and P3 (shown by a two-dot chain line), and finally the outermost ring bond yields. If the diffusion depth of each ring is sufficiently deep, the breakdown voltage BV of the FLR having n rings arranged at equal intervals is the punch-through breakdown voltage BVpt between the rings and the breakdown voltage of the cylindrical joint of the nth ring. From BVcy, BV ≒ nBVpt + BVcy can be expressed by the following equation (1). That is, in this structure, the breakdown voltage is F
It is determined by the spacing and number of LR rings and is not affected by the main joint. Therefore, the breakdown voltage of the FLR section is theoretically
The value is represented by Expression (1).

Next, as shown in FIG. 5, when a plurality of main junctions connected to GND are formed at intervals L, if the interval L between the main junctions P0 is narrow, a plurality of main junctions P0 are formed.
Depletion layers extending from N to the n − -type layer are connected to each other to form one depletion layer (shown by a dashed line). The depletion layer becomes easier to connect as the distance L between the main junctions P0 is reduced, and the shape of the depletion layer approaches an ideal flat junction having no curvature, and the breakdown voltage is improved. Conversely, if the distance L between the main junctions P0 is increased, the respective depletion layers are less likely to be connected, and the breakdown voltage is reduced. Ultimately, in the state where no depletion layer is connected, the breakdown voltage decreases to the breakdown voltage of the cylindrical junction having the curvature corresponding to the diffusion depth.

The inventor conducted an experiment on the breakdown voltage when the distance L between the p-type layers was changed, and the results are shown in FIG. The withstand voltage is substantially inversely proportional to the interval L between the p-type layers, and if the interval between the p-type layers is reduced to about 5 μm, a withstand voltage close to the withstand voltage of the FLR can be obtained. .

Referring again to the structure of the conventional diode shown in FIG. 3, if the p-type semiconductor layer 15 is not provided below the insulating film on which the diode 17 is formed, the p-type layer 8 serving as a channel and the source It can be seen that the distance between the wiring 14 and the p-type layer 18 to which the wiring 14 is connected is very wide, and the withstand voltage is significantly reduced for the above-described reason.

[0019]

However, in the conventional structure, the formation of the p-type semiconductor layer 15 must be performed in a step before the formation of the field insulating film. Since there is no impurity introduction step, at least a photolithography step, an impurity implantation step, and a heat treatment step for activation are required only for forming the p-type layer, and the number of steps is increased. There was a point.

An object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide a technique capable of forming a protection element. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0021]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. In a semiconductor device in which a semiconductor element is formed on an insulating film formed in a predetermined region of a semiconductor substrate main surface, the insulating film is formed with a gap in the region,
A semiconductor layer of a conductivity type opposite to the semiconductor substrate main surface is formed on the semiconductor substrate main surface located in the gap.

More specifically, in a semiconductor device in which a power MISFET is formed in a cell region defined by an insulating film formed in a predetermined region on a main surface of a semiconductor substrate, and a semiconductor element is formed on the insulating film. Forming the insulating film with a gap in the region, and forming a semiconductor layer of a conductivity type opposite to the semiconductor substrate main surface on the semiconductor substrate main surface located in the gap. In the manufacturing method, a step of forming the insulating film on the main surface of the semiconductor substrate with a gap in the region; and a step of forming a conductive type opposite to the main surface of the semiconductor substrate on the main surface of the semiconductor substrate located in the gap. Forming a semiconductor layer.

[0023]

According to the above-described means, it is not necessary to form a p-type layer immediately below the insulating film while preventing the formation of the parasitic MISFET and a decrease in the breakdown voltage, so that the number of steps can be reduced.

[0024]

Embodiments of the present invention will be described below. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

(Embodiment 1) FIG. 7 is an equivalent circuit diagram of a semiconductor device according to an embodiment of the present invention. FIG. 8 shows a chip plane layout. FIG. 9 shows a portion indicated by broken lines in FIG. FIG. 10 shows a longitudinal section taken along line aa in FIG. 8, FIG. 11 shows a longitudinal section taken along line bb in FIG. 8, and FIG. 9 shows a vertical section taken along the line cc in FIG. In FIG. 9, a metal wiring layer serving as a source electrode or a gate pad is omitted to facilitate understanding.

As is apparent from FIG. 7, the semiconductor device of this embodiment has a diode mounted as a protection element between the gate and the source of the n-channel power MISFET. The semiconductor substrate referred to in the present invention is an epitaxial semiconductor layer (n) formed on the main surface of the semiconductor substrate 1 and having the same conductivity type as the substrate.
-A mold layer 2). And the MISFET is n-
Formed on the mold layer 2. These MISFETs are configured by regularly arranging a plurality of cells in a cell region surrounded by a field insulating film 3 provided in a rectangular ring-shaped region having an arcuate corner along the outer periphery of a semiconductor substrate. Have been. The field insulating film 3 is formed so as to be separated into a plurality with a gap in a region where the field insulating film 3 is formed.

The gate 4 of each cell is provided on the main surface of the semiconductor substrate with a gate insulating film 5 interposed therebetween, and adjacent gates 4 are provided continuously, and are connected to the gate wiring 6 at the outer periphery of the cell region. The gate wiring 6 is connected to a gate pad 7 serving as a connection region of the gate 4. In each cell, the n− type layer 2 formed on the n + type semiconductor substrate 1 becomes a drain region, the p type layer 8 formed on the n− type layer 2 becomes a base region where a channel is formed, The n + type layer 9 formed in the type layer 8 is a vertical FET serving as a source. The source electrode 11 provided in the cell region is connected to the n + type layer 9 serving as a source via an interlayer insulating film 10.
The source electrode 11 is electrically connected to the p + -type layer 12 provided in the p-type layer 8 in order to keep the base potential constant, in addition to the n + -type layer 9. Note that a part of the source electrode 11 becomes the source pad 13.

Around the field insulating film 3, a source wiring 14 is provided in a rectangular ring shape.
It is connected to the mold layer 18. The source wiring 14 is formed integrally with the source electrode 11, as is apparent from FIG. Around the source wiring 14 which is the terminal of the chip, a rectangular ring 1 made of a floating p-type diffusion layer is formed.
An FLR in which a plurality of 6s are arranged is provided. This FLR
In this case, as the applied voltage increases, a depletion layer extends from the inner ring 16 to the outer ring 16 before avalanche breakdown occurs, and punches through. Although two rings are shown in the figure, as described above, the required pressure resistance can be obtained by changing the number of stages. For example, if the breakdown voltage is about 60 V or less, the floating ring 16 may not be provided.

In the present embodiment, diodes 17 each serving as a protection element are provided on a plurality of field insulating films 3 formed with a gap in a region where the field insulating film 3 is formed. One end of each diode 17 is electrically connected to the gate line 6 and the other end is electrically connected to the source line 14. The diode 17 is formed by alternately arranging n + -type layers 17a and p-type layers 17b using, for example, polycrystalline silicon. In the illustrated example, four stages of pn junctions are made bidirectionally, but a desired breakdown voltage can be obtained by changing the number of stages. Further, in this embodiment, as shown in FIG.
Diodes 17 are arranged on all the field insulating films 3 formed in the region where the field insulating film 3 is formed, but the number of diodes 17 may be changed as needed.

In this embodiment, as shown in FIG. 12, a p-type semiconductor layer 18 is formed on the main surface of the semiconductor substrate located in the gap of the field insulating film 3 so as to have substantially the same diffusion as the p-type layer 8 in the cell region. Formed at a depth, and the lower part of the field insulating film is n
Although the p-type well layer 15 is not provided under the field insulating film 3 on which the diode 17 is provided, the p-type layer 18
Are arranged at an interval L which is approximately equal to or less than the interval of the p-type layer 8 in the cell region, so that the breakdown voltage is not reduced, and no parasitic MISFET is formed in the diode 17. Since the breakdown voltage of the p-type layer 18 becomes higher as the distance L becomes narrower, it is desirable to form the distance L narrower. Therefore, the p-type layer 18 is extended below the field insulating film 3 by lateral diffusion. It is. Ideally, it is desirable that the p-type layers 18 be connected to each other by lateral diffusion below the field insulating film 3.

Subsequently, a method of manufacturing the above-described semiconductor device will be described for each step with reference to FIGS. In each figure, the FLR part is on the left, the diode part is in the center, and the MI is on the right.
The SFET section is shown. First, an n− type layer 2 is formed by epitaxial growth on an n + semiconductor substrate 1 made of single crystal silicon into which arsenic has been introduced. And
A silicon oxide film is formed on the entire surface of the n − -type layer 2 by, for example, thermal oxidation, and the silicon oxide film is patterned into the field insulating film 3 by etching removal using a photolithographic mask. This state is shown in FIG.

Next, the gate insulating film 5 is formed by, for example, thermal oxidation.
Is formed, and a polycrystalline silicon film 17 'to be the gate 4 or the diode 17 is formed on the entire surface of the main surface of the semiconductor substrate by CVD (C
Chemical Vapor Deposition). Phosphorus is introduced into the region to be the gate 4 and boron is introduced into the region to be the diode. This state is shown in FIG.

Next, the gate 4 and the diode 17 are formed by patterning the polycrystalline silicon film 17 'by etching removal using a photolithographic mask to form the gate 16 and the p serving as a channel of the MISFET.
A p-type layer 18 serving as a diffusion layer adjacent to both sides of the mold layer 8 or the diode is selectively formed simultaneously by ion implantation. This state is shown in FIG. If the p-type layer 17b of the diode is formed by this ion implantation step, it is possible to omit the step of introducing boron into the region to be the diode described above.

Next, the n + type layer 9 serving as the source of the MISFET and the n + type layer 17a of the diode are simultaneously formed by ion implantation using a photolithographic mask. FIG. 16 shows this state.

Next, a p + -type layer 12 for reducing the connection resistance to the p-type layer 8 is formed by ion implantation using a photolithographic mask. For example, a PSG (Phosph) is formed as an interlayer insulating film 10 on the entire surface of the semiconductor substrate main surface.
orus Silicate Glass) film is deposited by CVD and S
After the application of the OG (Spin On Glass) film, an opening for exposing the connection region is provided. This state is shown in FIG.

Next, a conductive film (metal film) made of, for example, silicon-containing aluminum is formed on the entire surface of the main surface of the semiconductor substrate including the inside of the opening, and is patterned by etching removal using a photolithographic mask. Gate pad 7, source electrode 11, and source line 1
After forming a protective insulating film 20 on the entire main surface of the semiconductor substrate, an opening for exposing the gate pad 7 and the source pad 13 is formed. Also, a grinding process is performed on the back surface of the n + type semiconductor substrate 1, and a drain electrode 19 in which nickel, titanium, nickel, and silver are sequentially laminated is formed on the back surface by, for example, vapor deposition, and the state shown in FIG. 18 is obtained.

As described above, in the present invention, since the p-type layer 18 is formed after the formation of the field insulating film, the p-type layer 18 can be formed by using another element formation process, so that the number of steps can be reduced. Is possible.

(Embodiment 2) FIG. 19 is an equivalent circuit diagram of a semiconductor device according to another embodiment of the present invention, FIG. 20 shows a chip plane layout, and FIG. 21 shows a portion shown by broken lines in FIG. FIG. 21 is an enlarged view of aa in FIG.
FIG. 22 shows a vertical section taken along the line, and FIG.
It shows a longitudinal section along the line. In FIG. 21,
To facilitate understanding, a metal wiring layer serving as a source electrode or a gate pad is omitted.

As apparent from FIG. 19, the semiconductor device according to the present embodiment has a gate and an n-channel power MISFET.
A resistor is mounted between the gate pads as a protection element.
The MISFET is formed on an n + type semiconductor substrate 1 made of, for example, single crystal silicon, and on a semiconductor substrate on which an n− type layer 2 is formed by, for example, epitaxial growth. These MISFETs are configured by regularly arranging a plurality of cells in a cell region surrounded by a field insulating film 3 provided in a rectangular ring-shaped region having an arcuate corner along the outer periphery of a semiconductor substrate. Have been. The field insulating film 3 is formed so as to be separated into a plurality with a gap in a region where the field insulating film 3 is formed.

The gate 4 of each cell is provided on the main surface of the semiconductor substrate via a gate insulating film 5, adjacent gates 4 are continuously provided, and connected to the gate wiring 6 at the outer peripheral portion of the cell region. In each cell, the n− type layer 2 formed on the n + type semiconductor substrate 1 becomes a drain region, the p type layer 8 formed on the n− type layer 2 becomes a base region where a channel is formed, The n + type layer 9 formed in the type layer 8 is a vertical FET serving as a source. N + type layer 9 serving as a source
Is connected to a source electrode 11 provided in the cell region via an interlayer insulating film 10. The source electrode 11 has n
In addition to the + -type layer 9, it is also electrically connected to a p + -type layer 12 provided in the p-type layer 8 in order to keep the base potential constant. Note that a part of the source electrode 11 is
It becomes 3.

Around the field insulating film 3, a source wiring 14 is provided in a rectangular ring shape.
It is connected to the mold layer 18. The source wiring 14 is shown in FIG.
As is apparent from FIG.

An FLR in which a plurality of rectangular annular rings 16 each composed of a floating p-type diffusion layer are provided around the source wiring 14 serving as a terminal of the chip. In this FLR, as the applied voltage increases, the inner ring 16 moves to the outer ring 1 before avalanche breakdown occurs.
6, a depletion layer extends to punch through. Although two rings are shown in the figure, as described above, the required pressure resistance can be obtained by changing the number of stages. For example, if the breakdown voltage is about 60 V or less, the floating ring 16 may not be provided.

In this embodiment, a resistor 20 serving as a protection element is provided on a plurality of field insulating films 3 formed with a gap in a region where the field insulating film 3 is formed. One end of 20 is electrically connected to the gate wiring 6, and the other end is electrically connected to the gate pad 7. Resistance 2
0 is formed by using, for example, polycrystalline silicon into which a p-type impurity is introduced and meandering it.

In this embodiment, the p-type semiconductor layer 1 is formed on the main surface of the semiconductor substrate located in the gap of the field insulating film 3.
8 is formed with a diffusion depth substantially equal to that of the p-type layer 8 in the cell region, the lower part of the field insulating film is the n − type layer 2, and the p-type
Although no p-type well layer is provided, the p-type layer 18
Are arranged at an interval L which is approximately equal to or less than the interval, the breakdown voltage is not reduced.

Since the breakdown voltage of the p-type layer 18 becomes higher as the interval L becomes narrower, it is desirable to form the interval L narrower. Therefore, the semiconductor layer 18 extends under the field insulating film 3 by lateral diffusion. I have been. Ideally, it is desirable that the p-type layers 18 be connected to each other by lateral diffusion below the field insulating film 3. Further, in the present embodiment, the resistors 20 are arranged in a meandering manner. However, the present invention can be practiced even if they are arranged in a straight line, and a configuration in which a plurality of resistors are formed and connected in parallel or in series may be adopted.

Subsequently, a method of manufacturing the above-described semiconductor device will be described for each process. The method of manufacturing the semiconductor device of the present embodiment is substantially the same as that of the above-described embodiment except for the resistance forming step. First, an n− type layer 2 is formed by epitaxial growth on an n + semiconductor substrate 1 made of single crystal silicon into which arsenic has been introduced. Then, a silicon oxide film is formed on the entire surface of the n − type layer 2 by, for example, thermal oxidation, and the silicon oxide film is patterned into the field insulating film 3 by etching removal using a photolithographic mask.

Next, the gate insulating film 5 is formed by, for example, thermal oxidation.
Is formed, and a polycrystalline silicon film to be the gate 4 or the resistor 21 is formed on the entire surface of the main surface of the semiconductor substrate by CVD (Chemical Vapor
r Deposition). Phosphorus is introduced into the region that becomes the gate 4 and boron is introduced into the region that becomes the resistor 21.

Next, the gate 4 and the resistor 21 are formed by patterning the polycrystalline silicon film 17 ′ by etching removal using a photolithographic mask to form the ring 16 or the p-type layer 8 serving as a channel of the MISFET.
Alternatively, the p-type layer 18 serving as a diffusion layer adjacent to both sides of the resistor is selectively formed by ion implantation. If impurities are introduced into the resistor 21 by this ion implantation step,
It is also possible to omit the step of introducing boron into the region to be the resistor 21 described above.

Next, an n + type layer 9 serving as a source of the MISFET is formed by ion implantation using a photolithographic mask.

Next, a p + -type layer 12 for reducing the connection resistance to the p-type layer 8 is formed by ion implantation using a photolithographic mask. For example, a PSG (Phosph) is formed as an interlayer insulating film 10 on the entire surface of the semiconductor substrate main surface.
orus Silicate Glass) film is deposited by CVD and S
After the application of the OG (Spin On Glass) film, an opening for exposing the connection region is provided.

Next, a conductive film (metal film) made of, for example, aluminum containing silicon is formed on the entire surface of the main surface of the semiconductor substrate including the inside of the opening, and is patterned by etching removal using a photolithographic mask. Gate pad 7, source electrode 11, and source line 1
After forming a protective insulating film 18 on the entire main surface of the semiconductor substrate, an opening for exposing the gate pad 7 and the source pad 13 is formed. Further, the back surface of the n + type semiconductor substrate 1 is subjected to a grinding process, and the drain electrode 19 in which nickel, titanium, nickel, and silver are sequentially laminated is formed on the back surface by, for example, vapor deposition.

As the protection element of the semiconductor device, the resistor of the present embodiment and the diode of the above-described embodiment can be used together. FIG. 23 is an equivalent circuit diagram of a semiconductor device of such an example, FIG. 24 shows a chip plane layout, and FIG. 25 is an enlarged view of a portion shown by broken lines in FIG. In FIG. 25, a metal wiring layer serving as a source electrode or a gate pad is omitted to facilitate understanding.

As is apparent from FIG. 23, the semiconductor device according to the present embodiment has a gate and an n-channel power MISFET.
A diode is mounted as a protection element between the sources, and a resistor is mounted between the gate and the gate pad as a protection element.

In the present embodiment, diodes 1 serving as protection elements are provided on a plurality of field insulating films 3 formed with a gap in a region where field insulating film 3 is formed.
7 and a resistor 21 serving as a protection element are provided. One end of the diode 17 is electrically connected to the gate wire 6, the other end is electrically connected to the source wire 14, and one end of the resistor 21 is connected to the gate wire 6 and the other end. Are electrically connected to the gate pad 7.

The diode 17 is formed by alternately arranging n + -type layers 17a and p-type layers 17b using, for example, polycrystalline silicon. In the illustrated example, four stages of pn junctions are made bidirectionally, but a desired breakdown voltage can be obtained by changing the number of stages. In this embodiment, as shown in FIG. 24, the diodes 17 are arranged on all the field insulating films 3 formed in the formation region of the field insulating film 3 surrounding the gate wiring 6, but, of course, as necessary, You can change the number. Resistance 2
1 is formed by using, for example, polycrystalline silicon into which p-type impurities are introduced, and arranging it in a meandering manner.

In this embodiment, the p-type semiconductor layer 1 is formed on the main surface of the semiconductor substrate located in the gap of the field insulating film 3.
8 is formed with a diffusion depth substantially equal to that of the p-type layer 8 in the cell region, the lower part of the field insulating film is the n − type layer 2, and the diode 17 or the field insulating film 3 on which the resistor 21 is provided. Although no p-type well layer is provided below, the p + -type layer 12 is arranged in the gap between the field insulating films 3 at an interval L which is equal to or less than the interval between the p-type layers 8 in the cell region. Therefore, the breakdown voltage is not reduced, and no parasitic MISFET is formed in the diode 17.

Since the breakdown voltage of the p-type layer 18 becomes higher as the distance L becomes smaller, it is desirable to form the distance L smaller. Therefore, the p-type layer 18 is formed under the field insulating film 3 by lateral diffusion. It has been extended. Ideally, it is desirable that the p-type layers 18 be connected to each other by lateral diffusion below the field insulating film 3. Note that the above-described method for manufacturing a semiconductor device having a diode and a resistor can be applied to a method for manufacturing such a semiconductor device. As described above, in the present invention, since the p-type layer 18 is formed after the formation of the field insulating film, the p-type layer 18 can be formed by using another element formation process, and thus the number of steps can be reduced. is there.

As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention. For example, the present invention provides an IGBT (Integrated Gate) other than a semiconductor device provided with a power MISFET.
The present invention is also applicable to a semiconductor device provided with a bipolar transistor or the like.

[0059]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, there is an effect that a semiconductor layer for preventing a decrease in breakdown voltage and preventing a parasitic FET can be formed after forming a field insulating film. (2) According to the present invention, the effect (1) has an effect that the semiconductor layer can be formed by using another element formation process. (3) According to the present invention, the effect (2) has an effect that the number of steps can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view showing a conventional power MISFET.

FIG. 2 is an enlarged plan view of a main part of a portion shown by broken lines in FIG.

FIG. 3 is a longitudinal sectional view taken along the line aa in FIG.

FIG. 4 is a partial longitudinal sectional view for explaining a relationship between a withstand voltage and a depletion layer.

FIG. 5 is a partial longitudinal sectional view for explaining a relationship between a withstand voltage and a depletion layer.

FIG. 6 is a graph showing the relationship between the spacing between semiconductor layers and the breakdown voltage.

FIG. 7 is an equivalent circuit diagram of the semiconductor device according to one embodiment of the present invention;

FIG. 8 is a plan view showing the semiconductor device of the present embodiment.

FIG. 9 is an enlarged plan view of a portion indicated by broken lines in FIG. 8;

FIG. 10 is a longitudinal sectional view taken along the line aa in FIG.

FIG. 11 is a longitudinal sectional view taken along the line bb in FIG. 8;

FIG. 12 is a longitudinal sectional view taken along the line cc in FIG. 8;

FIG. 13 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 14 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 15 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 16 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 17 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 18 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 19 is an equivalent circuit diagram of a semiconductor device according to another embodiment of the present invention.

FIG. 20 is a plan view showing the semiconductor device of the present embodiment.

FIG. 21 is an enlarged plan view of a main part of a portion shown by broken lines in FIG. 20;

FIG. 22 is a longitudinal sectional view taken along the line cc in FIG. 20;

FIG. 23 is an equivalent circuit diagram of a semiconductor device which is a modification of another embodiment of the present invention.

FIG. 24 is a plan view showing the semiconductor device of the present embodiment.

FIG. 25 is an enlarged plan view of a main part of a portion shown by broken lines in FIG. 24;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor base, 2 ... n-type layer (drain region), 3 ...
Field insulating film, 4 gate, 5 gate insulating film, 6
... gate wiring, 7 ... gate pad, 8 ... p-type layer (channel formation region), 9 ... n + type layer (source region), 10 ... interlayer insulating film, 11 ... source electrode, 12 ... p + type layer, 13 ...
Source pad, 14 ... source wiring, 15 ... p-type layer (well layer), 16 ... ring, 17 ... diode, 17a ... n
+ Type layer (diode region), 17b ... p-type layer (diode region), 18 ... p-type layer, 19 ... drain electrode, 20 ...
Protective insulating film.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Nobuo Machida 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. No. 15 Inside Hitsutobu Semiconductor Co., Ltd. (72) Inventor Takamitsu Kanazawa 15th Asahidai, Moroyama-cho, Iruma-gun, Saitama Prefecture F-term in Hitsutobu Semiconductor Co., Ltd. AR09 BH01 BH02 BH04 BH13 BH18 CA02 CD04 EZ20

Claims (10)

[Claims] 1. A semiconductor device in which a semiconductor element is formed on an insulating film formed in a predetermined region of a main surface of a semiconductor substrate, wherein the insulating film is formed with a gap in the region and is located in the gap. A semiconductor device, wherein a semiconductor layer of a conductivity type opposite to that of the semiconductor substrate main surface is formed on the semiconductor substrate main surface. 2. A power MISFE in a cell region defined by an insulating film formed in a predetermined region of a main surface of a semiconductor substrate.
In a semiconductor device in which T is formed and a semiconductor element is formed on the insulating film, the insulating film is formed with a gap in the region, and a semiconductor substrate main surface located in the gap is provided on the semiconductor substrate main surface. A semiconductor layer having the opposite conductivity type to the semiconductor layer, and the semiconductor element is formed on an insulating film located between the gaps. 3. The semiconductor device according to claim 1, wherein the semiconductor element formed on the insulating film is at least one of a diode or a resistor serving as a protection element.
3. The semiconductor device according to claim 1. 4. The semiconductor device according to claim 2, wherein a diffusion depth of a semiconductor layer located in a gap between the insulating films is equal to a diffusion depth of a channel formation region of the power MISFET. . 5. The semiconductor device according to claim 1, wherein the semiconductor layer located in the gap between the insulating films is laterally diffused into the main surface of the semiconductor substrate under the adjacent insulating film. 13. The semiconductor device according to item 9. 6. A method of manufacturing a semiconductor device in which a semiconductor element is formed on an insulating film formed in a predetermined region of a main surface of a semiconductor substrate, wherein the insulating film is formed on the main surface of the semiconductor substrate by forming a gap in the region. And forming a semiconductor layer of a conductivity type opposite to the semiconductor substrate main surface on the semiconductor substrate main surface located in the gap. 7. A power MISFE is provided in a cell region defined by an insulating film formed in a predetermined region of a main surface of a semiconductor substrate.
A method for manufacturing a semiconductor device in which T is formed and a semiconductor element is formed on the insulating film, wherein a step of forming the insulating film on the main surface of the semiconductor substrate with a gap in the region; Forming a semiconductor layer of a conductivity type opposite to the semiconductor substrate main surface on the semiconductor substrate main surface located on the substrate, and forming the semiconductor element on an insulating film located between the gaps. Manufacturing method of a semiconductor device. 8. The method for manufacturing a semiconductor device according to claim 6, wherein the semiconductor element formed on the insulating film is at least one of a diode or a resistor serving as a protection element. . 9. The semiconductor device according to claim 7, wherein a semiconductor layer located in a gap between the insulating films and a channel formation region of the power MISFET are formed in the same step.
13. The method for manufacturing a semiconductor device according to item 5. 10. The semiconductor device according to claim 6, wherein the semiconductor layer located in the gap between the insulating films extends to the main surface of the semiconductor substrate under the adjacent insulating film by lateral diffusion. 9. The method for manufacturing a semiconductor device according to claim 1.