JP2000305917A - Multi-processor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To properly process a time series processing and a non-time series processing with high efficiency with simple structure regarding a multi-processor system. SOLUTION: This multi-processor system is constituted so as to connect plural processors with plural peripheral circuit parts via a bus SB and to perform distributed processing of interruption requests from plural peripheral circuit parts by plural processors. In this case, the system is provided with plural processors (a) to (c) to be specified by a master (a) and one or two or more non-masters (b), (c) plural peripheral circuit parts 1 to n to output processor instruction information RID to represent that the master (=1) or infinite (=zero) simultaneously with generation of the interruption requests IRQ and an allocation control part 40 to allocate the interruption requests from each of the peripheral circuit parts 1 to n to processors of the master (a) or one or two or more infinite (a) to (c) according to the processor instruction information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly to a multiprocessor system in which a plurality of processors and a plurality of peripheral circuits are connected via a common bus, and an interrupt request from the plurality of peripheral circuits is provided. The present invention relates to a multiprocessor system in which a plurality of processors share a processing request.

In this type of system, a plurality of processors efficiently process each interrupt request from a plurality of peripheral circuit units under load distribution control, and depending on the interrupt request (the type of processing), May need to be processed in chronological order.

[0003]

2. Description of the Related Art For example, a centralized monitoring unit in a data transmission system or the like collects events (changes in monitoring data, etc.) that occur irregularly in a large number of main signal circuit units, and collects these events in a multiprocessor unit at high speed and in parallel. Analysis processing,
Notification is performed to a maintenance monitoring console or the like.

Conventionally, a vacant processor accepts an interrupt request (event processing) in a cyclical manner by priority arbitration control by a round robin method or the like provided in a multiprocessor unit, thereby equalizing and processing each processor load. Was being accelerated.

[0005]

However, the order of events input to the multiprocessor unit and the order of output of the processing results are reversed depending on the complexity of the analysis contents of the event or the load state of the processor receiving the event. A case (a so-called “first-in first-out phenomenon”) may occur.

For example, when a "failure occurrence" is notified from a certain monitored device, and "failure recovery" is notified shortly thereafter, if the "failure occurrence" is processed by the processor a in a high load state, and Assuming that the processor b in the low load state processes the “failure recovery”, the processor b
Completes the processing before the processor a, and notifies the result to the maintenance monitoring console in this order. When viewed from the maintenance monitoring console side, the status is reported in the order of “failure recovery” → “failure occurrence”, and the maintenance person erroneously recognizes the system status.

[0007] In this regard, a method of adding a weight (priority) or a time stamp to the processing request data can be considered. However, the weight and the time stamp are added to the interrupt or the processing result. The control to be reflected becomes complicated.

The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to efficiently and appropriately process time-series processing and non-time-series processing with a simple configuration. It is to provide a multiprocessor system.

[0009]

The above-mentioned problem is solved, for example, by referring to FIG.
Is solved. That is, in the multiprocessor system of the present invention (1), the plurality of processors and the plurality of peripheral circuit units are connected via the bus SB, and the plurality of processors share an interrupt request from the plurality of peripheral circuit units. Processor a specified by a master and one or more non-masters
To c, a plurality of peripheral circuit units 1 to n for outputting processor instruction information RID indicating master (= 1) or unspecified (= 0) together with generation of an interrupt request, and interrupt requests from each peripheral circuit unit And an allocation control unit 40 for allocating to the master a or one or more unspecified processors a to c in accordance with the processor instruction information.

In the present invention (1), each peripheral circuit unit 1
To n are processor instruction information RID1 to n (for example, R
(ID1 to n = 1/0) are output, the processing requiring time-series processing is processed in the time series by the master processor a, and the processing not requiring the time-series processing is free of any one. It is possible to easily specify that specific processors a to c perform processing quickly. Alternatively, the processing A requiring special processing is performed by the master processor a, and other general processing is performed by any of the unspecified unspecified processors a to c.
Can be easily specified.

The allocation control unit 40 includes the peripheral circuit units 1 to
The load distribution of the processors a to c can be efficiently performed by allocating the interrupt requests IRQ1 to n from n to the master a or one or more unspecified processors a to c according to the processor instruction information RID1 to n. Well done.

In the multiprocessor system according to the present invention (2), the plurality of processors and the plurality of peripheral circuit units are connected via a bus, and the plurality of processors share an interrupt request from the plurality of peripheral circuit units. In a multiprocessor system that performs processing, a unique identification ID (for example, ID = a
To c) and a plurality of peripherals that output processor identification information RID indicating a unique identification ID (= a to c) or unspecified (= 0) when an interrupt request is generated. Circuit units 1 to n, and an interrupt request from each peripheral circuit unit in accordance with its processor instruction information.
and an allocation control unit 40 for allocating to one or more unspecified processors a to c.

In the present invention (2), each of the peripheral circuit units generates a unique identification ID = a (or b,
c) or processor instruction information RI representing unspecified (= 0)
Depending on the configuration for outputting D, the processing requiring time-series processing is processed in the desired processor a (or b, c) in the respective time series, and the processing not requiring time-series processing is free. It is possible to easily specify that the processing is promptly performed by the unspecified processors a to c. Alternatively, a specific type of process A is processed by the processor a, another specific type of process B is processed by the processor b, and another type of process C is performed.
Can be easily specified to be processed by the processor c.

Further, the allocation control unit 40 responds to the interrupt request from each peripheral circuit unit with a unique identification IDa (or b, c) or a free 1 or 2 according to the processor instruction information RID.
With the above configuration of allocating to the unspecified processors a to c, the loads of the processors a to c are efficiently distributed.

Preferably, in the present invention (3), in the present invention (1) or (2), a plurality of peripheral circuit units 1 to n are interposed between the allocation control unit 40 and a plurality of peripheral circuit units. The arbiter 21 arbitrates two or more competing interrupt requests IRQ from the unit and receives the input to the allocation control unit in time series.

Accordingly, each of the peripheral circuits 1 to n can efficiently process each interrupt request generated at an arbitrary timing. The arbitration includes priority arbitration based on a specific priority or a round robin method, and arbitration based on scanning or polling.

Preferably, in the present invention (4), in the above-mentioned inventions (1) to (3), two or more competing interrupt acceptance requests ARQ from a plurality of processors a to c are provided.
And a permission arbiter 11 for issuing an acceptance permission AAK to any one of the processors.

Therefore, each of the interrupt requests simultaneously allocated to two or more unspecified processors a to c by the allocation control unit 40 can be arbitrated (preferably under load distribution control) to any one of the processors efficiently. Assigned. In addition,
This arbitration includes priority arbitration based on a specific priority or a round robin method, and arbitration based on scanning or polling.

Preferably, in the present invention (5), in the present invention (1), the master processor is determined by an external setting or an autonomous arbitration operation of a plurality of processors. Therefore, a desired processor can be externally set as the master processor. Alternatively, at the time of turning on the power to the multiprocessor system or at the time of resetting (restarting), a normally normal (no fault) processor that can participate in the autonomous arbitration operation is automatically determined as the master processor.

Preferably, in the present invention (6), in the above-mentioned present invention (1), the allocation control unit 40, when the master processor is abnormal, issues an interrupt request to the master processor for a predetermined time. Transfer to master processor. Therefore, the interrupt request can be effectively processed even when the master processor fails.

Preferably, in the present invention (7), in the above-mentioned present invention (2), the allocation control unit, when the specific processor is abnormal, sends an interrupt request to the specific processor to another processor. Transfer to the specified processor.
Therefore, the interrupt request can be effectively processed even when the designated processor fails.

[0022]

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the same reference numerals indicate the same or corresponding parts throughout the drawings.

FIG. 2 is a diagram showing the configuration of the multiprocessor system according to the first embodiment, showing a case where an interrupt request from each peripheral circuit is allocated to a master or an unspecified processor according to the processor instruction information RID. ing.

In the figure, reference numeral 10 denotes a multiprocessor unit,
PRa to PRc are processors constituting a multiprocessor unit, SB is a system bus (S bus), 11 is a priority arbitrator for an interrupt acceptance request ARQ from the processors PRa to PRc, and issues an acceptance permission AAK to any one of the processors. Permission arbiter (IABT), 12 is a processor PRa
, A bus arbiter (BABT) 13 for arbitrating the bus use request BRQ from PRc and issuing a bus right grant BAK to one of the processors, and a system bus arbiter (SA) 13 integrating the permission arbiter 11 and the bus arbiter 12.
BT) and 20 are peripheral circuit units that request the multiprocessor unit 10 to perform processing, and SPR1 to SPRn are processing units that constitute the peripheral circuit unit.
A main signal processing unit for performing the main signal processing of Sn;
A reception arbiter (PR) that prioritizes each processing (interruption) request from PR1 to SPRn by, for example, a round robin method and receives an input to the allocation control unit 40 described later in a time series
U), 30 are the system common memory (MEMo), 40
Is an interrupt decoder (IDEC) that converts interrupt requests from SPR1 to SPRn into interrupt requests to master or non-master processors PRa to PRc according to the processor instruction information RID. Note that the interrupt decoder 40 corresponds to the allocation control unit 40 in FIG.

In the processor PRa, the CPUa is connected to a RAM, a ROM, an EEPROM via a host bus HBa.
Connected to a main memory MEMa comprising
a can directly access the main memory MEMa via the host bus HBa. The host bus HBa is connected to the S bus via a host-system bus bridge HSBa, and the CPUa can directly access the S bus (that is, the main signal processing units SPR1 to SPRn, MEMo, etc.) via HSBa. .

For example, when the CPUa accesses the MEMo address space, the host-system bus bridge H
The SBa detects that it is an external address, and outputs a bus right request BRQa = 1. The bus arbiter 12 receiving this performs arbitration with another bus right request if necessary, for example, in a round-robin manner, and when accepting BRQa = 1, returns the bus permission BAKa = 1. Thereby, the CPUa is connected to the S bus and can directly access MEMo. Similarly, the CPUa uses the I / O command or the like to execute the main signal processing units SPR1 to SPRn.
Can be accessed directly. Processor PRb, PRc
The same applies to. CPUa to CPUc are M
They can communicate with each other via reading / writing messages to / from EMo.

The main signal processing unit SPR1 may be realized by a normal hardware configuration. In this example, however, a CPU (not shown) for processing the main signal SS1 is provided inside. In any case, such a main signal processing unit SPR
When an event (a change in monitoring data or the like) occurs inside the main signal processing unit 1, the main signal processing unit SPR1 sets the interrupt request IRQ1 = 1
And processor instruction information RID1 = 1 (master) or RID1 depending on whether this interrupt request is to be processed in a time series (sequential).
= 0 (unspecified) is determined. Main signal processing units SPR2 to SPR
The same applies to PRn.

On the other hand, in the multiprocessor unit 10,
Which one becomes the master processor may be set in advance from outside, but in this example, it is automatically determined by the autonomous arbitration operation of PRa to PRc. That is, when the power of the present system is turned on or the present system is reset (restarted), the CPUa to CPUc substantially simultaneously execute the bus right request BR.
It is assumed that Qa to BRQc = 1. Then, for example, the CPUa that first acquires the bus right reads out the data at the specific address of the MEMo (RAM) and stores the data at the specific address of the other CPU.
When D has not been written, its own identification ID = a is written, thus declaring that it is the master CPU. On the other hand, other CPUs that have acquired the bus right after the second
The CPU b and the CPU c recognize that they are not the master CPU by writing the identification ID = a of the other CPU at the specific address of MEMo. In this case, the CPUa has PIDa = 1 (master) as the processor state identifier.
Are output, and the other CPUs b and c both output PIDb = P
It outputs IDc = 0 (non-master).

With this configuration, first, the main signal processing unit SPR
The operation when 1 generates an interrupt request IRQ1 by designating the processor instruction RID1 = 1 (master) will be specifically described. That is, when an event occurs internally, the main signal processing unit SPR1 outputs an interrupt request IRQ1 = 1. The reception arbiter 21 receiving the request performs priority arbitration with another interrupt request if necessary, and returns an interrupt request enable RQE1 = 1 when accepting IRQ1 = 1. Upon receiving RQE1 = 1, the main signal processing unit SPR1 outputs a processor instruction RID1 = 1 (master), and this signal is applied to an instruction bus IB consisting of 1 bit. on the other hand,
Reception arbiter 21 outputs gate signal RQE / = 1 at the same timing as RQE1 = 1.

In the interrupt decoder 40, since the processor designation IB from the SPR1 is IB = 1 (master) and the processor state PIDa of the CPUa is 1 (master), at the timing of RQE / = 1, the AND gate circuit A2 Only is energized, and the interrupt request signal IRQa = 1. That is, this interrupt request is assigned only to the master CPUa.

When the master CPUa receives IRQa = 1, it issues an acceptance permission request ARQa = 1 to the permission arbiter 11.
Is output. Upon receiving this, the permission arbiter 11 arbitrates with another reception permission request if necessary, and
When a = 1 is accepted, the acceptance permission AAKa = 1 is returned. Also, the permission arbiter 11 outputs an S bus request instruction signal AAK / (= corresponding to BRQa) at the same timing as AAKa = 1, which is preferentially received by the bus arbiter 12. As a result, the bus arbiter 12 temporarily outputs the bus permission BAKa = 1, whereby the master CPUa and the S bus are connected. The CPUa outputs the interruption permission IAKa = 1 when the reception permission AAKa = 1 and the bus permission BAKa = 1 are received. Interrupt permission I
AKa = 1 is sent to the main signal processing units SPR1 to SPRn via a 1-bit permission bus AB.

On the other hand, the main signal processing unit SPR1 outputs interrupt vector information to the address / data terminal A / D1 by receiving the interrupt request enable RQE1 = 1 and the interrupt enable IAK1 = 1. The interrupt vector information includes an identification ID of the main signal processing unit SPR1 (that is, a processing request source), type information of an interrupt process, and the like.

On the other hand, the master CPUa acquires the interrupt vector information from the SPR1 via the S bus, and sets IAKa = 0 (deactivated) at the next clock timing. On the other hand, in the main signal processing unit SPR1, the interrupt permission IAKa =
As a result, the interrupt request IRQ1 = 0 is set at the clock timing. With this, the reception arbiter 21
Sets the interrupt request enable RQE1 = 0, whereby the output of the address / data terminal A / D1 is deactivated.

After that, the master CPUa sets the main signal processing unit S
Jump to the designated interrupt vector of PR1 and execute the corresponding interrupt processing. At this time, if necessary, the main signal processing unit SPR1 of the processing request source is connected via the S bus to exchange processing data and processing result data. The final processing result data is also written in the common memory 30, and this data is collected and processed by a system monitoring monitor (not shown).

When the master CPUa is executing the previous interrupt process, the CPUa does not accept a new interrupt request, for example, by executing an interrupt disable command issued internally by the CPUa. In this case, for example, the main signal processing unit SPR1 newly allocated to the CPUa
, The new interrupt request IRQa = 1 is ignored at the entrance of the CPUa, so that the acceptance permission request ARQa = 0 remains.

On the other hand, in the reception arbiter 21 in this case,
Despite setting interrupt request enable RQE1 = 1,
After a predetermined number of clock cycles, the main signal processing unit S
Since the interrupt request IRQ1 of PR1 does not become 0,
The interrupt request enable RQE1 is forcibly set to "0".
As a result, the main signal processing unit SPR1 in this case stands by for processing while keeping the interrupt request IRQ1 = 1, and waits for the next time the interrupt request enable RQE1 = 1. Thus, the time-series interrupt requests generated in the main signal processing unit SPR1 are processed in time series by the master CPUa. On the other hand, the service of the reception arbiter 21 immediately shifts to arbitration of another SPR.

Next, the main signal processing unit SPR2 designates the processor instruction RID2 = 0 (unspecified) and specifies the interrupt request IRQ2.
The operation in the case of occurrence of will be described specifically. That is, when an event occurs, the main signal processing unit SPR2 outputs an interrupt request IRQ2 = 1. The reception arbiter 21 receiving the request performs arbitration with another interrupt request if necessary, and returns an interrupt request enable RQE2 = 1 when accepting IRQ2 = 1. The main signal processing unit SPR2 receives the RQE2 = 1,
2 = 0 (unspecified) is output, and the signal is applied to the designated bus IB. On the other hand, reception arbiter 21 outputs gate signal RQE / = 1 at the same timing as RQE2 = 1.

In the interrupt decoder 40, since IB = 0, the output of the inverter circuit I1 becomes 1, and the signal RQE / = 1
, The AND gate circuits A1, A3, and A5 are energized all at once, whereby the interrupt requests IRQa to IRQ
c = 1. That is, an interrupt request by an unspecified processor instruction is allocated by the interrupt decoder 40 to all CPUs including the master CPUa.

In the CPUa-CPUc, IRQa-
Upon receiving IRQc = 1, it outputs acceptance permission requests ARQa to ARQc = 1 to permission arbiter 11. In addition,
ARQa = 1 is not output when the master CPUa is executing the interrupt processing of the main signal processing unit SPR1 as described above. In this way, processing concentration on the master CPUa is avoided. On the other hand, the permission arbiter 11 transmits the reception permission requests ARQa to ARQ.
While performing priority arbitration by the round robin method or the like during Qc = 1, for example, when accepting the acceptance permission request ARQb = 1, the reception permission AAKb = 1 is returned. By the way,
Under the round robin method, the last acceptance permission AAKa =
The priority order of the CPUa given 1 is the lowest, and the acceptance permission AAKb = 1 is given to the CPUb this time with priority. In this way, the load distribution among the unspecified CPUs a to c is equalized.

The permission arbiter 11 receives the permission permission AAK.
At the same timing as b = 1, an S bus request instruction signal AAK
/ (= Corresponding to BRQb), which is preferentially accepted by the bus arbiter 12. As a result, the bus permission BAKb = 1, and the CPUb is connected to the S bus. Then, the CPUb outputs the interrupt permission IAKb = 1 and, in the same manner as above, the interrupt vector information from the main signal processing unit SPR2 via the S bus (that is, the interrupt request source SP).
R2 identification ID, processing type information, etc.). Thus, the processor instruction RI by the main signal processing unit SPR2
The interrupt request IRQ2 = 1 accompanied by D2 = 0 (unspecified) is promptly processed by any of the vacant CPUa, CPUb, or CPUc under the above-described predetermined load distribution control.

FIG. 3 is a timing chart of the interrupt processing according to the embodiment, and shows an example of the timing when the master CPUa accepts the interrupt processing. In the figure, the interrupt request enable RQE1 = 1 for the interrupt request IRQ1 = 1 of the main signal processing unit SPR1 happens to occur in the minimum time MIN (one clock cycle) in this example. Interrupt permission AAKa = for interrupt request IRQa = 1
1 is the same. In general, in the case of an interrupt request of an unspecified instruction, the CPU in a normally idle state has a priority.
AAKa = 1 for Qa = 1 often occurs in the minimum time MIN. Further, the bus permission BAKa = 1 for the signal AAK / (corresponding to AAKa = 1) = 1 always occurs in the minimum time MIN due to priority processing in the bus arbiter 12. Thus, the interrupt request IRQ1 = 1 from the main signal processing unit SPR1 is normally accepted in about four clocks after issuing the interrupt request enable RQE1 = 1. Therefore, when the time exceeds this time, the reception arbiter 21
In order to give priority to a processing request from another main signal processing unit SPR, even if the interrupt request IRQ1 = 1, the allocation service to the SPR1 is temporarily stopped. That is, the interrupt request enable RQE1 = 0.

FIG. 4 is a diagram showing the configuration of a multiprocessor system according to the second embodiment.
This shows a case where the master is automatically transferred to another CPU when a fails. In the figure, reference numeral 50 denotes a processor selection unit (PSEL) that provides another CPUb or CPUc as a temporary master to the system when, for example, the master CPUa fails. For other configurations, see FIG.
It may be the same as that described above.

However, in this case, the CPUa has an abnormality detecting unit (watch dog timer, etc.) inside, and the CPUa
Is abnormal (enters an infinite loop, etc.), the multifunction MFCa = 1 is output. Other CPUb,
The same applies to CPUc. Now, when MFCa = 1 for the master CPUa, the AND gate circuit A11
Is deactivated, and the input of the AND gate circuit A2 is also deactivated. Therefore, the main signal processing unit SPR1
The interrupt request of processor instruction RID1 = 1 (master) does not reach master CPUa.

On the other hand, in the processor selecting section 50, the CP
The output of the OR gate circuit O1 is 1 due to the state PIDa = 1 (master) of Ua, and the output of the AND gate circuit A12 =
It becomes 1. This is input to the OR gate circuit O2, whereby the output of the OR gate circuit O2 = 1. Now, CP
Assuming that Ub is normal, the processor error MFCb =
Since this is 0, the input of the AND gate circuit A13 is energized. Also, the output of the OR gate circuit O2 =
As a result of 1, the output of the AND gate circuit A13 = 1, and thus the interrupt request accompanied by the processor instruction RID1 = 1 (master) from the main signal processing unit SPR1 reaches the substitute master CPUb via the AND gate circuit A4. .

That is, in this case, the master-designated interrupt request from SPR1 is processed in time series by the substitute master CPUb. In SPR1, as long as time-series processing requests are processed in time series, actually, any CPU may be the master. On the other hand, since the alternative master CPUb knows that the processing request source is SPR1 via the S bus,
The interrupt request from SPR1 can be properly processed. Thus, when the master CPUa fails, the CPUb becomes the substitute master, and when the substitute master CPUb fails, the CPUc becomes the substitute master by the same algorithm as described above. In this example, the output of the AND gate circuit A16 is fed back to the input of the OR gate circuit O1.
PU can be an alternative mast.

In the second embodiment, since the master CPUa has a fault, the processor selection unit 50
The other CPUb is automatically set as the substitute master according to the above control, but is not limited to this. For example, when a failure occurs in the master CPUa, an interval between the CPUb and the CPUc (however,
In this case, the CPUa does not participate in the arbitration due to a failure.)
The above-mentioned autonomous master extraction arbitration is performed again, and the CPU
b or CPUc may be the original master.

FIG. 5 is a diagram showing a configuration of a multiprocessor system according to the third embodiment.
... N to the processor instruction information RID
(= 0 to 3), the unique identification ID = 1 (or 2,
3) corresponding processors a to c or unspecified (= 0)
Are assigned to the processors a to c. In the figure, reference numeral 40 denotes an interrupt decoder (IDEC) according to the third embodiment.
It may be the same as that described above.

The main signal processing unit SPR1 receives the interrupt request IRQ1
= 1, and RID1 = "0" when requesting the processing to unspecified processors a to c, and RID1 = when requesting the processing to specific processors a, b or c.
"1", "2" or "3" is output.

In the interrupt decoder 40, the decoder DE
C decodes data "0"-"3" on bus IB and energizes corresponding output terminals 0-3. Therefore, when the processor instruction RID1 = “0” (unspecified), the AND gate circuits A1, A3, and A5 are energized all at once, and any one of the interrupt requests is accepted by the permission arbiter 11. When processor instruction RID1 = "1" (designation of processor a), only AND gate circuit A2 is energized and finally accepted by processor a. The same applies to the case where the processor instruction RID1 = "2" / "3" (processor b / c designation).

FIG. 6 is a diagram showing the configuration of a multiprocessor system according to the fourth embodiment.
The case where the designated destination is automatically transferred to another CPUb, for example, when Ua breaks down is shown. In the figure, 50
Is a processor selection unit (PSE) according to the fourth embodiment.
L). Other configurations may be the same as those described with reference to FIG.

In the figure, the main signal processing unit SPR1 now issues an interrupt request IRQ1 = 1 and a processor instruction RID1.
= "0" (unspecified), the request is AN
D gate circuits A1, A3, A5
At the timing of / = 1, IRQa to IRQc = 1.
In this case, even if the CPUa is abnormal, the interrupt request is finally accepted by the CPUb or the CPUc.

Next, the main signal processing unit SPR1 sends the interrupt request IR
Assuming that processor instruction RID1 = "1" (processor a designation) is output together with Q1 = 1, decoder DEC
The OR gate circuit O1 is energized by the output terminal 1 = 1, and its output = 1. In this state, if the CPUa is normal, the processor failure MFCa = 0 causes AN
The D gate circuit A11 is satisfied, and the interrupt request is allocated to the designated CPUa via the AND gate circuit A2.

However, in this case, if the designated CP
If Ua is faulty, the input to AND gate circuit A11 is deactivated by MFCa = 1, which also deactivates the input to AND gate circuit A2. Therefore, the main signal processing unit S
The interrupt request for processor a from PR1 does not reach CPUa.

On the other hand, inside the processor selecting section 50,
The output of the OR gate circuit O1 = 1 due to the output terminal 1 = 1 of the decoder DEC, and the output of the AND gate circuit A12 due to this and the processor abnormality MFCa = 1 =
1, which is input to the OR gate circuit O2,
The output of the R gate circuit O2 = 1.

Now, assuming that the CPUb is normal, since the processor abnormality MFCb = 0, the input of the AND gate circuit A13 is thereby activated. Further, the output of the OR gate circuit O2 = 1, the output of the AND gate circuit A13 = 1, and thus the main signal processing unit S
The interrupt request with the processor a designation from PR1 is AN
It is allocated to the alternative processor CPUb via the D gate circuit A4. The same applies to a case where another specified CPU has a failure.

In the second / fourth embodiments,
Since the master / designated CPUa is faulty, the master / designated interrupt processing is assigned to another predetermined CPUb, but the present invention is not limited to this. For example, if this interrupt request is
You may comprise so that it may distribute to PUa-CPUc.

Although the above embodiments have been described with reference to specific numerical examples, it goes without saying that the present invention is not limited to these numerical examples.

In each of the above embodiments, the case where the reception arbiter 21 performs the priority arbitration by the round robin method has been described, but the present invention is not limited to this. For example, the main signal processing unit SP
It scans (or polls) the interrupt requests IRQ1 to IRQn from R1 to n cyclically to enable interrupt request REQE.
A method of returning 1 to n may be adopted. This is the same for the permission arbiter 11.

In each of the above embodiments, the interrupt decoder 40 and the processor selecting section 50 are realized by a hardware configuration. However, this section may be realized by a software configuration based on program control using a CPU or the like. It is clear.

Although a plurality of preferred embodiments of the present invention have been described, it is needless to say that various changes can be made in the configuration, control, and combination of these components without departing from the spirit of the present invention. Not even.

[0061]

As described above, according to the present invention, with a simple configuration, preferably with or without a processor failure,
Since time-series processing and non-time-series processing can be performed appropriately and efficiently, it greatly contributes to the improvement of the processing performance and reliability of the multiprocessor system.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating a configuration of a multiprocessor system according to a first embodiment.

FIG. 3 is a timing chart of an interrupt process according to the embodiment;

FIG. 4 is a diagram illustrating a configuration of a multiprocessor system according to a second embodiment.

FIG. 5 is a diagram illustrating a configuration of a multiprocessor system according to a third embodiment.

FIG. 6 is a diagram illustrating a configuration of a multiprocessor system according to a fourth embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Multiprocessor part 11 Permission arbiter (IABT) 12 Bus arbiter (BABT) 13 System bus arbiter (SABT) 20 Peripheral circuit part 21 Reception arbiter (PRU) 30 Common memory (MEMo) 40 Interrupt decoder (IDEC) 50 Processor selection part ( PSEL) PRa to PRc Processor SB System bus (S bus) SPR1 to SPRn Main signal processing unit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kazuhiko Sakato 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa F-term in Fujitsu Limited (Reference) 5B045 AA00 FF03 FF06 FF11 GG02 JJ13 5B061 BA01 BA02 BB04 BC03 BC08 GG11 5B083 AA08 BB03 CC04 CD01 CE01 DD09 EE02

Claims (7)

[Claims] 1. A multiprocessor system in which a plurality of processors and a plurality of peripheral circuit units are connected via a bus, and wherein a plurality of processors share an interrupt request from the plurality of peripheral circuit units. Or, a plurality of processors specified by two or more non-masters, a plurality of peripheral circuit units for outputting processor instruction information indicating master or unspecified together with generation of an interrupt request, and an interrupt request from each peripheral circuit unit And an allocation control unit for allocating to a master or one or more unspecified processors according to the processor instruction information. 2. A multiprocessor system in which a plurality of processors and a plurality of peripheral circuit units are connected via a bus, and wherein a plurality of processors share and process interrupt requests from the plurality of peripheral circuit units. A plurality of processors specified by the ID; a plurality of peripheral circuits for outputting a processor identification information indicating a unique identification ID or unspecified together with the generation of the interrupt request; and a processor for receiving the interrupt request from each peripheral circuit. A multi-processor system comprising: an allocation control unit that allocates a unique identification ID or one or more unspecified processors according to the instruction information. 3. An intermediary between a plurality of peripheral circuit units and an allocation control unit, arbitrating at least two competing interrupt requests from the plurality of peripheral circuit units, and inputting the input to the allocation control unit in a time-series manner. 3. The multiprocessor system according to claim 1, further comprising a reception arbiter for receiving. 4. The apparatus according to claim 1, further comprising a permission arbiter for arbitrating at least two competing interrupt reception requests from a plurality of processors and issuing a reception permission to any one of the processors. The multiprocessor system according to any one of the above. 5. The multiprocessor system according to claim 1, wherein the master processor is determined by an external setting or an autonomous arbitration operation of a plurality of processors. 6. The multiprocessor system according to claim 1, wherein the allocation control unit transfers an interrupt request to the master processor to a predetermined non-master processor when the master processor is abnormal. 7. The multiprocessor according to claim 2, wherein the allocation control unit transfers an interrupt request to the specific processor to another predetermined processor when the specific processor is abnormal. system.