JP2000305747A - Display controller and display control method in computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a processing speed by reducing access frequency to a local bus, and to properly attain an operation without unnecessarily leaving a binary/multilevel converting mechanism activated. SOLUTION: This display controller is provided with an address register 144 which stores an address to be written in a frame buffer memory 160, a register 146 which holds foreground data, a register 148 which holds background data, and a binary/multilevel converting circuit 142 which converts binary data into multilevel data (foreground data or background data). Then, the binary data can be written from a CPU 120 in the binary/multilevel converting circuit 142, and each time the binary data are written from the CPU 120, the binary data can be converted into the multilevel data, and written in the frame buffer memory 160.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a display control device relating to binary / multi-value conversion in display control, and a display control method in a computer system.

[0002]

2. Description of the Related Art Conventionally, a display control device in a computer system, as shown in FIG.
A display control circuit 40, a frame buffer memory 60 connected to the display control circuit 40 for storing display data, and a display device such as a CRT for displaying and displaying the display data of the frame buffer memory 60 under the control of the display control circuit 40. 8
0. And CPU
When writing binary data (font data, binary image data, etc.) from 20 to the frame buffer memory 60,
Since the frame buffer memory 60 for storing display data to be output and displayed on the display device 80 is multi-valued data (color data) in a pixel (pixel) system, it was necessary to convert binary data to multi-valued data. As a method of converting the binary data into multi-valued data, there are usually the following two methods.

(1) A method in which the CPU 20 converts binary data into multi-valued data and then writes the multi-valued data directly to the frame buffer memory 60 via the display control device 40. Path of path A.

(2) Activate a BitBLT (bit blit) 50 having a binary / multi-value conversion function in the display control device 40 and send binary data to the BitBLT 50 using the CPU 20 or DMA. And BitBL
A method in which T50 converts the data into multi-valued data and writes the data into the frame buffer memory 60.

[0005]

The conventional CPU described above.
20 is a method of converting binary data into multi-valued data and writing it directly to the frame buffer memory 60, the color format of the frame buffer memory 60 is 8 bpp.
(Bit per pixel), 16bpp, 24b
As a result, the frequency of access to the local bus 90 increases, and the processing time also increases. Also, in the method of starting BitBLT 50 and converting binary data into multi-valued data and writing the same in the frame buffer memory 60, binary data corresponding to the data amount set in the BitBLT 50 must be sent to the BitBLT 50.
BitBLT 50 does not end the processing. For this reason, if a state occurs in which the data to be sent to the BitBLT 50 is insufficient, the BitBLT
The LT 50 remains activated and cannot be used for other purposes.

Therefore, the present invention has been made in consideration of the above circumstances, and solves the above-mentioned problems, reduces the frequency of access to the local bus, and improves the processing speed.
It is an object of the present invention to provide a display control device and a display control method in a computer system in which a mechanism having a binary / multi-value conversion function can be appropriately operated without being inadvertently activated.

[0007]

In order to achieve the above object, the present invention provides a mechanism for writing multi-value data to a frame buffer memory which is a display memory every time the CPU writes binary data. Thus, the color format of the frame buffer memory is, for example, 8 bpp or 16 bp.
Even if it changes to p, 24 bpp, etc., the multi-value data is written to the frame buffer memory every time binary data is written without increasing the number of accesses to the local bus. It is characterized in that it is configured not to be in a state of being activated like BitBLT.

More specifically, the display control device has a function of writing binary data from the CPU to perform binary / multilevel conversion and writing the multilevel data into the frame buffer memory. I do. That is, it is configured such that a linear address or a two-dimensional address can be set as an address to be written. The write address is configured so that an arbitrary value can be set. The writing address automatically indicates the next writing address by writing the binary data, so that the binary data can be written continuously. Further, the configuration is such that the number of effective pits of binary data to be written can be set. Further, the bit value of the binary data is 0
In this case, the frame buffer memory is configured not to be rewritten.

According to the above configuration, conventionally, the CPU converts binary data into multi-valued data and writes it into the frame buffer memory, or activates BitBLT to execute BitBL
Although the required number of binary data has been sent to T and written in the frame buffer memory, according to the present invention, the binary data is sent to a binary / multi-value conversion circuit provided in the display control device. This makes it possible to convert the data into multi-valued data and write it to the frame buffer memory.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 shows a schematic configuration of a display control device in a computer system according to a first embodiment of the present invention. This system includes a CPU 120 that controls the entire system, a display control device 140, a frame buffer memory 160, and a display device 180.

The CPU 120 sends and writes binary data and the like to the display controller 140 via a local bus 190 such as a PCI bus to which various devices are connected.

The display control device 140 has a function of controlling access to the frame buffer memory 160 and outputting display data to the display device 180. Further, the display control device 140 is provided with a binary / multi-value conversion circuit 142, an address register (address RG) 144, a foreground data register (FG data RG) 146, and a background data register (BG data RG) 148. Have been.

The binary / multi-value conversion circuit 142 includes a CPU 120
Has the function of converting the binary data sent from the MPU into multi-valued data and writing the data into the frame buffer memory 160. The address register 144 is a register for setting an address on the frame buffer memory 160 into which the binary data is converted into the multi-value data by the binary-multi-value conversion circuit 142. There are two setting methods for the address register 144, a linear address method and a two-dimensional address method. The foreground data register 146 is a register for setting data to be written in a portion where the bit value of binary data is 1. The background data register 148 stores the pit value of the binary data as 0.
This is a register for setting the data to be written in the portion of (1).

The frame buffer memory 160 is a display memory for storing display data, and the format of the display data is a pixel format.

The display device 180 outputs and displays the display data of the frame buffer memory 160 under the control of the display control circuit 140.

Here, the concept of data when converting binary data into multi-valued data will be described with reference to FIG. As shown in the figure, in accordance with the bit value of the binary data to be written from the CPU 120, the foreground data register 14 is stored in the portion where the bit value is 1 in the frame buffer memory 160.
6 is written, and the data of the background data register 148 is written in the portion where the bit value is 0. In this way, the binary data is converted into the n-value data.

The concept of the memory map in the present embodiment will be described with reference to FIG. As shown, usually C
The space in which the PU 120 accesses the frame buffer memory 160 and the space in which the PU 120 accesses the binary / multi-level conversion circuit 142 are separate. When the CPU 120 writes the binary data into the binary / multi-level conversion circuit access space, the binary / multi-level conversion circuit 142 stores the data of the foreground data register 146 for the portion where the pit value of the binary data is 1;
The part “0” is converted into multi-valued data using the data of the background data register 148, and is written in the address position corresponding to the address information set in the address register 144 on the frame buffer memory 160.

The operation and operation of the above configuration are shown in FIG.
This will be described below with reference to the flowchart of FIG.

The CPU 120 sets an address in the frame buffer memory 160 for writing binary data in the address register 144 (step S402). next,
The foreground data and the background data are set in the foreground data register 146 and the background data register 148, respectively (step S40).
4).

As shown in the memory map of FIG.
The space in which the CPU 120 accesses the frame buffer memory 160 is different from the space in which the CPU 120 accesses the binary / multi-level conversion circuit 142. When the CPU 120 writes binary data in the binary / multi-level conversion circuit access space, (Step S406) The binary / multi-level conversion circuit 142 uses the foreground data when the pit value of the binary data is 1;
The part of 0 is converted into multi-valued data using the background data (step S408), and written into a position corresponding to the address information indicated by the address register 144 on the frame buffer memory 160 (step S410).

As described above, according to the present embodiment, the conversion of binary data into multi-valued data is performed in the display control device 140. The number of accesses to the local bus 190 is reduced to 1 / n, whereas the number of accesses to the local bus 190 can be significantly reduced. Therefore, even when the bus performance is slow, binary data can be written to the frame buffer memory at high speed. Also, the bus utilization of other devices connected to the bus is improved. (Second Embodiment) FIG. 5 is a diagram showing a schematic configuration of a display control device in a computer system according to a second embodiment of the present invention. This system includes a CPU 520 that controls the entire system, a display control device 540, a frame buffer memory 560, and a display device 580.

The CPU 520 sends and writes binary data and the like to the display control device 540 via a local bus 590 such as a PCI bus to which various devices are connected.

The display control device 540 has a function of controlling access to the frame buffer memory 560 and outputting display data to the display device 580. The display control device 540 includes a binary / multi-level conversion circuit 542, an address register (address RG) 544, a foreground data register (FG data RG) 546, a background data register (BG data RG) 548, and an address addition. A value register (address addition value RG) 550 is provided.

The binary-to-multivalue conversion circuit 542 includes a CPU 520
Has the function of converting the binary data sent from the CPU into multi-valued data and writing the data into the frame buffer memory 560. The address register 544 is a register for setting an address on the frame buffer memory 560 to which binary data is converted into multi-value data by the binary-multi-value conversion circuit 542 and then written. The address register 544 can be set in two ways: a linear address system and a two-dimensional address system. The foreground data register 546 is a register for setting data to be written in a portion where the bit value of binary data is 1. The background data register 548 stores the bit value of the binary data as 0.
This is a register for setting the data to be written in the portion of (1).
The address addition value register 550 is a register for setting a value (skip value) to be added to the address register 544 after writing the binary data.

The frame buffer memory 560 is a memory for storing display data, and the format of the display data is a pixel format.

The display device 580 displays and outputs the display data of the frame buffer memory 560 under the control of the display control circuit 540.

The operation and operation of the above configuration are shown in FIG.
This will be described with reference to the flowchart of FIG.

First, the CPU 520 sets an address on the frame buffer memory 560 for writing binary data in the address register 544 (step S602).
Next, the foreground data and the background data are set in the foreground data register 546 and the background data register 548, respectively (step S6).
04). Then, after writing the binary data, the address addition value data for updating the value of the address register 544 is set in the address addition value register 550 (step S606).

As in the first embodiment, when the CPU 520 writes binary data to the binary / multi-level conversion circuit access space (step S608), the binary / multi-level conversion circuit 542 is executed.
Is converted into multi-valued data by using the foreground data when the bit value of the binary data is 1 and the background data when the bit value is 0 (step S610). 54
The data is written to the address indicated by No. 4 (step S612).

When the writing to the frame buffer memory 560 is completed, the binary-to-multivalue conversion circuit 542 obtains the address to be written next by adding the address addition value to the address.
Set in the address register 544 (step S61)
4).

As described above, according to the present embodiment, the first
In addition to the embodiment, by writing binary data, the address is automatically updated to the next address to be written, so that the CPU 520 does not need to set the address every time. (Third Embodiment) FIG. 7 is a diagram showing a schematic configuration of a display control device in a computer system according to a third embodiment of the present invention. This system includes a CPU 720 that controls the entire system, a display control device 740, a frame buffer memory 760, and a display device 780.

The CPU 720 sends and writes binary data and the like to the display control device 740 via a local bus 790 such as a PCI bus to which various devices are connected.

The display controller 740 has a function of controlling access to the frame buffer memory 760 and outputting display data to the display 780. The display control device 740 includes a binary / multi-value conversion circuit 742, an address register (address RG) 744, a foreground data register (FG data RG) 746, a background data register (BG data RG) 748, and a length register. (Length RG) 750.

The binary-to-multivalue conversion circuit 742 includes a CPU 720
Has the function of converting the binary data sent from the MPU into multi-valued data and writing the data into the frame buffer memory 760. The address register 744 is a register for setting address information on the frame buffer memory 760 to be written after the binary data is converted into the multi-value data by the binary-multi-value conversion circuit 742. The address register 744 can be set in two ways: a linear address system and a two-dimensional address system. The foreground data register 746 is a register for setting data to be written in a portion where the bit value of binary data is 1. The background data register 748 is a register for setting data to be written in a portion where the bit value of binary data is 0. The length register 750 is a register for setting a data width converted into multi-valued data from binary data. That is, the register 750 can specify a valid data length for the bus 790.

The frame buffer memory 760 is a memory for storing display data, and the format of the display data is a pixel format.

The display device 780 displays and outputs the display data of the frame buffer memory 760 under the control of the display control circuit 740.

FIG. 8 is a diagram showing the concept of data when the number of effective bits is 4 bits. As shown in the figure, only 4 bits (shaded portion) of the binary data are converted into n-bit multi-valued data and written into the frame buffer memory 760 (shaded portion).

The operation and operation of the above configuration are shown in FIG.
This will be described with reference to the flowchart of FIG.

First, the CPU 720 sets an address in the frame buffer memory 760 for writing binary data in the address register 744 (step S902).
Next, the foreground data and the background data are set in the foreground data register 746 and the background data register 748, respectively (step S9).
04). Then, of the binary data, the data length to be converted to the multi-value data is set in the length register 750 (step S906).

As in the first embodiment, when the CPU 720 writes binary data into the binary / multi-level conversion circuit access space (step S908), the binary / multi-level conversion circuit 742 is executed.
Is converted into multi-level data using binary data with a bit value of 1 for foreground data and a bit value of 0 with background data (step S910), and is indicated by an address register 744 on the frame buffer memory 760. Write to the address (step S912). At this time, only the data having the length indicated by the length register 750 is rewritten to the multi-value data.

As described above, according to the present embodiment, even when the binary data to be written is smaller than the data length of the local bus 790, the binary / multi-level conversion circuit 742 can be effectively used. (Fourth Embodiment) FIG. 10 is a diagram showing a schematic configuration of a display control device in a computer system according to a fourth embodiment of the present invention. This system includes a CPU 1020 for controlling the entire system, a display control device 1040,
It comprises a frame buffer memory 1060 and a display device 1080.

The CPU 1020 sends and writes binary data and the like to the display control device 1040 via a local bus 1090 such as a PCI bus to which various devices are connected.

The display control device 1040 controls access to the frame buffer memory 1060 and the display device 1080
It has the function of outputting display data to The display control device 1040 includes a binary / multi-valued conversion circuit 1042, an address register (address RG) 1044, a foreground data register (FG data RG) 1046, and a background data register (BG data RG) 104.
8, a transparency setting register (transparency setting RG) 1050 is provided.

The binary-to-multivalue conversion circuit 1042 includes a CPU 10
It has a function of converting binary data sent from the MPU 20 into multi-valued data and writing the data into the frame buffer memory 1060. The address register 1044 is a register for setting address information on the frame buffer memory 1060 to be written after the binary data is converted into the multivalue data by the binary / multivalue conversion circuit 1042. The address register 1044 can be set in two ways: a linear address system and a two-dimensional address system. The foreground data register 1046 is a register for setting data to be written in a portion where the bit value of binary data is 1. The background data register 1048 is a register for setting data to be written in a portion where the bit value of binary data is 0. The transparency setting register 1050 is a register for setting the non-transparent mode / transparent mode.
Here, the non-transparent mode means that the bit value of the binary data is 0.
In this case, the background data is written in the frame buffer memory 1060. On the other hand, the transparent mode is a mode in which the data on the frame buffer memory 1060 is kept as it is when the bit value of the binary data is 0. ... see FIG.

The frame buffer memory 1060 is a memory for storing display data, and the format of the display data is a pixel format.

The display device 1080 includes a display control circuit 104.
Under the control of 0, the display data of the frame buffer memory 1060 is output and displayed.

The operation and operation of the above configuration are shown in FIG.
This will be described with reference to the flowchart of FIG.

First, the CPU 1020 sets an address in the frame buffer memory 1060 for writing binary data in the address register 1044 (step S12).
02). Next, the foreground data and the background data are set in the foreground data register 1046 and the background data register 1048, respectively (step S1204).

Here, when the non-transparent mode is set in the transparent setting register 1050 (non-transparent mode in S1206), the CPU 1020 executes the non-transparent mode access to the binary / multi-level conversion circuit access space as in the first embodiment. When the value data is written (step S1208), the binary / multi-value conversion circuit 104
Step 2 converts the foreground data into the binary data with the bit value of 1 using the foreground data and the background data with the bit value of 0 into the multi-value data (step S121).
0), writing to the address indicated by the address register 1044 on the frame buffer memory 1060 (step S1)
212).

On the other hand, when the transparent setting register 1050 is set to the transparent mode (transparent mode in S1206), C
When the PU 1020 writes the binary data to the binary / multi-level conversion circuit access space (step S1214), FIG.
As shown in (2), the binary-to-multivalue conversion circuit 1042 sets the bit value of the binary data to 1 (the bit value of S1216:
1), the data is converted into multi-valued data using the foreground data (step S1218), and the frame buffer memory 1
060 is written at a position corresponding to the address information set in the address register 1044 (step S122).
0). If the bit value is 0 (bit value of S1216: 0), the data in the frame buffer memory 1060 is left as it is (S1222).

As described above, according to the present embodiment, when the data in the frame buffer memory 1060 is directly written into the frame buffer memory 1060 for the back portion of the font pattern or the like, if the transparent mode is set, the binary data is converted. Just write in the frame buffer memory 10
Only the necessary part on 60 can be written with multi-value data.

[0052]

As described above in detail, according to the present invention, by providing the binary / multi-value conversion function, every time the binary data is written to the display control device, the data is converted into the multi-value data. Thus, the frequency of access to the bus can be reduced, the bus usage rate can be reduced, and the processing speed can be improved. Further, since the conversion into the multi-value data and the writing into the display memory are completed for each binary data to be written, there is no state in which the binary data has been activated, and it can be used at any time.

Further, according to the present invention, an address to be written next time can be automatically generated, so that it is not necessary to set an address every time binary data is written, thereby improving operability and processing speed. I can do it.

Further, according to the present invention, even when the data length of binary data to be written is shorter than the data length of the bus, the binary / multi-level conversion function functions properly. It does not require write processing.

Furthermore, according to the present invention, the back portion of binary data (mainly the portion having a bit value of 0) such as font data can be read even if it is desired to leave the data in the display memory as it is. The binary / multi-level conversion function can be appropriately used without performing the write processing by the modify write.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a display control device in a computer system according to a first embodiment of the present invention.

FIG. 2 is an exemplary view showing the concept of data when converting binary data into multi-level data according to the embodiment;

FIG. 3 is an exemplary view conceptually showing a memory map according to the embodiment;

FIG. 4 is an exemplary flowchart showing the flow of a binary / multi-value conversion process according to the embodiment;

FIG. 5 is a block diagram showing a schematic configuration of a display control device in a computer system according to a second embodiment of the present invention.

FIG. 6 is an exemplary flowchart showing the flow of a binary / multi-value conversion process according to the embodiment;

FIG. 7 is a block diagram showing a schematic configuration of a display control device in a computer system according to a third embodiment of the present invention.

FIG. 8 is a view showing a concept of data when the number of effective pits is 4 bits according to the embodiment;

FIG. 9 is an exemplary flowchart showing the flow of a binary / multi-value conversion process according to the embodiment;

FIG. 10 is a block diagram showing a schematic configuration of a display control device in a computer system according to a fourth embodiment of the present invention.

FIG. 11 is a conceptual diagram of writing in a transparent mode according to the embodiment.

FIG. 12 is an exemplary flowchart showing the flow of a binary / multi-value conversion process according to the embodiment;

FIG. 13 is a block diagram showing a schematic configuration of a display control device in a conventional computer system.

[Explanation of symbols]

140, 540, 740, 1040: display control device; 142, 542, 742, 1042: binary / multi-valued conversion circuit; 144, 544, 744, 1044: address register, 146, 456, 746, 1046: foreground data register 148, 548, 748, 1048 ... background data register, 160, 560, 760, 1060 ... frame buffer memory, 190, 590, 790, 1090 ... local bus, 550 ... address addition value register, 750 ... length register, 1050 ... Transparency setting register.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Kinya Maruko, Inventor 2-9-9 Suehirocho, Ome-shi, Tokyo Inside the Toshiba Ome Plant (72) Inventor Mitsuaki Takeda 2--9, Suehirocho, Ome-shi, Tokyo Stock Company Inside the Toshiba Ome Plant (72) Inventor Tadashi Yoshida 3-3-1 Shinmachi, Ome-shi, Tokyo Toshiba Computer Engineering Co., Ltd. (72) Inventor Kimihiko Tezuka 3-3-1 Shinmachi, Ome-shi, Tokyo Toshiba Computer Engineering F term in reference (reference) 5B069 BB20 LA12 5C082 AA01 BA34 BA39 BB15 CB01 DA87 MM02

Claims (8)

[Claims] 1. A display memory for storing display data and a display device for outputting and displaying data stored in the display memory are connected to convert binary data transmitted via a bus into multi-value data. In a display control device having a binary / multilevel conversion function, address conversion means for storing address information to be written to the display memory after converting the binary data into multilevel data; A foreground data setting means for setting data to be written in a binary data portion having a predetermined bit value; and in the binary data, a binary data portion having a bit value different from the predetermined bit value. With reference to the background data setting means for setting the data to be written, and the set values of the foreground data setting means and the background data setting means, Binary-to-multilevel conversion means for converting binary data to multilevel data; and writing for writing the binary data sent out via the bus to a memory space associated with the binary-to-multilevel conversion means. Means, each time the writing means writes binary data to the memory space associated with the binary / multi-valued conversion means, the binary / multi-valued conversion means converts the binary data into multi-valued data. A display control device configured to write into the display memory with reference to the address information of the address storage means. 2. When the writing means writes binary data to the binary / multi-value conversion means, a predetermined addition value is generated for the address stored in the address storage means and the addition value is stored. An address addition value setting means is provided, and each time the writing means writes binary data to the binary / multi-value conversion means, an address for the next writing process is referred to by referring to a storage value of the address addition value setting means. 2. The display control device according to claim 1, wherein automatic setting is possible. 3. An effective data length storage means for storing a data length of the binary data to be converted into multi-valued data, wherein when the transmitted binary data is shorter than the data length of the bus, 2. The display control device according to claim 1, wherein the multi-value conversion means performs a binary-multi-value conversion with reference to the effective data length storage means. 4. A non-transparent mode in which the binary data is a predetermined bit value and is written in the display memory with reference to a setting value of the background data setting means, and wherein the binary data is the predetermined bit value. 2. The display control device according to claim 1, further comprising a transparent mode in which the data in the display memory is kept as it is when the bit value is different from the bit value. 5. A display memory for storing display data, a display device for outputting and displaying data stored in the display memory, and a display memory connected to the display memory and the display device and transmitted via a bus. In a computer system comprising a display control device having a binary / multi-value conversion function for converting value data into multi-value data, an address to be written to the display memory after the conversion of the binary data into the multi-value data is set. In the binary data, data to be written in a binary data portion having a predetermined bit value is set as foreground data, and a bit value different from the predetermined bit value in the binary data is set. Is set as background data, and the binary data is written to a memory space related to the binary-to-multilevel conversion function. In each writing, the binary data is converted to multi-level data by referring to the foreground data and the background data, and is written to the display memory by referring to the address information. A display control method in a computer system, comprising: 6. A predetermined addition value is generated for the address in accordance with the writing of the binary data, and the addition value is added to the address. 6. The display control device in a computer system according to claim 5, wherein an address adding process is executed to automatically set a next address. 7. A data length for converting the binary data into multi-valued data is set. If the transmitted binary data is shorter than the data length of the bus, the binary / multi-valued conversion function performs the data conversion. 6. The display control device in a computer system according to claim 5, wherein a binary-to-multivalue conversion is performed with reference to the length. 8. When the binary data is a predetermined bit value, a non-transparent mode is executed in which the binary data is written to the display memory with reference to the background data, and the binary data is the predetermined bit value. 6. The display control device according to claim 5, wherein when the bit value is different from the above, a transparent mode in which the data in the display memory is kept as it is is executed.