JP2000299928A - Power supply control device and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a shunt resistor unneeded and to respond at high speed to an abnormal current in the case of an imperfect layer short-circuit, by constituting a full-bridge a DC-DC converter with the second main electrodes of first and second semiconductor elements, the first main electrode of third and fourth semiconductor elements and a load having first and second terminals. SOLUTION: An n-channel first switch circuit 801 has a first main electrode terminal DA1 connected to an external input terminal T1, a second main electrode terminal SA1 connected to a first external output terminal T3, and a control electrode terminal GA1. Another n-channel second switch circuit 802 has a first main electrode terminal DA2 connected to the external input terminal T1, a second main electrode terminal SA2 connected to a second external output terminal T33, and a control electrode terminal GA2. This control circuit detects an abnormal current in either one of the first switch circuit 801 and second switch circuit 802. If an abnormal current occurs, one of the first and second switch circuits 801, 802 is controlled in such a way as to be turned on or off in order to generate current oscillation, which breaks the first and/or second switch circuits 801, 802.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a power supply control device and a semiconductor device used for the same, and more particularly to a semiconductor device suitable for an H-bridge type power supply control device capable of controlling the rotation of a DC motor in both forward and reverse directions. .

[0002]

2. Description of the Related Art As a semiconductor device (power semiconductor device) used in a conventional power supply control device, there is, for example, one shown in FIG. The power supply control device shown in FIG. 10 is a device that selectively supplies power from a battery to each load in an automobile and controls power supply to the load by a transistor QF with a built-in temperature sensor. The power supply control device shown in FIG. 10 includes a power supply 10 for supplying an output voltage VB.
1 is connected to one end of the shunt resistor RS, and the other end is connected to the drain terminal D of the temperature sensor built-in transistor QF. Further, a load 102 is connected to the source terminal S of the transistor QF with a built-in temperature sensor. Here, the load 102 corresponds to a headlight of an automobile, a drive motor of a power window, and the like. The power supply control device illustrated in FIG. 10 further includes a driver 901 that detects a current flowing through the shunt resistor RS and controls driving of the temperature sensor built-in transistor QF by a hardware circuit.
An A / D converter 902 and a microcomputer (CPU) 903 for controlling on / off of a drive signal of a transistor QF with a built-in temperature sensor based on a current value monitored by a driver 901 are provided. The transistor QF with a built-in temperature sensor has an overheat cutoff function of forcibly turning off the conduction state by a built-in gate cutoff circuit when the temperature of the semiconductor chip rises to a temperature equal to or higher than a specified value.

In FIG. 10, ZD1 is a signal between the gate terminal G and the source terminal S of the transistor QF with a built-in temperature sensor.
This is a Zener diode that bypasses an overvoltage applied to the true gate TG of the temperature sensor built-in transistor QF while keeping it at 2V. Driver 9
01 is a differential amplifier 911, 9 as a current monitor circuit
13, a differential amplifier 912 as a current limiting circuit, a charge pump circuit 915, and a temperature sensor via an internal resistor RG based on an on / off control signal from the microcomputer 903 and an overcurrent determination result from the current limiting circuit. The driving circuit 914 drives the true gate G of the built-in transistor QF. If an overcurrent is detected via the differential amplifier 912 based on the voltage drop of the shunt resistor RS and the current exceeds the determination value (upper limit), the drive circuit 914 turns off the transistor QF with a built-in temperature sensor. Then, when the current decreases below the judgment value (lower limit), the transistor QF with a built-in temperature sensor is turned on. On the other hand, the microcomputer 903 constantly monitors the current via the current monitor circuit (differential amplifiers 911 and 913), and turns off the drive signal of the temperature sensor built-in transistor QF if an abnormal current exceeding a normal value flows. This turns off the temperature sensor built-in transistor QF. Note that if the temperature of the transistor with built-in temperature sensor QF exceeds a specified value before the drive signal of the off control is output from the microcomputer 903, the transistor with built-in temperature sensor QF is turned off by the overheat cutoff function.

[0004]

However, the above-described conventional power supply control device requires a shunt resistor RS connected in series to a power supply path for current detection. By increasing the load current,
There is a problem that the heat loss of the shunt resistor cannot be ignored.

The above-described overheat cutoff function and overcurrent control circuit function when a large current flows due to the almost complete short-circuit state occurring in the load 102 or the wiring. It does not function when a small short-circuit current flows due to the occurrence of a rare short-circuit such as a short-circuit, and the microcomputer 903 must detect an abnormal current via a current monitor circuit and control the transistor QF with a built-in temperature sensor to turn off. In some cases, the response by the microcomputer to such an abnormal current is poor.

Also, a shunt resistor RS and an A / D converter 90
2. Since the microcomputer 903 and the like are required, a large mounting space is required, and there is also a problem that the cost of the power supply control device is increased by these relatively expensive articles.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and circumstances, and eliminates the need for a shunt resistor. An object of the present invention is to provide an H-bridge type power supply control device which enables high-speed response and is easy to integrate.

It is another object of the present invention to provide an H-bridge type power supply control device capable of performing various measurements such as undercurrent detection, lamp disconnection detection, and open detection and controlling the same.

Still another object of the present invention is to eliminate the need for a shunt resistor directly connected to a power supply path for current detection, thereby suppressing heat loss of a power supply control device, and providing an imperfect circuit having a certain degree of short-circuit resistance. It is an object of the present invention to provide a semiconductor device which enables a high-speed response to an abnormal current when a rare short circuit such as a short circuit occurs, and which can be easily integrated and is compatible with an inexpensive H-bridge circuit.

Still another object of the present invention is to detect an undercurrent,
An object of the present invention is to provide a semiconductor device which can cope with an H-bridge circuit which can perform various measurements such as lamp disconnection detection and open detection and control thereof.

[0011]

A first feature of the present invention is as follows.
A first switching circuit incorporating a first main semiconductor element and having a first main electrode terminal, a second main electrode terminal connected to a first terminal of a load, and a control electrode terminal; and a second main semiconductor. A second switching circuit incorporating the element and having a first main electrode terminal, a second main electrode terminal connected to a second terminal of the load, and a control electrode terminal; and a second switching circuit connected to the first terminal of the load. A third main semiconductor element having one main electrode, a second main electrode, and a control electrode; and a first main electrode, a second main electrode, and a control electrode connected to a second terminal of the load. 4th
And a reference semiconductor element having a first main electrode connected to the first main electrode terminal of the first and second switching circuits, a control electrode, and a second main electrode connected to the reference resistor, respectively. And the second of the first and second main semiconductor elements.
A first input terminal connected to the cathodes of the first and second isolation diodes, and a first input terminal connected to the cathodes of the first and second isolation diodes, and a second input terminal connected to the second main electrode of the reference semiconductor element. A comparator connected to two input terminals;
And a first and second multiplexer connected to the control electrodes of the second and main semiconductor elements, respectively, and a control voltage applied to the control electrodes of the first and second multiplexers and the reference semiconductor element according to the output of the comparator. Detecting at least an abnormal current flowing through the first and second main semiconductor elements, comprising at least a control voltage supply means for supplying and a logic circuit connected to each control electrode of the third and fourth main semiconductor elements; When an abnormal current occurs, one of the first and second main semiconductor elements is turned on / off to generate a current oscillation, and the current oscillation causes conduction of one of the first and second main semiconductor elements. That is, the power supply control device interrupts the state.

Here, the first main semiconductor element includes a first main electrode connected to the first main electrode terminal of the first switching circuit, and a second main electrode connected to the second main electrode terminal. And a control electrode connected to the control electrode terminal. Further, the second main semiconductor element includes a first main electrode connected to the first main electrode terminal of the second switching circuit, a second main electrode connected to the second main electrode terminal, and a control electrode terminal. And a control electrode connected to the control electrode. Therefore, the full bridge type is formed by the second main electrode of the first and second main semiconductor elements, the first main electrode of the third and fourth main semiconductor elements, and the load having the first and second terminals. dc-dc converter, ie
An "H bridge circuit" is configured. As the load of the H-bridge circuit, an inductive load such as a DC motor that reverses the rotation direction or a stepping motor can be used. Alternatively, another H-bridge circuit configuration such as an H-bridge circuit for inverting a write current flowing through a magnetic head having no middle point, such as a thin film head, for writing data for magnetic recording such as a hard disk drive or a floppy disk drive. It can also be applied to the load of.

For example, a DC motor in which a first terminal is connected to the first and third main semiconductor elements and a second terminal is connected to the second and fourth main semiconductor elements is as follows. Can be inverted.

First, in order to rotate the DC motor in the forward direction, the first multiplexer is turned on, the second multiplexer is turned off, and an "H" level signal is applied to the control electrode of the first main semiconductor element. Then, an "L" level signal is applied to the control electrode of the second main semiconductor element. At the same time, the logic circuit applies an “H” level signal to the control electrode of the fourth main semiconductor element and an “L” level signal to the control electrode of the third main semiconductor element. That is, a first main semiconductor element,
The fourth main semiconductor element is brought into a conductive state, and current flows from the first main semiconductor element via a DC motor, and further via a path via the fourth main semiconductor element.

On the other hand, in order to rotate the DC motor in the reverse direction, the first multiplexer is turned off, the second multiplexer is turned on, and "L" is applied to the control electrode of the first main semiconductor element.
The level signal is applied to the control electrode of the second main semiconductor element as an “H” level signal. At the same time, an "H" level signal is applied to the control electrode of the third main semiconductor element and an "L" level signal is applied to the control electrode of the fourth main semiconductor element.
The second main semiconductor element and the third main semiconductor element are brought into conduction, and a current flows from the second main semiconductor element via a direct-current motor and further through a path via the third main semiconductor element.

The stepping motor has a rotor composed of a rotatable movable magnet, and a plurality of driving coils composed of electromagnets are arranged around the rotor. These drive coils are selected by the H-bridge circuit of the present invention, and a current of a predetermined magnitude is made to flow in a pulse shape, so that the position and the number of revolutions of the rotor can be controlled in an open loop.

As the first to fourth main semiconductor elements and the reference semiconductor element, MOS transistors such as a MOS field effect transistor (FET) and a MOS static induction transistor (SIT), various MOS composite devices, Insulated gate bipolar transistor (IGB
Insulated gate type power devices such as T) can be used. These semiconductor elements may be of an n-channel type or a p-channel type. Further, the “first main electrode” means one of an emitter electrode and a collector electrode in an IGBT, and one of a source electrode and a drain electrode in a MOS transistor. The “second main electrode” is one of an emitter electrode and a collector electrode that does not become the first main electrode in an IGBT, and one of a source electrode and a drain electrode that does not become the first main electrode in a MOS transistor. Mean one. That is, if the first main electrode is an emitter electrode, the second main electrode is a collector electrode, and if the first main electrode is a source electrode, the second main electrode is a drain electrode. The “control electrode” obviously means the gate electrodes of the IGBT and the MOS transistor.

According to a first feature of the present invention, an H bridge in which one of the first and second main semiconductor elements conducts by controlling the voltage of the control electrode by the first and second multiplexers. The operation corresponding to the circuit becomes possible. As the first and second main semiconductor elements, for example, a power MO
When the S transistor is used, the voltage between the terminals (voltage between the drain and the source) of the power MOS transistor which forms a part of the power supply path is changed when the state changes from the off state to the on state (for example, in the case of an n-channel FET). In the voltage characteristics, the state of the power supply path and the load,
That is, it changes according to the wiring inductance of the path and the time constant based on the wiring resistance and the short-circuit resistance. For example,
In a normal operation in which a short circuit has not occurred, the voltage quickly falls below a predetermined voltage. However, in a case where a complete short circuit has occurred, the voltage does not fall below the predetermined voltage. Further, when an incomplete short circuit having a certain short-circuit resistance occurs, although it converges to a predetermined voltage, it takes a long time to converge.

A first feature of the present invention utilizes a transient voltage characteristic of a semiconductor element when transitioning from an off state to an on state in such a semiconductor element. That is, by detecting the difference between the voltage between the terminals of the first and second main semiconductor elements and the voltage between the terminals of the reference semiconductor element (reference voltage), the first and second power supply paths are formed. This is to determine the degree to which the terminal voltage of the main semiconductor element (that is, the current in the power supply path) deviates from the normal state.

Therefore, it is possible to eliminate the need for the conventional shunt resistor connected in series to the power supply path for detecting the current, and to reduce not only an overcurrent due to a complete short circuit but also a certain short-circuit resistance. It is also possible to easily detect an abnormal current when a rare short circuit such as an incomplete short circuit occurs. A second feature of the present invention is that the first main semiconductor element is built in,
A first switching circuit having a first main electrode terminal connected to the external input terminal, a second main electrode terminal connected to the first external output terminal, and a control electrode terminal; and a second main semiconductor element built therein. A second switching circuit having a first main electrode terminal connected to the external input terminal, a second main electrode terminal connected to the second external output terminal, and a control electrode terminal; and a third external output terminal A third main semiconductor element having a first main electrode, a second main electrode and a control electrode connected to a ground terminal, and a first main electrode connected to a fourth external output terminal and a ground terminal A fourth main semiconductor element having a second main electrode and a control electrode, and a first main electrode, a control electrode, and a reference resistor respectively connected to the first main electrode terminals of the first and second switching circuits. Reference half having a second main electrode connected to Body element, first and second isolation diodes each having an anode connected to the second main electrode of the first and second main semiconductor elements, and a first input connected to the cathodes of the first and second isolation diodes. A comparator having terminals connected to each other and a second input terminal connected to a second main electrode of the reference semiconductor device; and a first and second multiplexer connected to control electrodes of the first and second main semiconductor devices, respectively. Control voltage supply means for supplying a control voltage to each of the control electrodes of the first and second multiplexers and the reference semiconductor element according to the output of the comparator; and control of each of the third and fourth main semiconductor elements. An abnormal current flowing through the first and second loads connected to the first and second external output terminals, respectively. Main half of A semiconductor device that generates a current oscillation by controlling ON / OFF of one of the body elements and interrupts one of the conduction states between the external input terminal and the first and second external output terminals by the current oscillation That is.

The first main semiconductor element includes a first main electrode connected to the first main electrode terminal of the first switching circuit, a second main electrode connected to the second main electrode terminal, and a control electrode. A control electrode connected to the terminal. Further, the second main semiconductor element includes a first main electrode connected to the first main electrode terminal of the second switching circuit, a second main electrode connected to the second main electrode terminal, and a control electrode terminal. And a control electrode connected to the control electrode.

Between the first to fourth external output terminals, the first
And connecting a load having a second terminal to
A bridge circuit is configured. In this H-bridge circuit, the first multiplexer is turned on, the second multiplexer is turned off, and an "H" level signal is applied to the control electrode of the first main semiconductor element. Is applied with an "L" level signal. At the same time, the logic circuit applies an “H” level signal to the control electrode of the fourth main semiconductor element and an “L” level signal to the control electrode of the third main semiconductor element, thereby providing the first main semiconductor element. A current flows from the semiconductor device through a first external output terminal, a load, a fourth external output terminal, and further to a fourth main semiconductor device.

On the other hand, the first multiplexer is turned off,
Are turned on, and an “L” level signal is applied to the control electrode of the first main semiconductor element and an “H” level signal is applied to the control electrode of the second main semiconductor element. At the same time, an “H” level signal is applied to the control electrode of the third main semiconductor element.
By applying an “L” level signal to the control electrode of the fourth main semiconductor element, the second main semiconductor element passes through the second external output terminal, the load, the third external output terminal, and A current flows in a path leading to the third main semiconductor element.

According to a second feature of the present invention, the first and second switching circuits, the third and fourth main semiconductor elements, the reference semiconductor element, the first and second isolation diodes, the comparators, the first and second switching circuits, Preferably, the two multiplexers, the control voltage supply means and the logic circuit are integrated on the same semiconductor substrate. When integrated on the same semiconductor substrate, the external input terminal, the first to fourth external output terminals,
For example, 1 × 1 formed on the element formation surface of a semiconductor chip
Aluminum (Al), a plurality of high impurity density regions (source region / drain region, or emitter region / collector region, etc.) doped with a donor or an acceptor of about 0 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ^−3, etc. Or aluminum alloy (Al-Si, Al-Cu-Si)
And so on. These metal wirings are in ohmic contact with the high impurity density region.
An oxide film (SiO ₂ ), PS,
A passivation film made of a G film, a BPSG film, a nitride film (Si ₃ N ₄ ), a polyimide film, or the like is formed. Then, a plurality of openings (windows) are provided in a part of the passivation film so as to expose the plurality of electrode layers, and bonding pads necessary as external input terminals and first to fourth external output terminals are formed. I have. A bonding wire made of a gold (Au) wire or an aluminum (Al) wire having a diameter of 50 μm to 200 μm is connected to the bonding pad. When the semiconductor element is mounted on the surface of the wiring board by a face-down (flip chip) method in which the surface on which the integrated circuit is disposed faces downward, the external input terminals and the first to fourth terminals are used. It is not always necessary to arrange the external output terminals and the like in the peripheral portion of the semiconductor element (semiconductor chip).

When, for example, a power MOS transistor is used as the first and second main semiconductor elements constituting the semiconductor device, the terminal voltage (drain-source voltage) of the power MOS transistor forming a part of the power supply path is ,
In the voltage characteristics at the time of transition from the off state to the on state (for example, falling in the case of an n-channel FET),
It changes according to the state of the power supply path and the load, that is, the time constant based on the wiring inductance and the wiring resistance and the short-circuit resistance of the path. For example, in a normal operation in which a short circuit does not occur, the voltage quickly decreases to a predetermined voltage or less, but when a complete short circuit occurs, the voltage does not decrease to a predetermined voltage or less.
Further, when an incomplete short circuit having a certain short-circuit resistance occurs, although it converges to a predetermined voltage, it takes a long time to converge.

A second feature of the present invention utilizes a transient voltage characteristic of the semiconductor element when transitioning from an off state to an on state in such a semiconductor element. That is, the voltage between the terminals of the first and second main semiconductor elements and the first and second
Of the first and second main semiconductor elements forming a part of the power supply path (i.e., the current of the power supply path) ) Deviates from the normal state.

Therefore, it is not necessary to use a conventional shunt resistor connected in series to a power supply path for detecting a current, so that heat loss of various devices of the H-bridge type can be suppressed. It is possible to easily detect not only the current but also an abnormal current when a rare short circuit such as an incomplete short circuit having a certain short-circuit resistance occurs. Furthermore,
Overcurrent can be detected without using a shunt resistor. Especially when the on / off control of the semiconductor device is configured by a hardware circuit, no microcomputer is required, so the occupied area can be reduced and the manufacturing unit cost can be reduced. It is possible.

Particularly, the current capacity of the reference semiconductor element is the first.
The ratio of the number of unit cells constituting each semiconductor element may be determined so as to be smaller than the current capacity of the second main semiconductor element. By selecting the number of unit cells and setting the layout of the planar pattern of the power IC, the circuit configuration of the reference semiconductor element can be reduced, and the area of the semiconductor chip can be reduced. Equipment cost can be greatly reduced.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the H-bridge circuit of the present invention, a typical structure of a power supply control circuit in the case of a single power line serving as a basis of the H-bridge circuit and its basic structure will be described. The operation will be described.

(Structure and Operation of Power Supply Control Circuit) As shown in FIG. 6, a power supply control circuit having a current oscillation type cutoff function, which is the basis of the present invention, incorporates a main semiconductor element (power device) QA. The switching circuit 803 and the abnormal current of the main semiconductor element QA are detected, and when an abnormal current occurs, the main semiconductor element QA is turned on / off to generate a current oscillation. Is a semiconductor integrated circuit (power IC) in which a control circuit to be integrated is integrated on the same substrate.

[0031] Normally, the power IC connects the input terminal _{T D} to the power source 101 for supplying an output voltage VB, it operates to connect the output terminal _{T S} to the load 102. Switching circuit 803 constituting the power IC has a first main electrode terminal DA to the input terminal T _D, connecting the second main electrode terminals SA to the output terminal T _S. And this switching circuit 8
03 is connected to the first main electrode (drain electrode) of the main semiconductor element (power device) QA, and the second main electrode terminal SA is connected to the second main electrode (source) of the main semiconductor element QA. Electrode) S. Here, as shown in FIG. 11, the switching circuit 803 includes a control electrode TG and a second main electrode (source electrode) S of the main semiconductor element QA.
₀ , the overheat cutoff circuit 120 is connected. Note that if a method of measuring the number of times of current oscillation is adopted, the overheat cutoff circuit 120 is not essential.

Here, an n-channel type semiconductor device monolithically integrated on the same semiconductor substrate will be described. As shown in FIG. 6, the control circuit of the semiconductor device of the present invention includes a switching circuit 803 having an n-channel type main semiconductor element QA, and an n-channel MOS transistor QB as a reference semiconductor element connected in parallel to the switching circuit 803. And a comparator CMP1 for comparing the voltage between the main electrodes of the main semiconductor element QA with the voltage between the main electrodes of the reference semiconductor element QB, and the main semiconductor element QA and the reference semiconductor element QB according to the output of the comparator CMP1. At least control voltage supply means 111 for supplying a control voltage to the control electrode is provided.

As shown in FIG. 11, the switching circuit 8
The overheat cutoff circuit 120 constituting the main semiconductor element Q
The overheat interrupting element QS connected to the gate electrode of A, a latch circuit 122 for inputting a signal to the gate electrode of the overheat interrupting element QS, a temperature sensor 121 for controlling the state of the latch circuit 122, and the like. I have. That is, when the temperature sensor 121 detects that the surface temperature of the semiconductor chip 110 has risen to a specified temperature or higher, the state of the latch circuit 122 changes according to the detection information from the temperature sensor 121, and this state changes. Latch circuit 122
Is held. As a result, the overheat cut-off element QS is turned on operation, short circuit between the gate electrode TG and the source electrode S ₀ of the main semiconductor element QA, forcibly off control of the main semiconductor element QA.

Here, the temperature sensor 121 is formed by connecting four diodes made of polysilicon or the like in series.
The temperature sensor 121 is integrated near the main semiconductor element QA. As the junction temperature of the main semiconductor element QA rises, the surface temperature of the semiconductor chip rises and the temperature sensor 1
The forward drop voltage of the four diodes 21 gradually decreases. Then, when the sum of the forward drop voltages of the four diodes decreases to a potential at which the gate potential of the nMOS transistor Q51 is set to the “L” level, the nMOS transistor Q51 is turned off from the on state. Thereby, the gate potential of the nMOS transistor Q54 is pulled up to the potential of the gate control terminal G of the main semiconductor element QA, and the nMOS transistor Q54 is turned on.
Therefore, the nMOS transistor Q53 is turned off, the nMOS transistor Q52 is turned on from the off state, and "1" is latched by the latch circuit 122. At this time, the output of the latch circuit 122 becomes “H”.
Level, and the overheat cutoff element QS is turned on from the off state. Consequently, is the main semiconductor element QA true gate TG and the second main electrode (source electrode) S ₀ between a short circuit, the main semiconductor element QA is turned off from the on state,
Overheating will be interrupted.

Referring back to FIG. 6, the power supply control circuit of the present invention comprises a MOS transistor QB as a reference semiconductor element,
Resistances R1, R2, R5, R8, RG, reference resistance Rr, Zener diode ZD1, diode D1, comparator CM
P1, a drive circuit 111 serving as a control voltage supply means, and a main semiconductor element QA and the same semiconductor substrate (semiconductor chip)
It is monolithically mounted on 110. Further, outside the semiconductor chip 110 constituting the semiconductor device of the present invention,
Resistor R10 and switch SW connected to control terminal _TG
1 is provided. The power supply control circuit of the present invention functions when a user or the like turns on the switch SW1.

Drive circuit 111 as control voltage supply means
Has a source transistor Q5 whose collector side is connected to the potential VP, and a sink transistor Q6 whose emitter side is connected to the ground potential (GND), which are connected in series.
On / off control of the source transistor Q5 and the sink transistor Q6 based on the switching signal by the on / off switching of the switch SW1, and outputs a signal for controlling the drive to the control electrodes of the main semiconductor element QA and the reference semiconductor element QB. . The bipolar transistor (B) shown in FIG.
JT) instead of MOS transistors
May be configured. For example, in the case of CMOS, the driving circuit 11
1 can also be configured. If the drive circuit 111 is constituted by MOS transistors, the power IC (semiconductor device) of the present invention can be manufactured by a simple MOS transistor manufacturing process.
Can be manufactured. Also, drive circuit 1 with BJT
With the configuration of 11, the power IC of the present invention can be manufactured by the BIMOS manufacturing process. The output voltage VB of the power supply 101 is, for example, 12 V, and the output voltage VP of the charge pump is, for example, VB + 10 V.

The first main electrode (drain electrode) of the main semiconductor element QA and the first main electrode (drain electrode) of the reference semiconductor element QB constituting the switching circuit 803 are connected to each other and maintained at a common potential. . Further, the reference resistance Rr is provided on the second main electrode (source electrode) of the reference semiconductor element QB.
Is connected. Note that the reference resistor Rr does not necessarily need to be monolithically integrated, but may be connected via an external terminal as an external resistor of the semiconductor device of the present invention. The resistance value of the reference resistor Rr is the MOS transistor Q
What is necessary is just to select according to the ratio of B and the channel width W of the main semiconductor element QA. For example, as described above, the ratio of the channel width W between the MOS transistor QB and the main semiconductor element QA is set to 1:
When it is set to 1000, the resistance value of overload state is 1000.
What is necessary is just to set so that it may become a double value. This reference resistance Rr
Set by the main semiconductor element QA same drain as when the overload current flows in the abnormal operation of the - source voltage V _DS of the can be generated in the reference semiconductor element QB.

A series circuit of a resistor R1 and a resistor R2 is connected between the first main electrode terminal DA and the second main electrode terminal SA of the switching circuit 803. This resistance R1 and resistance R2
Of between connecting point and the second main electrode terminals SA, via a terminal T _R, the variable resistor RV is connected via an external terminal as an external resistance. By changing the resistance value of the variable resistor RV, the resistance value of the reference resistor Rr can be variably set equivalently.
This makes it possible to cover a plurality of specifications with one type of semiconductor chip 110.

The "+" input terminal of the comparator CMP1 shown in FIG.
- parallel resistance (R2‖RV) and de-divided voltage of the source S _{voltage) V DS} between the resistor R1 and the resistor R2 and the variable resistor RV is supplied via a resistor R5. Also, comparator CMP
The source voltage _VSB of the reference semiconductor element QB is supplied to the “−” input terminal of No. 1. "+" Signal level at the input terminal _V +>"-" signal level V of the input terminals _- when the output of the comparator CMP1 becomes the "H" level, the drive circuit 1
11 supplies a voltage to the gate electrode. In the opposite case, the output of the comparator CMP1 becomes “L” level, and the driving circuit 1
11 turns off the gate drive of the switching circuit 803. As described later, the comparator CMP1 has a certain hysteresis characteristic.

FIG. 8 is a conceptual equivalent circuit focusing on the main semiconductor element QA used in the power IC of the present invention. The equivalent circuit of the main semiconductor element QA, equivalent current source _g m · _v i,
Drain resistance rd, the gate-source capacitance _{C GS,} is shown in a simplified using the gate-drain capacitance _{C GD} and the drain-source capacitance CD _S. Where g
_m is the transmission conductance of the main semiconductor element QA.
When an equivalent circuit of the main semiconductor element QA is used, a power supply path from the power supply 101 to the load 102 is represented as a circuit as shown in FIG. The load 102 includes a wiring inductance L0 and a wiring resistance R0 of the power supply path.

FIG. 7 shows the voltage Vd between the drain and source of the main semiconductor element QA forming a part of such a power supply path.
_The falling voltage characteristic when the _DS transitions from the OFF state to the ON state is shown by the reference load (normal operation) when the wiring between the load 102 or the main semiconductor element QA and the load 102 is short-circuited.
Is a transient response curve shown when the load 102 has a resistance of 1 kΩ. The fall characteristic is the impedance of the entire power supply path according to the embodiment of the present invention, for example, the wiring inductance of a load circuit or a power supply system,
Provides a transient response according to the wiring resistance.

[0042] First, the drain when the resistance of the load 102 in FIG. 7 is a 1 k [Omega - the variation of the source voltage _{V D S,}
It can be considered as follows. That is, depending on the characteristics of the main semiconductor element QA used in this measurement, for example, the drain current _ID
= 12mA (when power supply voltage is 12V and load resistance is 1kΩ)
It is assumed that the true gate-source voltage V _TGS is approximately equal to the threshold voltage Vth = 1.6V. And FIG.
Since the charging of the true gate TG of the main semiconductor element QA by the drive circuit 111 is continued, the true gate-source voltage V _TGS rises if this state is continued.
However, since the drain-source voltage _VDS decreases and the true gate-drain capacitance value _CGD increases, the charge that reaches the true gate-source voltage _VTGS is absorbed. That is, the drain - source voltage V _DS is true gate - charge reaches the source voltage V _TGS is to generate a capacity sufficient not to cause potential increase, the true gate - source voltage V _TGS is about 1.6V (= Vth). That is, at each lapse of time after the main semiconductor element QA transitions to the ON state, the charged charge sent to the gate G by the drive circuit 111 is absorbed, and the true gate TG voltage V
Drain-source voltage V that keeps _TGS constant
_DS .

[0043] Here, the drain load resistance corresponding to 1 k [Omega lower load R - the difference from the curve when the load resistance = 1 k [Omega 7-source voltage _{V DS} and [Delta] V _DS.
Then, the true gate corresponding to the load R in the time t - the source voltage and V _{TGS R.} That is, if a voltage corresponding to the charge of (1) is _subtracted from the true gate-source voltage V _TGSR , Q _GD = ΔV _DS × C _GD + (V _TGSR −Vth) × C _GS. , The true gate-source voltage V _TGSR substantially _equals the threshold voltage Vth = 1.6V. In other words, the true gate-source voltage V _TGSR means that the potential has increased from the threshold voltage Vth = 1.6 V by a voltage corresponding to the charge Q _GD . This can be expressed by the following equation.

(V _TGSR −Vth) × C _GS + ((V _TGSR −Vth) −ΔV _DS ) × C _GD = (ΔV _DS − (V _TGSR −Vth)) × C _GD (2) V _TGSR −Vth = ΔV _DS × 2C _GD / (C _GS + 2C _GD ) (3) ∴ΔV _DS = (V _TGSR −Vth) · ((C _GS / 2C _GD ) +1) (4) That is, ΔV _DS is proportional to (V _TGSR −Vth). When the drain current _ID is zero, the drain-source voltage V is determined only by the circuit for charging the true gate and the Miller capacitance.
_Although the curve of _DS is determined, when the drain current _ID flows,
Back electromotive force is generated by the inductance L _C of the entire circuit, and the same effect as when the load resistance is increased is obtained. Therefore, when the drain current _ID is changing, an inductance equivalent resistance is generated, and even when the pure resistance value of the load becomes very small as in the case of dead short, the equivalent impedance of the load is the inductance of the entire circuit. L not decrease below a certain value determined by _C. Therefore, the drain current I
The rising slope of _D falls to a constant value, and the curve of the true gate-source voltage V _TGS also falls.

Reference of semiconductor device (power IC) of the present invention
Ratio of channel width W between semiconductor device QB and main semiconductor device QA
As N2: N1 (n = N1 / N2 = 1000)
In the case of forming a mirror circuit, the main semiconductor element QA
Source voltage V_SAAnd the source voltage V of the reference semiconductor element QB
_SBAre equal, (the drain current I of the main semiconductor element
_DQA) = 1000 × (Drain current of reference semiconductor device)
I_DQB). Therefore, the drain of the main semiconductor element QA
Current as I_DQA= 5A, the reference semiconductor element QB
I as the rain current_DQB= 5mA each flowing
The main semiconductor element QA and the reference semiconductor element QB
Each drain-source voltage V_{D S}Match and follow
The true gate-source voltage V_TGSAlso matches.
That is, V _DSA= V_DSB, V_TGSA= V_TGSBWhen
Become. Where V_DSA, V_{DS B}Is the main semiconductor
The drain-source voltage of the element QA and the reference semiconductor element QB
Pressure and V_TGSA, V_TGSBIs the main semiconductor
Between the true gate and source of element QA and reference semiconductor element QB
Voltage.

Therefore, when the reference semiconductor element QB is completely turned on, it can be approximated that the power supply voltage VB is substantially applied to both ends of the reference resistor Rr. Therefore, as a load of the reference semiconductor element QB equivalent to the load of 5A connected to the main semiconductor element QA, the resistance value of the reference resistor Rr is R
It is determined as r = 12V / 5mA = 2.4 kΩ.

Next, the operation of the semiconductor device (power IC) of the present invention in the pentode characteristic (drain saturation characteristic) region of the MOS transistor will be described. When the main semiconductor element QA transitions to the ON state, the drain current _IDQA rises toward the final load current value determined by the circuit resistance. Also, the true gate of the main semiconductor element QA - source voltage _{V TGSA} takes a value determined by the drain current _{I DQA,} drain - braked by the mirror effect of the capacitance _{C GD} due to a decrease in source voltage _{V DSA} Meanwhile, this also stands up. Further, the reference semiconductor element QB operates as a source follower using the reference resistance Rr as a load resistance according to the gate voltage determined by the main semiconductor element QA.

The true gate-source voltage V _TGSA of the main semiconductor device QA increases as the drain current _IDQA increases.

V _DSA = V _TGSA + V _{TGD ····· (5) V DSB = V} TGSB + V TGD ····· from a relationship of _{(6), V DSA -V DSB} = V TGSA -V TGSB = (I DQA -n × I DQB) / G _m ... (7) However, _{g m} is the ratio of the channel width of the transfer conductance, n = N1 / N2 is the main semiconductor element QA and the reference semiconductor element QB of the main semiconductor element QA. Accordingly, by detecting the difference V _DSA −V _DSB between the drain and source voltages, the difference between the drain currents ( _IDQA− n ×
_IDQB ) can be obtained.

The drain-source voltage V _DSB of the reference semiconductor element QB is input to the “-” input terminal of the comparator CMP1. The value V _{+ obtained} by dividing the voltage _VDSA between the drain and the source of the main semiconductor element QA by the resistor R1 and the resistor R2 is input to the “+” input terminal of the comparator CMP1 via the resistor R5. That is, V ₊ = V _DSA × R1 / (R1 + R2) (8) is input to the “+” input terminal of the comparator CMP1. When the load side is in a normal state, (Rr / n) <R, V ₊ <V _DSB , and the main semiconductor element QA
Maintain ON state. Here, R is the value of the load resistance. When the load side is overloaded, (Rr / n)> R, and the _further, when the V _{+> V DSB,} in triode characteristic region, the main semiconductor element QA is turned off. The respective source potential of the main semiconductor element QA and the reference semiconductor element QB _{V SA,} When _{V SB,} after the main semiconductor element QA is turned off, the source potential _{V SA, V SB,} since decreases towards to GND, the Both V _DSA and V _DSB increase. Before the source potentials V _SA and V _SB reach the GND potential, V
₊ <V _DSB is satisfied, and again the main semiconductor element QA
Turns on. Main semiconductor element QA is, immediately after the transition to the ON state, 5 located in the triode characteristic region, then triode characteristic to continue the on-state towards the (linear characteristic) region, at the V _+> V _DSB off I do. This is,
This is one cycle of the on / off operation. It is due to the inductance of the load circuit that once it is turned off, the off state is maintained, and once it is turned on, the on state is maintained. The inductance of the load circuit acts equivalently to the resistance when the current changes. When the current is decreasing, the sign of the inductance equivalent resistance becomes negative, and the load side resistance is reduced. On the other hand, when the current increases, the sign of the inductance equivalent resistance becomes positive, and the load-side resistance increases. Therefore, once the main semiconductor element QA is turned off, the off state is maintained, and when the main semiconductor element QA is turned on, the on state is maintained. On the reference semiconductor element QB side, since the reference resistance Rr is n = N1 / N2 times larger than the load resistance R, the inductance effect is negligibly small. Therefore, it can be considered that the reference semiconductor element QB operates as a pure resistance circuit.

In the comparator CMP1, the diode D
Hysteresis is formed by 1 and the resistor R5. When the main semiconductor element QA constituting the switching circuit 803 is shifted to the OFF state, the gate potential by the sink transistor in the driver circuit 111 is grounded, the cathode potential of the diode D1 _is, V SA -0.7 V (the Zener diode ZD1 (Forward voltage), so that the diode D1 conducts. As a result, the resistance R1 → the resistance R5 → the diode D
The current flows through the path of No. 1 and the signal level V ₊ of the "+" input terminal of the comparator CMP1 becomes larger than the value of the above-mentioned expression (8) when the drive circuit 111 performs ON control. Therefore, the main semiconductor element QA maintains the off state up to a specific drain-source voltage difference V _DSA −V _{DSB that is} smaller than immediately before the transition to the off state, and thereafter, the main semiconductor element QA further maintains V
_{By DSA} increases, the signal level _{V +} is "+" input terminal of the comparator _CMP1, becomes smaller than _{V DSB,} the output of the comparator CMP1 is changed to "H" level from the "L" level. Accordingly, the main semiconductor element QA is again turned on. It should be noted that there are various methods for attaching the hysteresis characteristic, but this is one example.

[0052] The drain of when the main semiconductor element QA transition to the OFF state - source voltage _{V DS A} threshold V
_{Assuming DSAth} , the following equation holds. That is, V _DSAth −V _DSB = R2 / R1 × V _DSB (9) Equation (9) indicates an overcurrent determination value, and is satisfied in a triode characteristic region (ohmic characteristic region) and a pentode characteristic region (drain saturated region).

Next, the operation in the triode characteristic region will be described. When the main semiconductor element QA included in the switching circuit 803 transitions to the ON state while the load circuit and the power supply system are in a normal state, the main semiconductor element QA continuously maintains the ON state. For this reason, after the true gate-source voltages V _TGSA and V _TGSB reach the pinch-off voltage, the main semiconductor element QA and the reference semiconductor element QB
Operate in the triode characteristic region. In the semiconductor device of the present invention, the reference semiconductor element QB and the main semiconductor element QA
Of the reference semiconductor element QB, the ratio of the channel width W of the reference semiconductor element QB is 1: n.
_{DS (ON) B} is the ON resistance R of the main semiconductor element QA.
N times _{DS (ON) A} (R _{DS (ON) B} = n ·
_{RDS (ON ) A} ). On the other hand, being equal to the source potential of the source potential and the main semiconductor element QA criteria semiconductor element QB, the drain current _{I DQB} of the reference semiconductor element QB is 1 / n times the drain current _{I DQA} main semiconductor element QA ( _{I DQB = (1 / n)} · I D QA). Referring to the typical on-resistance R _{DS (ON)} of the 5A class semiconductor element, for example, the on-resistance R _{DS of} the main semiconductor element QA
_{DS (ON) A is changed} to a gate-source voltage V _GS = 10
At V, it can be assumed that R _{DS (ON) A} = 30 mΩ. n = N1 / N2 = 1000 and the power supply voltage VB =
Assuming that 12 V and the reference resistance Rr = 2.4 kΩ, V _DSB = I _DQB × (n · R _{DS (ON) A} ) = 5 [mA] × 30 [Ω] = 0.15 [V] (10) V _DSA = I _DQA × 30 [mΩ] (11) V _DSA −V _DSB = 30 [mΩ] × (I _DQA −5 [A]) (12) Becomes

When an abnormality occurs in the load and the drain current _IDQA increases, the value of equation (12) increases. When the value exceeds the overcurrent determination value, the main semiconductor element QA constituting the switching circuit 803 is turned off. Transition to. In this case, the state transits to the off state via the pinch-off point, the operation state in the pentode characteristic region described above, and the off state. And FIG.
After a certain period of time has passed, the comparator CMP1 has "+" due to the hysteresis of the diode D1 and the resistor R5 shown in FIG.
The signal level V ₊ of the input terminal becomes smaller than _VDSB ,
The output of the comparator CMP1 changes from the "L" level to the "H" level, and the main semiconductor element QA is turned on again. In this way, the main semiconductor element QA repeats the transition to the ON state and the OFF state, and finally, the overheat cutoff circuit 120 operates to reach the overheat cutoff. Note that if the load circuit and the power supply system return to normal before the overheat interruption (an example of an intermittent short-circuit failure), the main semiconductor element QA keeps on continuously.

FIG. 9A shows the drain current _ID of the semiconductor device (power IC) of the present invention, and FIG. 9B shows the corresponding drain-source voltage _VDS . In the figure,
Is the case of overload, and is the case of normal operation. When the overload state occurs (in the figure), the on / off control of the main semiconductor element QA is repeatedly performed as described above to greatly change the drain current _ID , thereby configuring the switching circuit 803. Due to the periodic heating action of the main semiconductor element QA, the overheating of the main semiconductor element QA is accelerated.

Next, an H-bridge circuit as an embodiment of the present invention will be described with reference to the drawings based on the above description of the power supply control circuit. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals.

(First Embodiment) Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar portions as those in FIG. 6 are denoted by the same or similar reference numerals.

[0058] The semiconductor device having a current oscillation type blocking function according to an embodiment of the present invention, as shown in FIG. 1, the first main electrode terminal DA1 connected to the external input terminal T _1, the first
The second main electrode terminal SA which is connected to an external output terminal T ₃
A first switching circuit 801 of the n-channel type and a 1 and a control electrode terminal GA1, the first main electrode terminal DA2 connected to the external input terminal T _1, the second external output terminal T
An n-channel type second switching circuit 802 having a second main electrode terminal SA2 and a control electrode terminal GA2 connected to the control circuit ₃₃ is provided. First switching circuit 801
Is connected to the first main electrode connected to the first main electrode terminal DA1, the second main electrode connected to the second main electrode terminal SA1, and the control electrode terminal GA1, as shown in FIG. An n-channel first main semiconductor device QA1 having a control electrode and an overheat cutoff circuit 120. Further, the second switching circuit 802 includes a first main electrode connected to the first main electrode terminal DA2, a second main electrode connected to the second main electrode terminal SA2, and a control electrode terminal G.
It comprises an n-channel second main semiconductor element QA2 having a control electrode connected to A2 and an overheat cutoff circuit 120. The semiconductor device according to the embodiment of the present invention further includes an n-channel reference semiconductor element QB having a first main electrode, a control electrode, and a second main electrode. The first main electrode of the reference semiconductor element QB
First main electrode terminal DA1 of switching circuit 801 and first main electrode terminal DA2 of second switching circuit 802
Connected to each other. As a result, the first main electrodes of the reference semiconductor element QB are connected to the first main electrodes of the first main semiconductor element QA1 and the second main semiconductor element QA2, respectively.

[0059] Further, the semiconductor device according to the embodiment of the present invention, the third of the first main electrode connected to the external output terminal T _34, the second main electrodes and a control connected to the ground terminal T ₃₆ and a third main semiconductor element QA3 having an electrode, a first main electrode connected to the fourth external output terminal T _35, and a second main electrode and a control electrode connected to the ground terminal T ₃₆ A fourth main semiconductor element QA4, a first separation diode D33 and a second separation diode D34 each having an anode connected to the second main electrode of the first and second main semiconductor elements, and a first separation diode. A comparator CMP1 having a first input terminal connected to the cathodes of D33 and the second isolation diode D34, and a second input terminal connected to the second main electrode of the reference semiconductor device QB; Q
The first multiplexer MUX1 and the second multiplexer MUX2 connected to the control electrodes of A1 and the second main semiconductor element QA2, respectively, and the first multiplexer MUX1 and the second multiplexer MUX2 according to the output of the comparator CMP1. And a control voltage supply means 111 for supplying a control voltage to the control electrode of the reference semiconductor element QB, respectively.
And a logic circuit 19 connected to respective control electrodes of the third main semiconductor element QA3 and the fourth main semiconductor element QA4.
0 at least.

The first main semiconductor element Q is provided by the first multiplexer MUX1 and the second multiplexer MUX2.
An H-bridge type operation in which either one of A1 and the second main semiconductor element QA2 conducts becomes possible. Further, by connecting the logic circuit 190 to each control electrode of the third main semiconductor element QA3 and the fourth main semiconductor element QA4, the current flowing through the H-bridge circuit does not become out of phase. By detecting the abnormal current of the DC motor M as a load flows through the first external output terminal T ₃ and the second external output terminal T _33, the abnormal current first main semiconductor element QA1 and the second at the time of occurrence One of the main semiconductor elements QA2 is turned on / off to generate a current oscillation, and the current oscillation causes the first to fourth external output terminals T ₃ ,
Interrupting the conduction state between the _{T 33, T 34, T 35} .

The logic circuit 190 connected to the control electrodes of the third main semiconductor element QA3 and the fourth main semiconductor element QA4 includes a resistor R7 connected to the inverter 121.
1, a MOS transistor Q72 having a control electrode connected to the inverter 121, a resistor R72 connected to the inverter 122, and an M transistor having a control electrode connected to the inverter 122.
And an OS transistor Q71.

First, in the H-bridge circuit shown in FIG. 1, in order to rotate the DC motor M in the positive direction, the first multiplexer MUX1 is turned on, and the signal from the drive circuit 111 is turned on. An "H" level signal is applied to the control electrode of the first main semiconductor element QA1. At the same time, the MOS transistor Q71 of the logic circuit 190 is turned off, and an "H" level signal is applied to the control electrode of the fourth main semiconductor element QA4. On the other hand, the second multiplexer MUX2 is in the cutoff state, and the control electrode of the second main electrode terminal SA2 of the second switching circuit 802 is grounded via the resistor R42. At the same time, the MOS transistor Q72 of the logic circuit 190 is turned on, the control electrode of the third main semiconductor element QA3 is grounded,
Set to “L” level. For this reason, the first main semiconductor element Q
A1 and the fourth main semiconductor element QA4 are brought into conduction, and a current flows from the first main semiconductor element QA1 via the DC motor M and further via the fourth main semiconductor element QA4.

On the other hand, to rotate the DC motor M in the reverse direction, the first multiplexer MUX1 is turned off, and the first multiplexer MUX1 is turned off.
The control electrode of the first main semiconductor element QA1 of the switching circuit 801 is grounded via the resistor R43. At the same time, in the logic circuit 190, the MOS transistor Q71 is turned on, and the control electrode of the fourth main semiconductor element QA4 is grounded. Then, the second multiplexer MUX2 is
Into a conductive state, and the second
An “H” level signal is applied to the control electrode of the second main electrode terminal SA2 of the switching circuit 802. At the same time, in the logic circuit 190, the MOS transistor Q72 is turned off, and an "H" level signal is applied to the control electrode of the third main semiconductor element QA3. Therefore, the first main semiconductor element QA1 and the fourth main semiconductor element QA4 are turned off, and the second main semiconductor element QA2 and the third main semiconductor element QA3 are turned on. Therefore, from the second main semiconductor element QA2 via the DC motor M,
A current flows through a path passing through the main semiconductor element QA3.

Next, to stop the rotation of the DC motor M,
What is necessary is just to open both switches SW1 and SW2. When the switches SW1 and SW2 are both opened, the first multiplexer MUX1 and the second multiplexer MUX2
Are both turned off, and the control electrodes of the first main semiconductor element QA1 and the second main electrode terminal SA2 are respectively connected to the resistor R4
3, the first main semiconductor element QA
The first and second main electrode terminals SA2 are turned off, and the supply of current from the DC power supply 101 to the DC motor M is stopped.

As shown in FIG. 1, the semiconductor device having the current oscillation type interrupting function used in the H-bridge circuit of the present invention is as follows.
First switching circuit 801, second switching circuit 8
02, third main semiconductor element QA3, fourth main semiconductor element QA4, reference semiconductor element QB, first isolation diode D
33, a second isolation diode D34, a comparator CMP1,
First multiplexer MUX1, second multiplexer MUX2, control voltage supply means 111, and logic circuit 190
Integrated on the same substrate (Power I
C). The control circuit of the semiconductor integrated circuit (power IC) detects an abnormal current in one of the first switching circuit 801 and the second switching circuit 802, and
When an abnormal current occurs, at least one of the first switching circuit 801 and the second switching circuit 802 is turned on / off.
Off control generates a current oscillation, and by this current oscillation,
The first switching circuit 801 and / or the second switching circuit 802 are shut off.

As the semiconductor integrated circuit board, an insulating substrate such as ceramic or glass epoxy, an insulating metal substrate, or the like can be used. Further, such a hybrid I
In addition to C, a structure of a power IC monolithically integrated on the same semiconductor substrate (same semiconductor chip) is also possible. The structure of a power IC monolithically integrated is more preferable in terms of miniaturization.

First to fourth main semiconductor elements QA1, QA
2, QA3, QA4, for example, a DMOS structure,
A power MOS transistor having a VMOS structure or a UMOS structure or a MOSSIT having a structure similar to these can be used. In addition, the emitter switched thyristor (ES
T), a MOS composite device such as a MOS control thyristor (MCT) or another insulated gate power device such as an IGBT can be used. Furthermore, if the gate is always used with a reverse bias, a junction FET, junction SIT or SI
Thyristors and the like can also be used. First to fourth main semiconductor elements QA1, QA2, QA used for this power IC
3, QA4 may be an n-channel type or a p-channel type. That is, the semiconductor device having the current oscillation type interruption function of the present invention includes both an n-channel type and a p-channel type.

As shown in FIG. 11, the first switching circuit 801 comprises an n-channel first main semiconductor element QA1.
The second switching circuit 802 includes an n-channel type second main semiconductor element QA2 and the overheat cutoff circuit 120.
However, when an on / off number integration circuit (number control means) is provided, the overheat cutoff circuit 120 is not essential.

First to fourth main semiconductor elements QA1, QA
2, QA3 and QA4 may employ, for example, a power device having a multi-channel structure in which a plurality of unit cells (unit cells) are connected in parallel. The reference semiconductor element QB is arranged at a position adjacent to the first and second main semiconductor elements QA1 and QA2 so as to be connected in parallel to the first and second main semiconductor elements QA1 and QA2. Since the reference semiconductor element QB is disposed at an adjacent position in the same process as the main semiconductor elements (main MOS transistors) QA1 and QA2, variations in electrical characteristics due to the influence of temperature drift and non-uniformity between lots. Can be eliminated (reduced). The number of unit cells connected in parallel constituting the reference semiconductor element QB is adjusted such that the current capacity of the reference semiconductor element QB is smaller than the current capacities of the first and second main semiconductor elements QA1 and QA2. For example, for the unit cell number 1 of the reference semiconductor element QB, the first and second
The number of unit cells of the main semiconductor elements QA1 and QA2
With this configuration, the ratio of the channel width W between the reference semiconductor element QB and the first and second main semiconductor elements QA1 and QA2 is set to 1: 1000. The temperature sensor 121 includes a plurality of diodes formed of a polysilicon thin film or the like deposited on an interlayer insulating film formed on the reference semiconductor element QB and the first and second main semiconductor elements QA1 and QA2. Are connected in series, and the temperature sensor 121 is connected to the first and second main semiconductor elements QA1 and QA.
2 is integrated at a position near the channel region.

In FIG. 1, Zener diode ZD1
The overvoltage is applied to the true gate TG of the first and second main semiconductor elements QA1 and QA2 while maintaining the voltage between the gate terminal G and the source terminal S of the first and second main semiconductor elements QA1 and QA2 at 12V. It has a function to bypass this in the case where it is attempted.

Further, outside the semiconductor chip 110, the fifth
Reference resistor Rr1 the connected to the external terminal T ₁₇ is provided for. The resistance value of the reference resistor Rr1 may be selected in consideration of the ratio of the channel width W of the reference semiconductor device QB to the first and second main semiconductor devices QA1 and QA2. For example,
As described above, the ratio of the channel width W between the reference semiconductor device QB and the first and second main semiconductor devices QA1 and QA2 is set to 1:
In the case of 1000, the resistance may be set to be 1000 times the resistance value of the overload state of the H-bridge circuit.
By setting the reference resistor Rr1, H-bridge circuit to the same drain as when the overload current flows in the abnormal operation - source voltage V _DS of the can be generated in the reference semiconductor element QB.

[0072] On the other hand, the first external control electrode terminal _{T 37,} connected switches SW1 and resistor R10, to the second external control electrode terminal _{T 38,} the switch SW2 and the resistor R11 is connected. The semiconductor device having the current oscillation type cutoff function according to the embodiment of the present invention includes:
It functions when a user or the like turns on the switches SW1 and SW2. The output voltage VB of the power supply 101 is, for example, 1
At 2V, the output voltage VP of the charge pump 305 is, for example, VB + 10V.

First and second main semiconductor elements QA1, QA
2 first main electrode (drain electrode) and reference semiconductor element QB
The first main electrode of the (drain electrode) are all connected to the external input terminal T _1, it is maintained at a common potential. A first isolation diode D33 having an anode connected to the second main electrode of each of the first and second main semiconductor elements QA1 and QA2;
The second separation diode D34 is connected to the first separation diode D33 and the cathode of the second separation diode D34. The middle point (connection point) of the series circuit of the resistors R1 and R2 is connected to the cathodes of the first separation diode D33 and the second separation diode D34. That is, the first and second main semiconductor elements QA1 and QA2 are separated from each other by the first and second isolation diodes D33 and D34.
Is connected to a series circuit of resistors R1 and R2. As a result, a series circuit of the resistors R1 and R2 is connected between the first main electrode (drain electrode) and the second main electrode (source electrode) of the first and second main semiconductor elements QA1 and QA2. . The first or second main semiconductor element QA is connected to the “+” input terminal of the comparator CMP1 shown in FIG.
A voltage obtained by dividing the voltage VDS between the main electrodes (voltage between drain D and source S) of _QA1 by the resistors R1 and R2 is supplied through the resistor R5. The source voltage VS of the MOS transistor (reference semiconductor element) QB is supplied to the "-" input terminal of the comparator CMP1. The "-" input terminal of the comparator CMP1 is connected to the reference semiconductor element Q
A source voltage _{VSB of} B is supplied. "+" Signal level at the input terminal _V +>"-" signal level at the input terminal V _-
, The output of the comparator CMP1 becomes “H” level,
The drive circuit 111 includes a first main semiconductor element QA1 forming the first switching circuit 801 or a second main semiconductor element QA forming the second switching circuit 802.
A voltage is supplied to the second gate electrode. In the opposite case, the output of the comparator CMP1 becomes “L” level, and the driving circuit 111
Turns off the gate drive of the first switching circuit 801 or the second switching circuit 802.

Between the drain and source of the reference semiconductor element QB
Voltage V_DSBIs directly connected to the "-" input terminal of the comparator CMP1.
Input to the first or second main semiconductor element QA1, QA2
Drain-source voltage V_DSAAre the resistors R1 and R
The value divided by 2 is input to the "+" input terminal of comparator CMP1.
Is forced. That is, the variable resistor RV is not taken into account.
Assuming that V is given by equation (8)₊Is a comparator CM
This is input to the "+" input terminal of P1. First
Indicates that the second main semiconductor elements QA1 and QA2 transition to the ON state.
Immediately after that, “+” input of the comparator CMP1 is performed by the equation (8).
Potential V of force terminal ₊Is determined, the reference semiconductor element Q
B drain-source voltage V_DSB> V₊It is. I
However, the gate of the first or second main semiconductor element QA1, QA2
Rain current I_DQAAs equation (8) increases,
V given₊Increases, and finally the reference semiconductor device QB
Drain-source voltage V_DSBLarger
, The output of the comparator CMP1 changes from “H” level to “L” level.
Change to the level, either the first or second main half
Conductive elements QA1 and QA2 are turned off. Soshi
Thus, the diode D1 and the resistor R5 shown in FIG.
After a certain period of time, the comparator CM
The potential V of the "+" input terminal of P1₊Decrease, so compare
The output of the CMP1 changes from “L” level to “H” level.
Into the first or second main semiconductor element QA1, QA2.
The transition to the ON state is made again. Thus, the first
Alternatively, the second main semiconductor elements QA1 and QA2 are turned on and
The transition to the off state is repeated until the first or
2 main semiconductor elements QA1 and QA2 are overheated.

(Modifications of Embodiments) It should not be understood that the description and drawings constituting a part of the disclosure of the above embodiments limit the present invention. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.

For example, as shown in FIG. 5, a second reference semiconductor element QC connected to the second reference resistor Rr2 is added to provide a more advanced function capable of undercurrent measurement, lamp disconnection detection, and open detection. It is possible to realize a simple semiconductor device. Also, an overcurrent detection unit 301 is provided in the semiconductor chip 110.
In addition, a current enable (Enable) unit 302, an inrush current masking circuit 303, an on / off number integration circuit (number control means) 304, a cutoff latch circuit 306, and the like can be added to further enhance the functions.

Hereinafter, modified examples of the present invention will be described.

<First Modification> For example, in the above-described embodiment, the on / off frequency integrating circuit 30 as shown in FIG.
4 is connected to the nodes N51, N52, N53 of FIGS. 1 and 11, and the first and second main semiconductor elements QA1, QA as the first and second main semiconductor elements in the case of incomplete short circuit.
2 can be quickened. That is, when the number of times of on / off control of the first and second main semiconductor elements QA1 and QA2 reaches a predetermined number, the first and second main semiconductors are turned on by the on / off number integration circuit (number control means) 304. Element Q
The operation of turning off A1 and QA2 can be performed.

As shown in FIG. 2, the on / off frequency integrating circuit 304 includes resistors R131 and R132 connected to the node N51 shown in FIG. 11 and a node N52 shown in FIG.
C131 connected to the node N5 in FIG.
1, a diode D132, a MOS transistor Q131, a backflow preventing diode D131 and a resistor R
133 is provided.

In the overcurrent control, each time the gate potentials of the first and second main semiconductor elements QA1 and QA2 periodically go to "H" level, the capacitor C131 is connected via the resistor R132 and the backflow prevention diode D131. Charged. M
Since the gate potential of the OS transistor Q131 is initially lower than the threshold value, it is in the off state. However, when the gate potential increases with the charging of the capacitor C131, the MOS transistor Q131 transitions to the on state. When the MOS transistor Q131 transitions to the ON state, the node N51 on the anode side of the temperature sensor 121 shown in FIG. 11 is pulled down, so that the same condition as in the high temperature state is satisfied, and the overheat cutoff element QS transitions to the ON state. The first and second main semiconductor elements QA1 and QA2 are shut off.

<Second Modification> The nodes N53 and N53 in FIG.
The overheat cutoff promotion circuit 106 shown in FIG. 3 may be connected to N62 to speed up the cutoff of the first and second main semiconductor elements QA1 and QA2. That is, in the case of an overcomplete short circuit, the on / off control of the first and second main semiconductor elements QA1 and QA2 is repeatedly performed to periodically generate heat of the first and second main semiconductor elements QA1 and QA2. When the overheat cutoff is caused to function by the action, the time until the overheat cutoff may be relatively long. In such a case, the first overheat cut-off promotion circuit (overheat cut-off promotion means) 106
In addition, the cutoff of the second main semiconductor elements QA1 and QA2 may be accelerated.

As shown in FIG. 3, the overheat cutoff promotion circuit 106
Is a MOS transistor Q221, a diode D22
1, a resistor R221 to R223 and a capacitor C221. In the overcurrent control, each time the gate potential of the first or second main semiconductor element QA1 or QA2 periodically goes to the “H” level, the capacitor C221 sets the resistance R
The battery is charged via the diode 222 and the backflow prevention diode D221. Since the gate potential of the MOS transistor Q221 is initially lower than the threshold value, the MOS transistor Q221 is in an off state.
Transistor Q221 transitions to an on state. Resistance R2
A current flows from the terminal TG (the true gate of the first or second main semiconductor element QA1 or QA2) located at the node N62 to the ground potential (GND) via the node 21 and is accumulated at the terminal TG (node N62). The charge is reduced. Therefore, also a drain for the same drain current I _D - source voltage V _{D SA} is increased, first and second main semiconductor elements Q
The power consumption of A1 and QA2 increases, and the overheating cutoff is accelerated. Note that the smaller the resistance R221, the earlier the overheat cutoff. Further, the resistor R223 is a discharge resistor of the capacitor C221, and is desirably set so that R222≪R223.

<Third Modification> Inrush current mask circuit 303 shown in FIG. 4 may be connected to nodes N52, N53, N71. The inrush current mask circuit 303 includes MOS transistors Q311 and Q312 connected to the node N71, a diode D311 connected to the node N53, and a node N31.
52, a resistor R313, a capacitor C311 and resistors R311 and R312 are connected. In the rush current mask circuit 303, when the first or second main semiconductor element QA1, QA2 transitions to the ON state,
Gate - source voltage _{V GSA} is supplied to the gate of the MOS transistor Q312 through a diode D311 and a resistor R312, also similarly gate - source voltage _{V G
SA} is connected to M via a diode D311 and a resistor R311.
It is supplied to the gate of the OS transistor Q311. MO
The gate of the S transistor Q312 is connected to the capacitor C311.
Is connected to the source SA (node N52) of the first and second main semiconductor elements QA1 and QA2 via a capacitor C311 immediately after the first or second main semiconductor element QA1 or QA2 transitions to the ON state. Is not charged, M
Since the gate potential of the OS transistor Q312 does not rise sufficiently, the MOS transistor Q312 cannot transition to the ON state. The MOS transistor Q311 is on while the MOS transistor Q312 is off, and the voltage dividing point supplied to the + terminal (node N71) of the comparator CMP1 is determined by the first and second main semiconductor elements QA1, Q2. It is coupled to the source SA of QA2 (node N52). Therefore, the output of the comparator CMP1 is kept at the “H” level, and the first and second main semiconductor elements QA are output even when a large inrush current flows.
1, QA2 will not transition to the off state.

As time passes, the capacitor C311 is charged via the resistor R312, and finally the MOS transistor C311 is charged.
Transistor Q312 transitions to the on state. Accordingly, the mask state in which the MOS transistor Q311 has transitioned to the off state ends, and the overcurrent detection control functions. Note that the resistor R313 is a discharge resistor for resetting the capacitor C311 after the first or second main semiconductor element QA1, QA2 transitions to the off state. R
It is desirable to set 312≪R313 so as not to affect the mask time. The mask time is R
Since it is determined by the time constant of 312 × C311, the mask time can be adjusted by arbitrarily changing the capacitance value of the external capacitor C311 in the case of one chip.

In the embodiment of the present invention, when the DC motor M serving as a load of the H-bridge circuit is turned on, an inrush current several times to several tens times that of the stable state is generated by the first or second main semiconductor element QA1, Flow to QA2. The period during which the rush current flows varies depending on the type and capacity (size) of the DC motor M serving as the load of the H-bridge circuit, and is approximately 3 msec to 20 msec. If the overcurrent control as described in the embodiment is performed during the period when the inrush current flows, it takes time for the DC motor M serving as the load of the H-bridge circuit to reach a steady state. If the start of the driving of the DC motor, which is a load, becomes poor, problems such as a delay in starting the operation of the wiper and the power window occur. Such a problem can be solved by adding the inrush current mask circuit 303 shown in FIG. 4 to the configuration of FIG.

As described above, the present invention naturally includes various embodiments and the like not described herein. Therefore, the technical scope of the present invention is determined only by the invention specifying matters according to the claims that are appropriate from the above description.

[0087]

According to the power supply control device of the present invention, H
Even when used in a bridge circuit, the conventional shunt resistor is unnecessary, and not only overcurrent due to a complete short circuit,
It is also possible to easily and accurately detect an abnormal current when a rare short circuit such as an incomplete short circuit having a certain short-circuit resistance occurs.

Further, according to the semiconductor device of the present invention, the heat loss of the power supply control device is suppressed by eliminating the need for the conventional shunt resistor. An abnormal current when a rare short circuit such as a short circuit occurs can be detected easily and accurately.

Further, since a microcomputer is not required, especially in the case of a power IC structure in which the control circuit section of the main semiconductor element is monolithically integrated on the same semiconductor substrate, the area of the semiconductor chip can be reduced and H The cost of the bridge type power supply control device can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of an on / off frequency integration circuit used in a semiconductor device according to a first modification of the present invention.

FIG. 3 is a circuit configuration diagram of an overheat cutoff promotion circuit used in a semiconductor device according to a second modification of the present invention.

FIG. 4 is a circuit configuration diagram of an inrush current mask circuit used in a semiconductor device according to a third modification of the present invention.

FIG. 5 is a circuit configuration diagram of another power supply control device of the present invention.

FIG. 6 is a configuration diagram of a power supply control circuit on which the present invention is based.

FIG. 7 is an explanatory diagram illustrating a principle used by the semiconductor device according to the embodiment of the present invention, and is an explanatory diagram of a fall characteristic of a drain-source voltage at the time of transition from an off state to an on state. .

FIG. 8 is a conceptual equivalent circuit diagram focusing on main semiconductor elements (first and second main semiconductor elements) of the semiconductor device according to the embodiment of the present invention;

FIG. 9A is a graph showing a transient response characteristic of a drain current of a main semiconductor element (first and second main semiconductor elements) in a semiconductor device according to an embodiment of the present invention; )
FIG. 3 is an explanatory diagram showing a transient response characteristic of a corresponding drain-source voltage.

FIG. 10 is a circuit configuration diagram of a conventional semiconductor switch.

FIG. 11 is an example of a circuit configuration diagram showing details of a switching circuit of the present invention.

[Explanation of symbols]

Reference Signs List 101 power supply 102, 103 load 106 overheat cutoff promotion circuit (overheat cutoff promotion means) 110 semiconductor chip 111 drive circuit (control means) 120 overheat cutoff circuit 121, 122 inverter 190 logic circuit 301 overcurrent detection section 302 current enable section 303 inrush current Masking circuit (prohibiting means) 304 ON / OFF count integration circuit (count control means 9 305 Charge pump section 306 Cutoff latch circuit 801 First switching circuit 802 Second switching circuit 803 Switching circuit C131, C221, C311 Capacitors CMP1, CMP411 Comparator D1, D71, D72, D131, D132, D22
1, D311 Diode D33, D34 Separation diode QA1 First main semiconductor element QA2 Second main semiconductor element QF Transistor with built-in temperature sensor QB MOS transistor (reference semiconductor element) QC MOS transistor (second reference semiconductor element) Q71, Q72 , Q131, Q221, Q311, Q3
12 MOS transistor RG Internal resistance R1, R2, R5, R131 to R133, R221 to R
223, R311 to R313, R331, R412, R
413 resistance Rr1 reference resistor (first reference resistance) Rr2 second reference resistor _{T 1, T 2, T 3} , T 17, T 18, T 33 ~T 38
Input / output terminal ZD1 Zener diode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H02P 1/22 H01L 27/08 102J H03K 17/08 H03K 17/687 E 17/687

Claims (3)

[Claims] A first switching circuit having a first main semiconductor element built therein and having a first main electrode terminal, a second main electrode terminal connected to a first terminal of a load, and a control electrode terminal; A second switching circuit incorporating a second main semiconductor element and having a first main electrode terminal, a second main electrode terminal connected to a second terminal of the load, and a control electrode terminal; A third main semiconductor element having a first main electrode, a second main electrode, and a control electrode connected to a first terminal; a first main electrode connected to the second terminal of the load; A fourth main semiconductor element having two main electrodes and a control electrode; a first main electrode respectively connected to the first main electrodes of the first and second main semiconductor elements; a control electrode and a reference resistance; A reference semiconductor device having a second main electrode connected to the first and second main electrodes; A first and a second isolation diode, each having an anode connected to a second main electrode of the main semiconductor element, and a first input terminal connected to the cathodes of the first and second isolation diodes, A comparator in which a second input terminal is connected to a second main electrode of the element; first and second multiplexers respectively connected to control electrodes of the first and second main semiconductor elements; Control voltage supply means for supplying a control voltage to each of the first and second multiplexers and the control electrode of the reference semiconductor element according to an output; and a control voltage supply means for each of the third and fourth main semiconductor elements. An abnormal current flowing through the first and second main semiconductor elements, and detecting one of the first and second main semiconductor elements when an abnormal current occurs On / off control to generate a current oscillation by the current oscillation, the power supply control apparatus characterized by blocking either the conduction state of the first and second main semiconductor elements. A first main electrode terminal connected to the external input terminal, a second main electrode terminal connected to the first external output terminal, and a control electrode terminal. A first switching circuit, a first main electrode terminal having a second main semiconductor element built therein and connected to the external input terminal, a second main electrode terminal and a control electrode terminal connected to the second external output terminal, A third main semiconductor element having a first main electrode connected to a third external output terminal, a second main electrode connected to a ground terminal, and a control electrode; A fourth main semiconductor element having a first main electrode connected to an external output terminal, a second main electrode connected to a ground terminal, and a control electrode; and a first main semiconductor element of the first and second main semiconductor elements. A first main electrode respectively connected to the main electrode, a control electrode and A reference semiconductor element having a second main electrode connected to the counter terminal; first and second isolation diodes each having an anode connected to the second main electrode of the first and second main semiconductor elements; A comparator having a first input terminal connected to the cathodes of the first and second isolation diodes, and a second input terminal connected to a second main electrode of the reference semiconductor device; First and second multiplexers respectively connected to the control electrodes of the main semiconductor element, and control voltages respectively applied to the control electrodes of the first and second multiplexers and the reference semiconductor element according to the output of the comparator. At least a control voltage supply means for supplying, and a logic circuit connected to each control electrode of the third and fourth main semiconductor elements, respectively connected to the first and second external output terminals. An abnormal current flowing through the first and second loads is detected, and when an abnormal current occurs, one of the first and second main semiconductor elements is turned on / off to generate a current oscillation. Wherein a conduction state between one of the external input terminal and the first and second external output terminals is cut off. 3. The first and second switching circuits, the third and fourth main semiconductor devices, the reference semiconductor device, the first and second isolation diodes, the comparator, the first and second devices. 3. The semiconductor device according to claim 2, wherein the multiplexer, the control voltage supply means, and the logic circuit are integrated on the same semiconductor substrate.