JP2000299622A - Noise suppression system for digital filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a noise suppression system for a digital filter capable of suppressing noises generated when inputting small data to a digital filter having a feedback loop. SOLUTION: A delay part 205 in an IIR digital filter 200 stores the high-order bits of data outputted from an adding part 204. A peak value detecting part 110 detects the peak value of the input data and corresponding to this peak value, a gain setting part 120 sets a multiplication value c0 of a multiplying part 130 and sets a multiplication value c1 of a multiplying part 140 to the inverse of the multiplication value c0. The multiplying part 130 multiplies the multiplication value c0 to the input data and outputs these data to the IIR digital filter 200 and the multiplying part 140 multiplies the multiplication value c1 to the data outputted from the IIR digital filter 200 and outputs the data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a digital filter noise suppression system for suppressing noise generated when a digital filter operates.

[0002]

2. Description of the Related Art Recently, with the spread of various devices for performing digital signal processing, such as a compact disk player and a digital versatile disk player, a large number of digital filters have been used. Since this digital filter can be integrated into a circuit, it can be made smaller, less expensive, and more reliable, and can have its filter characteristics easily adjusted by software processing. It has many advantages in comparison.

FIG. 4 is a diagram showing a configuration of a digital filter. The digital filter shown in FIG.
(Infinite Impulse Response) type digital filter, for example, a digital signal processor (DSP: Di
gital Signal Processor).

[0004] This IIR type digital filter 500 includes:
A delay unit 501 for delaying data input at a predetermined cycle by a time corresponding to the cycle, a multiplication unit 502 for multiplying input data by a filter coefficient b0, and a filter coefficient for delay data output from the delay unit 501 a multiplication unit 503 for multiplying b1; and an addition unit 5 for adding data output from the multiplication units 502 and 503 and a multiplication unit 506 described later.
04, a delay unit 505 for delaying data output from the addition unit 504 by a time corresponding to the data input period, and a multiplication unit 506 for multiplying the data output from the delay unit 505 by a filter coefficient a1. Have been. A feedback loop is formed by the addition unit 504, the delay unit 505, and the multiplication unit 506.

The above-mentioned IIR type digital filter 500
Then, the delay unit 505 is realized by, for example, storing data in a memory in the DSP. Therefore, the maximum value of the bit length (storable bit length) of the data that can be stored at one time in the delay unit 505 is a unique value depending on the DSP. Therefore, when the bit length of the input data is longer than the storable bit length of the delay unit 505, the delay unit 505 cannot store all the bits of the input data at one time.

In such a case, a first method is employed in which data to be stored in the delay unit 505 is divided into upper bits and lower bits, and each divided data is stored in a separate area of a memory. In this case, since the number of steps of the operation program corresponding to the operation of the delay unit 505 increases, for example, when processing of each divided band of the vehicle-mounted graphic equalizer is performed using a digital filter, When many digital filters are used, the total number of operation steps becomes enormous, which is not preferable. For this reason, the second method of storing a predetermined upper bit length of input data in the delay unit 505 and discarding other lower bits is often used.

[0007]

By the way, if lower bits are discarded when storing data in the delay section 505 included in the above-described feedback loop, limit cycle oscillation occurs, and an analog-to-digital converter or the like is used. There is a problem that noise is generated when no input is made in such a case. For example, even if a small signal whose output value becomes 0 when multiplied by the filter coefficient b1 or the like is input, the output value is fixed to a small value. At this time, when a predetermined value is input, the output may suddenly become a large value, which becomes noise. In particular, if the lower bits are truncated for negative data, the value increases and the above-described noise increases.

[0008] The present invention has been made in view of the above points, and an object of the present invention is to provide a digital filter having a feedback loop capable of suppressing noise generated when minute data is input. An object of the present invention is to provide a filter noise suppression method.

[0009]

In order to solve the above-described problems, a digital filter noise suppression method according to the present invention multiplies predetermined digital data by a first multiplication value corresponding to a peak value thereof. Then, the data is input to a digital filter having a feedback loop, and data output from the digital filter is multiplied by a second multiplied value corresponding to the first multiplied value. By multiplying the input data by a first multiplication value corresponding to the peak value of the input data, it is possible to prevent extremely small data from being input to the digital filter. Can be suppressed.

More specifically, the digital filter noise suppression system of the present invention is connected to a stage preceding a digital filter having a feedback loop, and multiplies input predetermined digital data by a first multiplication value and outputs the result. First multiplying means, a second multiplying means connected to the subsequent stage of the digital filter and multiplying digital data output from the digital filter by a second multiplied value and outputting the multiplied value, and input to the first multiplying means. A first multiplication value according to the peak value detected by the peak value detection means, and a second multiplication value according to the peak value detected by the peak value detection means, and a second multiplication value according to the first multiplication value. And a multiplication value setting means for setting a multiplication value. By setting the first multiplied value and the second multiplied value to appropriate values, noise generated by a digital filter having a feedback loop is suppressed.

In particular, the digital filter described above is a recursive filter having a data storage means for truncating and storing predetermined lower bits in a feedback loop, and is used when input data having a small value is stored in the data storage means. By preventing the feedback data output from the data storage means from being truncated to 0, the noise generated in the digital filter can be suppressed.

It is desirable that the second multiplication value set by the multiplication value setting means be a value proportional to the reciprocal of the first multiplication value. Thus, even when the first multiplied value changes, the overall gain determined by the first multiplied value and the second multiplied value can be made substantially constant.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a noise suppression system according to an embodiment to which a digital filter noise suppression system of the present invention is applied will be described with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a noise suppression system according to the present embodiment. The noise suppression system 100 shown in FIG. 1 is for suppressing noise generated when the primary IIR digital filter 200 operates.

First, an IIR digital filter 200 to be subjected to noise suppression by the noise suppression system 100
Will be described. The IIR digital filter 200 shown in FIG. 1 includes delay units 201 and 205, a multiplication unit 202,
03, 206, and an adder 204, and are realized by a DSP. Then, the addition unit 204 and the delay unit 20
5. A feedback loop is formed by the multiplication unit 206.

The delay unit 201 delays data input to the IIR type digital filter 200 at a predetermined period by a time corresponding to the period, and is realized by storing the data in a memory in the DSP. Therefore, the maximum value of the bit length of data that can be stored at one time in the delay unit 201 is a unique value depending on the DSP. The multiplication unit 202 multiplies the data input to the IIR digital filter 200 by a filter coefficient b0. Similarly, the multiplication unit 203 multiplies the delay data output from the delay unit 201 by the filter coefficient b1. The adder 204 adds data output from the multipliers 202 and 203 and a multiplier 206 described later.

The delay section 205 is provided with a predetermined period,
4 is delayed by the cycle time, and is realized by storing the data in a memory in the DSP. Therefore, the maximum value of the data bit length that can be stored in the delay unit 205 is also a unique value depending on the DSP. The delay units 201 and 205 store only a predetermined number of high-order bits in the input data, and discard the lower-order bit data without storing them.
For example, the bit length of the input data and the bit length of the operation in the adding section 205 are set to 40, the delay section 201 sets the upper 24 bits of the input data, and the delay section 205 sets the adding section 204
The upper 24 bits of the addition result data output from are stored. The multiplication unit 206 multiplies the delay data output from the delay unit 205 by a filter coefficient a1.

Here, the IIR type digital filter 200
Is the input of x [n] and the output is y [n], the difference equation showing the input / output relationship is:

[0019]

(Equation 1) And the transfer function H (z) is

[0020]

(Equation 2) Becomes

The above-described IIR type digital filter 200
Operates as a low-pass filter (LPF) or a high-pass filter (HPF) by setting each of the filter coefficients a1, b0, and b1 to a predetermined value.

Next, the noise suppression system 100 of the present embodiment combined with the IIR type digital filter 200
Will be described. As shown in FIG. 1, the noise suppression system 100 includes a peak value detection unit 110, a gain setting unit 1
20 and multiplication units 130 and 140.
The noise suppression system 100 and the IIR type digital filter 200 are realized by a single DSP.

The peak value detection section 110 detects a peak value of data (input data) input to the noise suppression system 100, and outputs a signal indicating the peak value to the gain setting section 120.

The gain setting section 120 sets a multiplication value c0 of one of the multiplication sections 130 and a multiplication value c1 of the multiplication section 140 connected to the preceding stage of the IIR digital filter 200 according to the peak value of the input data. Specifically, the gain setting unit 120 sets the multiplication value c0 of the multiplication unit 130 to a large value when the peak value of the input data is small, and conversely, sets the multiplication unit 13 when the peak value of the input data is large.
The multiplication value c0 of 0 is set to a small value. For example, the multiplication value c0 of the multiplication unit 130 is variably set in the range of 1 to 4 according to the magnitude of the peak value of the input data. Further, the gain setting unit 120 sets the multiplication value c1 of the other multiplication unit 140 connected to the subsequent stage of the IIR digital filter 200 to a reciprocal value of the multiplication value c0 of the one multiplication unit 130 described above.

The multiplication unit 130 multiplies the input data by the multiplication value c0 set by the gain setting unit 120. When the peak value of the input data is small, the multiplication unit 1
30 is multiplied by a large value. Conversely, when the peak value is large, a small value is multiplied. Therefore, input data having a substantially constant value is input to the IIR digital filter 200. The multiplication unit 140 multiplies the data output from the IIR digital filter 200 by the multiplication value c1 set by the gain setting unit 120. As described above, the multiplication value c1 of the multiplication unit 140
Is set to the reciprocal value of the multiplication value c0 of the multiplication unit 130 connected in front of the IIR digital filter 200, so that there is no fluctuation in the gain when passing through these two multiplication units 130 and 140. The gain characteristic of the noise suppression system 100 becomes substantially flat.

For example, it is assumed that data having a bit length of 40 bits is input, and only the upper 24 bits of the 40-bit data output from the adding section 204 are stored in the delay section 205.

The multiplier 130 described above serves as a first multiplier, the multiplier 140 serves as a second multiplier, the peak value detector 110 serves as a peak value detector, the gain setting unit 120 serves as a multiplier, and the like. Delay unit 2 in IIR filter 200
05 corresponds to the data storage means.

Next, the operation of the noise suppression system 100 will be described. FIG. 2 is a flowchart showing an operation procedure of the noise suppression system 100. When data is input to the noise suppression system 100, the peak value detection unit 110 detects a peak value of the input data, and outputs a signal indicating the peak value to the gain setting unit 120 (Step 100).

Next, the gain setting section 120 responds to the signal indicating the peak value by using the IIR digital filter 20.
The multiplication value c0 of the multiplication unit 130 connected to the preceding stage of the IIR digital filter 200 is set to a predetermined value of 1 or more as long as an overflow does not occur in the operation of the addition unit 204 within 0 (step 101). Further, the gain setting unit 120 sets the multiplication value c1 of the multiplication unit 140 connected to the subsequent stage of the IIR digital filter 200 to a reciprocal value of the multiplication value c0 of the multiplication unit 130 (step 102).

Next, the multiplication unit 130 multiplies the input data by the set multiplication value c0 and outputs the result to the IIR digital filter 200 (step 103). Multiplication unit 140
Multiplies the data output from the IIR digital filter 200 by the set multiplication value c1 (step 10).
4).

Thereafter, the operations after the peak detection of the input data (step 100) are repeated again. That is, the noise suppression system 100 operates to update the multiplication values of the multiplication units 130 and 140 according to the peak value of the input data.

As described above, in the noise suppression system 100, the peak value of the input data is detected by the peak value detection unit 110, and the multiplication value of the multiplication unit 130 is determined by the gain setting unit 120 in accordance with the peak value. While setting c0, the multiplication value c1 of the multiplication unit 140 is set to the reciprocal of the multiplication value c0. By multiplying the input data by the multiplication value c0, the IIR digital filter 200
It is possible to prevent the data output from the delay unit 205 from becoming 0 due to the bit truncation in the delay unit 205, and suppress noise generated when minute data is input. Further, since the multiplied value c0 of the multiplying unit 130 is set according to the peak value of the input data, the multiplied value c0 is set within a range where overflow does not occur in the operation of the IIR digital filter 200.
Can be set to an appropriate value. The multiplication unit 14
Since the multiplied value c1 of 0 is set to the reciprocal of the multiplied value c0 of the multiplying unit 130, a change caused by the fluctuation of the multiplied value c0 can be removed from the data output by the IIR digital filter 200, and the flattening can be performed. Thus, the effect of adding the noise suppression system 100 can be eliminated. Furthermore, since the noise suppression system 100 and the IIR digital filter 200 are realized by a program processing by a single DSP, the noise suppression system can be realized by adding only a few processing steps, and the processing load is reduced. The increase can be suppressed as much as possible.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. For example, in the embodiment described above, the primary IIR digital filter 200 is targeted for noise suppression, but noise can be similarly suppressed for other IIR digital filters.

FIG. 3 is a diagram showing a configuration in which the noise suppression system 100 is connected to a second-order IIR digital filter. For example, in a 7-band graphic equalizer for vehicle use, this second-order IIR type digital filter 300 has 14
Are used.

This IIR type digital filter 300 has
A delay unit 301 for delaying data input at a predetermined cycle by a time corresponding to the cycle, and a delay unit 301 at a predetermined cycle
A delay unit 302 that further delays the data output from the delay unit by the same time, a multiplication unit 303 that multiplies the input data by the filter coefficient b0, and a multiplication unit 304 that multiplies the data output from the delay unit 301 by the filter coefficient b1 A multiplication unit 305 for multiplying the data output from the delay unit 302 by the filter coefficient b2, and multiplication units 303, 304, and 305
And an adder 306 for adding data output from multipliers 309 and 310 described later, and an adder 3 at a predetermined cycle.
06, a delay unit 307 for delaying the data output from the delay unit 307 by the time corresponding to the cycle, a delay unit 308 for further delaying the data output from the delay unit 307 by the same time, and a filter for filtering the data output from the delay unit 307. The multiplication unit 309 includes a multiplication unit 309 that multiplies a coefficient a1 and a multiplication unit 310 that multiplies data output from the delay unit 308 by a filter coefficient a2. The IIR digital filter 300 includes an adder 306, a delay 307, and a multiplier 309.
And a feedback loop formed by the addition unit 306, the delay unit 308, and the multiplication unit 310.

The operation when the noise suppression system 100 is used for the IIR type digital filter 300 is as follows.
Basically, the IIR digital filter 20 shown in FIG.
The operation is the same as when the noise suppression system 100 is used for 0. That is, the peak value detection unit 110 detects the peak value of the input data, the gain setting unit 120 sets the multiplication value c0 of the multiplication unit 130 according to the peak value, and sets the multiplication value c1 of the multiplication unit 140. Is set to the reciprocal of the multiplication value c0, so that IIR
Noise caused by lower bit truncation in the delay units 307 and 308 in the type digital filter 300 can be suppressed.

In the above-described embodiment, the multiplication unit 14
Although the multiplied value c1 of 0 is set as the reciprocal of the multiplied value c0 of the multiplying unit 130, a value proportional to the reciprocal of the multiplied value c0 (multiplied by a predetermined value) may be used as the multiplied value c1. In this case, the entire noise suppression system 100 has a predetermined gain. However, the noise suppression system 100 still has a flat gain characteristic.
0 has the effect of suppressing the generation of noise.

In the above-described embodiment, the noise suppression system 100 and the IIR digital filter 200 are realized by a single DSP. However, the noise suppression system 100 and the IIR digital filter 200 are realized by separate DSPs. It may be realized. Further, the noise suppression system 100 or the IIR type digital filter 200 may be realized by a processor other than the DSP.

[0039]

As described above, according to the present invention, extremely small data is input to the digital filter by multiplying the input data by the first multiplication value corresponding to the peak value of the input data. Therefore, it is possible to suppress noise generated when the input data becomes small.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a noise suppression system according to an embodiment.

FIG. 2 is a flowchart showing an operation procedure of the noise suppression system.

FIG. 3 is a diagram illustrating a configuration in which a noise suppression system is connected to a secondary IIR digital filter.

FIG. 4 is a diagram showing a configuration of a first-order IIR digital filter.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 noise suppression system 110 peak value detection unit 120 gain setting unit 130, 140 multiplication unit 200 IIR digital filter

Claims (4)

[Claims] 1. A method in which predetermined digital data is multiplied by a first multiplication value corresponding to a peak value of the multiplied digital data and input to a digital filter having a feedback loop. , Multiplying the first multiplied value by a second multiplied value corresponding to the first multiplied value. 2. A first multiplying means connected to a preceding stage of a digital filter having a feedback loop and multiplying input predetermined digital data by a first multiplied value and outputting the result, and connected to a succeeding stage of the digital filter. A second multiplication means for multiplying the digital data output from the digital filter by a second multiplication value and outputting the multiplied value; and a peak value for detecting a peak value of the digital data input to the first multiplication means. Detecting means for setting the first multiplied value according to a peak value detected by the peak value detecting means, and setting the second multiplied value according to the first multiplied value And a noise suppression method for a digital filter. 3. The digital filter noise suppression method according to claim 2, wherein the digital filter is a recursive filter including data storage means for truncating and storing predetermined lower bits in the feedback loop. . 4. The noise of a digital filter according to claim 2, wherein said multiplied value setting means sets said second multiplied value to a value proportional to the reciprocal of said first multiplied value. Suppression method.