JP2000299460A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a U-MOS gate insulating film, the gate breakdown voltage of which is not lowered, without increasing the number of steps by preventing the thickness of the insulating film at the corner sections of trenches from becoming thinner than that in the sidewall sections of the trenches. SOLUTION: A method for manufacturing a semiconductor device includes a step of forming an insulating film 32, which becomes a gate insulating film on the side faces of trenches and on the surface of a substrate, a step of depositing polysilicon films 33 which become gate electrodes on the insulating film 32, and a step of removing the polysilicon films 33 by selectively leaving the portions of the film 33 to be wider than the openings of the trenches in the trenches and upper parts of the trenches. The method also includes a step of removing the insulating film 32 in regions, from which the polysilicon films 33 were removed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device having a vertical field effect transistor (U-MOS) using a trench gate electrode and a control circuit such as a C-MOS.

[0002]

2. Description of the Related Art A method of manufacturing a U-MOS as a power device and a C-MOS as a control circuit thereof is described in the following (1).
To (6). (1) UM
An OS trench is formed. (2) The first to be a U-MOS gate insulating film on the side surfaces of the trench and the entire surface of the substrate.
Is formed. (3) Deposit polysilicon on the first silicon oxide film to be a U-MOS gate electrode. (4) Etch back polysilicon to form a trench gate electrode. (5) The silicon oxide film on the surface of the substrate is removed by etching. At this time, since the corner of the side wall silicon oxide film is etched from both the front side and the side surface, the etching progresses quickly, and the silicon oxide film at the corner is etched deeper than the substrate surface. (6) Next, a second silicon oxide film to be a gate insulating film of the C-MOS is formed.

[0003]

However, in the above-described manufacturing method, the silicon oxide film at the corner of the trench is thinner than the silicon oxide film originally required. Will go down. In order to avoid this, it is conceivable to deposit a silicon oxide film again on the entire surface of the substrate and perform a masking process so that the thickness of the silicon oxide film is set to a specified value for each region. Will increase.

The present invention has been made in view of such conventional problems, and prevents the thickness of the U-MOS gate insulating film from becoming thinner at the corners of the trench than at the side walls of the trench, thereby lowering the gate breakdown voltage. It is an object of the present invention to provide a method for manufacturing a semiconductor device which can manufacture a U-MOS without any problem without increasing the number of steps.

[0005]

According to a first aspect of the present invention, there is provided a semiconductor device having a semiconductor region formed on a side surface of a trench formed in a semiconductor substrate with a gate insulating film interposed therebetween. A method of manufacturing a semiconductor device including a U-MOS having a gate electrode having a gate electrode for inducing a channel in a first step of forming the trench from a substrate surface in the semiconductor substrate; A second step of forming a first insulating film to be an insulating film; a third step of depositing a first polysilicon film to be the gate electrode on the first insulating film; The above first trench is selectively left over a portion of the upper portion of the trench that is larger than the opening area of the trench.
And a fifth step of removing the first insulating film in a region where the first polysilicon film has been removed. With this configuration, when the first insulating film is removed by etching, the first polysilicon film left in the opening above the trench is used as a mask to prevent etching of the first insulating film at the corner of the trench, and The thickness of the insulating film does not become thinner at the corner of the trench than at the side of the trench.

According to a second aspect of the present invention, there is provided a semiconductor device for manufacturing an intelligent power device including, on a main surface of the semiconductor substrate, the U-MOS and another semiconductor element constituting a control circuit of the U-MOS. A manufacturing method, in addition to the first to fifth steps according to claim 1,
A sixth step of forming a second insulating film having a thickness different from that of the first insulating film and serving as a gate insulating film of the another semiconductor element, and a second step of forming a second insulating film serving as a gate electrode of the other semiconductor element; The gist of the present invention is to include a seventh step of depositing a polysilicon film and an eighth step of selectively etching and removing the second polysilicon film to form the gate electrode.
With this configuration, when manufacturing an intelligent power device including another semiconductor element such as a U-MOS and a C-MOS constituting a control circuit for the U-MOS, an operation similar to the operation of the invention described in claim 1 can be obtained. Can be

[0007]

According to the first aspect of the present invention, the U-MO
In a method of manufacturing a semiconductor device including S, a first step of forming a trench from a substrate surface in a semiconductor substrate and a second step of forming a first insulating film serving as a gate insulating film on the trench side surface and the substrate surface And a third step of depositing a first polysilicon film serving as a gate electrode on the first insulating film, and selectively removing a portion of the trench that is wider than the opening area of the trench inside and above the trench. A fourth step of removing the first polysilicon film while leaving;
And a fifth step of removing the first insulating film in a region where the first polysilicon film has been removed. Therefore, when the first insulating film is removed by etching, the upper part of the trench is removed in the fourth step. Since the first polysilicon film left in the opening portion serves as a mask to prevent the etching of the first insulating film at the corner of the trench, the number of steps is not increased and the gate breakdown voltage is not reduced. MOS can be manufactured.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device for manufacturing an intelligent power device, wherein in addition to the first to fifth steps of the first aspect, the first insulating A sixth step of forming a second insulating film having a thickness different from that of the film and serving as a gate insulating film of another semiconductor element, and depositing a second polysilicon film serving as a gate electrode of the other semiconductor element; Since a seventh step and an eighth step of selectively etching and removing the second polysilicon film to form the gate electrode are provided, the U-M
When manufacturing an intelligent power device provided with an OS and another semiconductor element such as a C-MOS constituting a control circuit therefor, the same effect as the effect of the first aspect of the present invention can be obtained.

[0009]

FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described with reference to FIGS. The present embodiment is applied to a method of manufacturing an intelligent power device (IPD) including a U-MOS as a power device and a C-MOS constituting a control circuit for the U-MOS.

First, the gist of the present embodiment will be described with reference to FIGS. 1 (a), 1 (b) and 1 (c). FIG. 1 (a),
(B) and (c) show a second silicon oxide film (a second insulating film) serving as a gate insulating film of a C-MOS by removing a first silicon oxide film (a first insulating film) on a substrate surface. 2 shows a cross section of a U-MOS region in a step of forming a film. FIG. 1A shows a state before the first silicon oxide film 32 is removed, FIG. 1B shows a state after the first silicon oxide film 32 on the substrate surface is removed by hydrofluoric acid treatment, and FIG. The state after the formation of the oxide film 38 is shown. The components in FIG. 1 include an N-type silicon active layer 4 serving as a drain of a U-MOS, a P-type diffusion layer 20 serving as a base layer of a U-MOS,
A N ⁺ type diffusion layer 34 serving as a source region of the MOS, a plasma CVD oxide film 35, a first silicon oxide film 32 serving as a gate insulating film of the U-MOS, and a first N ^{+ serving as} a gate electrode of the U-MOS -Type doped polysilicon film 33, polysilicon film 36, a second gate insulating film for C-MOS
Of the silicon oxide film 38 of FIG.

As shown in FIG. 1A, a plasma CVD oxide film 35 on an N ⁺ -type doped polysilicon film 33 is processed at least wider than a trench width, and a known etch is performed using the plasma CVD oxide film 35 as a mask. The N ⁺ -type doped polysilicon film 33 is processed into a U-MOS gate electrode by using the back technique. At this time, the N ⁺ -type doped polysilicon film 33 selectively leaves a portion wider than the opening area of the trench at the upper end of the trench. In the next step, as shown in FIG. 1B, the first silicon oxide film 32 on the substrate surface in the region where the N ⁺ -type doped polysilicon film 33 has been removed is removed by hydrofluoric acid treatment. At this time, the N ⁺ -type doped polysilicon film 33 left in the opening above the trench is used as a mask to prevent the etching of the first silicon oxide film 32 at the corner of the trench. The thickness of the U-MOS gate insulating film according to No. 32 does not become thinner at the corner of the trench than at the side of the trench. Therefore, without increasing the number of steps, U
-It becomes possible to manufacture MOS. Then, FIG.
As shown in (c), a second silicon oxide film 38 to be a gate insulating film for C-MOS is formed to a thickness of 20 nm.

Next, a method of manufacturing an intelligent power device (IPD) will be described in order with reference to FIGS. As shown in FIG. 2A, an N-type silicon semiconductor support substrate 1, a silicon oxide film layer 2, an N ⁺ -type Sb-doped buried layer 3, and an N-type silicon active layer 4 substantially serving as a drain of a U-MOS. An SOI substrate to be configured is prepared. For example, the silicon oxide film layer 2 is 2 μm, N ⁺ type S
The b-doped buried layer 3 is 3 μm, the N-type silicon active layer 4
Has a thickness of 7 μm. First, C-MOS (N-MO
The regions where S, P-MOS) and U-MOS are to be formed are trench-isolated as follows. A silicon oxide film 5 is formed to a thickness of 100 nm on the surface of the substrate, a resist pattern 6 is formed thereon, and P (phosphorus) is ion-implanted at a predetermined position in a region to be a U-MOS (FIG. 2B). The resist pattern 6 is removed using an ashing device, and 11
20 ° C., 60 minutes, subjected to a heat treatment in an N ₂ atmosphere, N ⁺ -type S
An N ⁺ -type diffusion layer 7 reaching the b-doped buried layer 3 is formed (FIG. 2C). The silicon oxide film 5 on the surface is removed with buffered hydrofluoric acid, and a silicon oxide film 8 used as a mask for trench etching is formed on the surface again with a thickness of about 800 nm. A resist pattern (not shown) for isolation is formed on the surface, and the silicon oxide film 8 is
_The silicon oxide film 8 is dry-etched using ₄ gases and the resist pattern is removed by an ashing device.
Is subjected to isolation pattern processing (Fig. 2
(D)). Silicon is dry-etched using a magnetron RIE apparatus to form a trench 10. At this time, the depth of the trench 10 needs to reach the silicon oxide film layer 2 (FIG. 3A). H ₂ O oxidation is performed on the side wall of the trench 10 at 1100 ° C. to form a silicon oxide film 11 of about 800 nm. Thereafter, a polysilicon film 12 is formed to a thickness of 3 μm using an LPCVD apparatus, and the trench 10 is completely filled (FIG. 3B). Trench 10
Unnecessary polysilicon film on the surface of the substrate is etched back by a dry etching apparatus while leaving only the polysilicon film 13 inside. Thereafter, the silicon oxide film 9 on the surface is removed with buffered hydrofluoric acid, and the silicon oxide film 14
Is formed at 950 ° C. at about 40 nm by dry O ₂ oxidation (FIG. 3C). In this way, the C-MOS (N-
MOS, P-MOS) and a region for forming a U-MOS are separated by trench isolation.

Next, a resist pattern 15 having an opening at a predetermined position in a region to be a P-MOS is formed, and P ⁺ (phosphorus) is formed.
Is ion-implanted (FIG. 3D). Resist pattern 1
After removing 5 with sulfuric acid, a resist pattern 16 having an opening at a predetermined position in a region to be an N-MOS is formed.
⁺ (Boron) is ion-implanted (FIG. 4A). After removing the resist pattern 16 with sulfuric acid, a resist pattern 17 having an opening in a portion where a U-MOS is to be formed is formed.
B ⁺ (boron) is ion-implanted (FIG. 4B). After removing the resist pattern 17 with sulfuric acid, 1120 ° C.
Heat treatment is performed in N ₂ atmosphere for 960 minutes. Thus, U
A P-type diffusion layer 20 as a base layer in a region to be a MOS, a P-type diffusion layer 21 in a region to be an N-MOS,
An N-type diffusion layer 22 is formed in a region to be the OS. The silicon nitride film 18 is coated on the substrate surface with an LPCVD
Then, a resist pattern (not shown) having an opening in the LOCOS region is formed, the silicon nitride film 18 in the opening is removed by dry etching, and the resist pattern is removed by an ashing device. In order to form a channel stopper at a predetermined position in a region to be a P-MOS, a resist pattern 19 is formed, and B ⁺ (boron) is ion-implanted (FIG. 4C). Resist pattern 19
Is removed with sulfuric acid, a resist pattern 23 is formed, and P ⁺ (phosphorus) is ion-implanted to form a channel stopper at a predetermined position in a region to be an N-MOS (FIG. 4D). After removing the resist pattern 23 with sulfuric acid, a silicon field oxide film 24 of about 650 nm is formed at 1000 ° C. by H ₂ O oxidation. At this time, a channel stopper diffusion layer of the N ⁺ -type diffusion layer 25 is formed at a predetermined position of the region to be the N-MOS, and a P ⁺ -type diffusion layer 26 is formed at a predetermined position of the region to be the P-MOS. Thereafter, the silicon nitride film 18 on the surface is heated with hot phosphoric acid (155 ° C., 7 ° C.).
(0 min) treatment, and after removing the silicon oxide film 14 on the surface with buffered hydrofluoric acid, a silicon oxide film 27 is again formed to a thickness of 20 nm by dry O ₂ oxidation at 900 ° C. (FIG. 5A )). In order to form an N ⁺ type diffusion layer at a predetermined position in a region to be a U-MOS, a resist pattern 28 is formed, and As ⁺ (arsenic) is ion-implanted (FIG. 5).
(B)). After removing the resist pattern 28 using an ashing device, the silicon nitride film 2 is removed using an LPCVD device.
9 is 100 nm, and the PSG film 30 (P
₂ O ₅ : 4 mol%) is formed to a thickness of 350 nm. U-MO
A resist pattern (not shown) is formed to form a trench at a predetermined position in a region to be S, and the PSG film 30, the silicon nitride film 29, and the silicon oxide film 27 are removed by dry etching. To remove the resist pattern. The silicon is dry-etched using a magnetron RIE apparatus to form a trench 31 having a depth of about 2.2 μm (FIG. 5C). The PSG film 30 is removed with buffered hydrofluoric acid, and the silicon nitride film 2 is removed.
9 is removed with hot phosphoric acid (FIG. 5D).

A first silicon oxide film 32 serving as a gate insulating film of the U-MOS portion is formed at 1050 ° C. by dry O ₂ oxidation to a thickness of 50 nm, and then P (phosphorus) serving as a gate electrode of the U-MOS portion is formed. Doped first polysilicon film 33
(N ⁺ doped polysilicon film) is formed to a thickness of about 350 nm by an LPCVD apparatus. This first silicon oxide film 3
At the time of forming 2, an N ⁺ type diffusion layer 34 serving as a source region is formed at a predetermined position in the U-MOS region (FIG. 6A). The thickness of the CVD oxide film 35 is set to 100 nm using a plasma CVD apparatus.
(FIG. 6B). The polysilicon film 36 is L
Formed about 1200nm by PCVD equipment, U-MOS
Part of the trench is completely buried (FIG. 6C). The polysilicon film 36 unnecessary for filling the trench is etched back by dry etching. The plasma CVD oxide film 35 functions as an etching stopper and can detect the end point of the etching.

Here, the N ⁺ -type doped polysilicon film 3
3 is processed as a U-MOS gate electrode as follows.
First, a resist pattern 37 is formed at a predetermined position.
At this time, the resist pattern 37 is characterized in that the width is wider than the trench width. This resist pattern 3
7 is used as a mask, the plasma CVD oxide film 35 is etched with buffered hydrofluoric acid (FIG. 6 (d)), and the resist pattern 37 is removed with sulfuric acid.
The D oxide film 35 is processed. Using the plasma CVD oxide film 35 thus patterned as a mask, the N ⁺ -type doped polysilicon film 33 is etched back by dry etching. The gate electrode 33 processed by such a method has a processing shape that is at least wider than the trench width at the upper portion of the trench and covers the entire upper end portion of the trench (FIG. 7A). Next, C-MOS (N-MO
In order to form a second silicon oxide film serving as a gate insulating film in the (S, P-MOS) portion, the first silicon oxide film 32 on the surface is once removed with buffered hydrofluoric acid (FIG. 7).
(B)) A second silicon oxide film 38 is again formed to a thickness of 20 nm at 900 ° C. by dry O ₂ oxidation. At this time, U
Since the gate electrode 33 in the -MOS region covers the upper end of the trench, the gate oxide film 32 in the U-MOS region is not cut off at the top of the trench and becomes thinner (FIG. 7).
(C)).

A second polysilicon film 39 serving as a gate electrode of the C-MOS portion is formed to a thickness of 350 nm by an LPCVD apparatus, and P ⁺ (ions) are ion-implanted into the polysilicon film 39, thereby forming a predetermined portion of the C-MOS portion. A resist pattern is formed at the position, dry etching is performed, and the resist is stripped to form a gate electrode wiring (FIG. 7D). A resist pattern 41 is formed, and P ⁺ (phosphorus) is ion-implanted into a predetermined position of the N-MOS portion (FIG. 8A). After removing the resist pattern 41 with sulfuric acid or the like, a resist pattern 42 is formed again, and a BF is formed at a predetermined position in the P-MOS portion.
₂ ⁺ (ion) are implanted (Figure 8 (b)). After that, the resist pattern 42 is removed with sulfuric acid or the like. A CVD oxide film 43 is formed on the surface of the substrate to a thickness of about 30 nm (FIG. 8).
(C)). The LDD spacer 44 is formed by performing etch-back by a known etch-back method,
An oxide film (not shown) of about nm is formed (FIG. 8).
(D)). A resist pattern 45 is formed and an N-MOS
Then, P ⁺ (ion) is ion-implanted into a predetermined position of the U-MOS portion (FIG. 9A). After removing the resist pattern 45 with sulfuric acid or the like, a resist pattern 46 is formed again,
BF ₂ ⁺ (ions) are ion-implanted into predetermined positions of the -MOS and U-MOS portions (FIG. 9B). After that, the resist pattern 46 is removed with sulfuric acid or the like. An NSG BPSG film 53 is formed as an interlayer insulating film in a thickness of about 150 nm to 450 nm, and is heat-treated at 950 ° C. in a diffusion furnace for about 20 minutes.
At this time, the diffusion layers 47 to 47 are located at predetermined positions where the ion implantation is performed.
52 are formed (FIG. 9C). A contact hole is formed at a predetermined position, aluminum is formed to a thickness of about 1 μm by sputtering, and electrodes 54 to 62 are formed by dry etching (FIG. 9D).

By using the manufacturing method of this embodiment,
Power element unit (U-MOS) having a vertical field effect transistor (U-MOS) structure using a trench gate electrode
And an intelligent power device (IPD) having a control circuit unit (C-MOS) at the same time, a highly reliable intelligent power device (IPD) can be manufactured without lowering the U-MOS gate breakdown voltage. It is clear that the control circuit unit can be applied to an IPD other than the C-MOS structure (for example, a BiC-MOS structure).

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a main point of a method of manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a process chart for explaining the embodiment.

FIG. 3 is a process drawing following FIG. 2;

FIG. 4 is a process drawing following FIG. 3;

FIG. 5 is a process drawing following FIG. 4;

FIG. 6 is a process drawing following FIG. 5;

FIG. 7 is a process drawing following FIG. 6;

FIG. 8 is a process drawing following FIG. 7;

FIG. 9 is a process drawing following FIG. 8;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 N-type silicon semiconductor support substrate 4 N-type silicon active layer serving as U-MOS drain 20 P-type diffusion layer serving as U-MOS base layer 31 Trench 32 First silicon oxide serving as U-MOS gate insulating film Film 33 First N ⁺ -type doped polysilicon film serving as a gate electrode of U-MOS 34 N ⁺ -type diffusion layer 38 serving as a source region of U-MOS 38 Second silicon serving as a gate insulating film for C-MOS Oxide film 39 Second polysilicon film serving as gate electrode for C-MOS

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Koichi Murakami 2nd Takaracho, Kanagawa-ku, Yokohama-shi, Kanagawa F-term (reference) 5F048 AA05 AA07 AA09 AC03 AC06 BA12 BA16 BA19 BB05 BB06 BB16 BB20 BC06 BC11 BG12 BG14 DA12

Claims (2)

[Claims] 1. Manufacturing of a semiconductor device including a U-MOS having a gate electrode formed on a side surface of a trench formed in a semiconductor substrate via a gate insulating film and having a gate electrode for inducing a channel in a semiconductor region on a side surface of the trench. In the method,
A first step of forming the trench in the semiconductor substrate from a substrate surface, a second step of forming a first insulating film serving as the gate insulating film on the trench side surface and the substrate surface, and A third step of depositing a first polysilicon film serving as the gate electrode on the film; and a step of selectively leaving a portion wider than the opening area of the trench inside the trench and above the trench. A method of manufacturing a semiconductor device, comprising: a fourth step of removing a polysilicon film; and a fifth step of removing the first insulating film in a region where the first polysilicon film has been removed. Method. 2. The semiconductor device according to claim 1, wherein said U-MO
A method for manufacturing a semiconductor device for manufacturing an intelligent power device including S and another semiconductor element constituting a control circuit of the U-MOS, wherein the method comprises the steps of: A sixth step of forming a second insulating film having a thickness different from that of the first insulating film and serving as a gate insulating film of the another semiconductor element, and a second step of forming a second insulating film serving as a gate electrode of the other semiconductor element; Manufacturing a semiconductor device, comprising: a seventh step of depositing a polysilicon film; and an eighth step of selectively etching away the second polysilicon film to form the gate electrode. Method.