JP2000299389A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an I/O transistor with improved high electrostatic breakdown resistance, while maintaining drive capability. SOLUTION: This semiconductor device has a semiconductor substrate 1, an internal transistor 90, and an I/O transistor 80. In this case, the semiconductor device is equipped with a lightly-doped diffused(LDD) region 4 that is formed in the source/drain region of the internal transistor 90, a heavily-doped diffused region 9 that has a concentration of impurities larger than that of the LDD region 4 formed at a contact region, a silicide layer 10 that is formed at the surface between the source/drain and contact regions of the internal transistor 90, and an intermediate concentration diffused region 6 that has concentration of impurities which are larger than that of the LDD region but smaller than that of the heavily-doped diffused region 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device that exchanges data with an external device via an input / output transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the diffusion layer of a transistor has become thinner with the miniaturization of each constituent element due to the higher integration of a semiconductor element, and an increase in the resistance of the diffusion layer has become a problem. Therefore, a technique has been proposed in which a low-resistance silicide layer is formed on the surface of the diffusion layer to lower the resistance of the diffusion layer, thereby avoiding a reduction in element operation speed. However, a surge (abnormal voltage) such as noise is easily applied to the input / output transistor provided in the semiconductor device from the outside. Therefore, if a low-resistance silicide layer is formed in a region adjacent to the gate electrode on the surface of the diffusion layer, the electrostatic capacitance becomes high. There is a problem that the breakdown voltage becomes insufficient.
Therefore, conventionally, a silicide layer must be formed on the surface of a diffusion layer in an internal transistor of a semiconductor device that requires high-speed operation, and a silicide layer must not be formed in a diffusion layer of an input / output transistor that requires an electrostatic breakdown voltage. As a result, the required electrostatic breakdown voltage has been secured. In the following:
This conventional technique will be described more specifically.

FIG. 1 is a view for explaining a conventional method of manufacturing a first semiconductor device. In this semiconductor device, first, as shown in FIG. 1A, an input / output circuit region and an internal circuit region are separated from each other by forming an element isolation insulating film 2 on a semiconductor substrate 1. Next, the semiconductor substrate 1
A gate oxide film 5 and a gate electrode 3 are formed in each of the upper input / output circuit region and the internal circuit region. And
Using the gate electrode 3 as a mask, impurities are uniformly ion-implanted at a low concentration dose over the entire surface of the semiconductor substrate 1 so that the LDD region (low-concentration diffusion region) 4 is self-aligned with the gate electrode 3. Formed.

[0004] Next, as shown in FIG. 1 (b), an insulating film 7 is formed on the entire surface of the semiconductor substrate 1, typically by chemical vapor deposition of a SiO ₂ film. Then, FIG.
As shown in FIG. 6, the insulating film 7 is etched back by performing anisotropic etching that acts substantially perpendicularly on the semiconductor substrate 1, thereby forming the sidewall insulating film 7A of the gate electrode. After that, using the gate electrode 3 and the side wall insulating film 7A as a mask, the impurity of the same conductivity type as the impurity implanted into the LDD region 4 is implanted at a high concentration dose to form the high concentration diffusion region 9. Next, as shown in FIG. 1D, a silicide layer 1 made of cobalt or titanium is formed on the surfaces of the source / drain region of the input / output transistor 80 and the source / drain region of the internal transistor 90.
0 is formed in a self-aligned manner. Next, as shown in FIG. 1E, the internal transistor 90 is protected by a resist pattern, and the silicide layer 1 of the input / output transistor 80 is protected.
Only 0 is removed by etch back.

However, the conventional semiconductor device manufactured in this manner does not include a silicide layer in the source / drain region (diffusion layer) of the input / output transistor 80, and therefore, the resistance and the electrode of the diffusion layer of the input / output transistor 80 are not provided. An increase in contact resistance causes an operation delay. Therefore, from such a viewpoint, it is desirable to provide a silicide layer also in the source / drain region of the input / output transistor as the driving element.

Therefore, conventionally, Japanese Patent Laid-Open No.
A semiconductor device disclosed in Japanese Patent Application Publication No. 0-70266 has been devised. That is, in the second conventional semiconductor device, as shown in FIG. 2, silicide layers 10A and 10B are provided in the diffusion region of the output transistor, while the silicide layer 10B is separated from the gate electrode on the surface of the drain region. It is formed separately. Here, in order to provide the silicide layer 10B at a distance from the gate electrode, the insulating film 7B is previously covered so as to cover one of the side wall insulating films 7A of the gate electrode.
Is formed to extend from directly above the gate electrode to a part of the drain region. Also, the sidewall insulating film 7A directly under the gate electrode, conventionally the n ^- type or p ^- forms of LDD
Region 4 is formed.

However, the semiconductor device having such a structure also has the following problems. That is, first, forming the insulating film 7B on one side of the diffusion region of the output transistor by patterning as designed involves technical difficulties in terms of precision, and it is necessary to form the insulating film 7B on the gate electrode when forming the insulating film 7B. Depending on the displacement of the formation position of the resist film to be formed, the side wall of the gate electrode may be exposed by the subsequent etching. Since the LDD region 4 is a low concentration diffusion layer, the semiconductor substrate 1 and the LDD region 4
The collector resistance of the parasitic bipolar transistor Tr formed by the above is high, and when a surge (abnormal voltage) is applied to the output terminal OUT or the semiconductor substrate 1, a large amount of heat is generated and the output transistor is destroyed. There's a problem. Note that, in the conventional semiconductor device shown in FIG. 2, n ^{+ is} normally provided under the silicide layers 10A and 10B.
The diffusion layer 9A is formed so as to reach the end of the side wall insulating film 7A.

In addition, the ground terminal G
When the potential of the ND changes, the potential change is transmitted directly to the LDD region 4 in the source region via the silicide layer 10A, and thus there is a problem that the above-described destruction easily occurs.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and has an input / output transistor having a higher electrostatic breakdown resistance than a conventional one while ensuring the driving capability. And a method of manufacturing the same.

[0010]

The object of the present invention is to provide a semiconductor substrate, a first gate electrode formed in a first region on the semiconductor substrate, and a first gate electrode formed on both sides of the first gate electrode. An internal transistor having one source / drain region, a second gate electrode formed in a second region on the semiconductor substrate, and second source / drain formed on both sides of the second gate electrode And a first source / drain region formed in a region adjacent to the first gate electrode and having an LDD region having a first impurity concentration. Also has a first diffusion region having a high concentration, the second source / drain region has a second diffusion region having a second impurity concentration higher than the first impurity concentration, and a second gate electrode. Formed between the second diffusion region A third diffusion region having a third impurity concentration higher than the first impurity concentration and lower than the second impurity concentration, and an ohmic electrode is provided in the first diffusion region and the second diffusion region. This is achieved by providing a semiconductor device having a bonded contact region.

Further, the object of the present invention is also attained by providing a semiconductor device further comprising an insulating film formed immediately above and on the side wall of the second gate electrode and on the surface of the second diffusion region. . Further, the object of the present invention is also achieved by providing a semiconductor device in which the input / output transistor is a component of at least one of a data input circuit and a data output circuit of the semiconductor device.

Another object of the present invention is to form a first gate electrode formed in a first region on a semiconductor substrate and first source / drain regions formed on both sides of the first gate electrode. And an input / output transistor formed in a second region on the semiconductor substrate and having a second gate electrode and second source / drain regions formed on both sides of the second gate electrode. A method for manufacturing a semiconductor device comprising: forming a first and a second gate electrode on a semiconductor substrate; and performing a first concentration impurity diffusion on the semiconductor substrate to form a first source / drain region. Forming an LDD region on the second source / drain region and, after covering the internal transistor with a resist, diffusing an impurity of a second concentration higher than the first concentration into the second source / drain region; A first diffusion step of forming a first diffusion layer in the second source / drain region by removing the resist, forming an insulating film on the entire surface of the semiconductor substrate by removing the resist, and masking the second gate electrode. After that, an etching step of anisotropically etching the entire surface of the insulating film and an impurity diffusion of a third concentration higher than the second concentration in the semiconductor substrate are performed to form the first source / drain region and the second source / drain region. A second diffusion step of forming a second diffusion layer, and a step of forming a silicide layer on the surface of the second diffusion layer. You.

Further, the object of the present invention is achieved by providing a method of manufacturing a semiconductor device in which a sidewall insulating film of a first gate electrode is further formed in the above-mentioned etching step. Further, the object of the present invention is achieved by providing a method of manufacturing a semiconductor device in which a diffusion layer resistance is formed at the same time in the first diffusion step.

According to the above means in the present invention, even if a surge such as static electricity from the outside enters the input / output transistor through the silicide layer from any of the contact regions of the second source / drain regions, the resistance is higher than that of the silicide layer. Since the surge energy is absorbed in the second diffusion region having the high second impurity concentration, a high electrostatic breakdown voltage can be realized.

By forming the third diffusion region having a lower resistance value than the LDD region, the parasitic resistance of the input / output transistor and the collector resistance of the lateral transistor in the electrostatic breakdown model can be reduced.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. The same reference numerals in the drawings denote the same or corresponding parts. FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. In the figure, only the N-channel transistor is shown. The input / output transistor 80 in the figure constitutes a data input circuit and a data output circuit of the semiconductor device.

As shown in FIG. 3A, an element isolation insulating film 2 is first formed on a semiconductor substrate 1 to separate an input / output circuit region and an internal circuit region from each other. Next, a gate oxide film 5 is formed in each of the input / output circuit region and the internal circuit region on the semiconductor substrate 1. Then, a gate electrode 3 is formed by forming and patterning a polycide gate film on the gate oxide film 5. Next, using the gate electrode 3 as a mask, a P ⁺ impurity is ion-implanted into the semiconductor substrate 1 so that the substrate surface concentration becomes 1 × 10 ¹⁹ cm ⁻³ or less, so that the LDD region (low-concentration diffusion region) 4 becomes a gate electrode. 3 is formed in a self-aligned manner.

Next, as shown in FIG. 3B, the internal transistor 90 is formed in a resist 1 by mask patterning in which only an area where the input / output transistor 80 is formed is opened.
After masking with P.2, the region where the input / output transistor 80 is to be formed is doped with P ⁺ impurities at a substrate surface concentration of 1 × 10 ¹⁹ cm ^−3.
By implanting ions so as to have a density of about 1 × 10 ²⁰ cm ⁻³ , the middle concentration diffusion region 6 is formed in a self-aligned manner with respect to the gate electrode 3. In the case where a diffusion layer resistor is formed on the semiconductor substrate 1, if the patterning for forming the diffusion layer resistance is performed simultaneously with the mask patterning, the number of steps does not increase.

Next, as shown in FIG. 3C, an insulating film 7 for a sidewall spacer of the gate electrode 3 is formed on the entire surface of the semiconductor substrate 1 typically by chemical vapor deposition of a SiO ₂ film. Is done. Then, as shown in FIG. 3D, a mask 8 is used to mask the semiconductor substrate 1 from just above the gate electrode 3 of the input / output transistor 80 to a part of the medium-concentration diffusion region 6 using a mask pattern. To perform anisotropic etching which acts almost vertically. By this etching step, the insulating film 7 is etched back, and the side wall insulating film 7A of the gate electrode 3 is formed at the same time. In this step, the resist 8 is applied to a position away from the side wall of the gate electrode 3 by a certain distance to improve the electrostatic breakdown voltage, and is experimentally applied, for example, to a position 0.5 μm away from the side wall. The effect was also obtained by this. In the case where a diffusion layer resistor is formed on the semiconductor substrate 1, if the patterning for forming the diffusion layer resistor is performed at the same time as the mask patterning, the number of steps is not further increased.

FIG. 4 is a diagram for further explaining the method of manufacturing the semiconductor device according to the embodiment of the present invention. FIG.
As shown in (a), after removing the resist 8 covering the gate electrode 3 of the input / output transistor, As is applied to the entire surface of the semiconductor substrate 1 so that the substrate surface concentration becomes 1 × 10 ²⁰ cm ⁻³ or more. by ion-implanting an impurity at a high concentration ⁺ high concentration diffusion region 9 is formed on the source and drain regions of the region and an internal transistor which is not covered with the insulating film 7 of the source and drain regions of the output transistor 80 You.

Next, as shown in FIG. 4B, a high melting point metal such as titanium is deposited on the entire surface of the semiconductor substrate 1 and heat-treated, so that the source / drain region of the input / output transistor 80 is formed. A silicide layer 10 made of titanium or the like is formed on the surface of the formed high concentration diffusion region 9 and the surface of the source / drain region of the internal transistor 90. As the high melting point metal, cobalt, tungsten, nickel or the like is used in addition to titanium.

Next, as shown in FIG. 4C, an interlayer insulating film 13 is deposited on the entire surface of the semiconductor substrate 1, and then an electrode contact hole 14 is formed on the silicide layer 10. Then, as shown in FIG. 4D, the conductor wiring patterns 15 are filled so as to fill the electrode contact holes 14.
Is formed.

The semiconductor device according to the embodiment of the present invention is manufactured by the above method. According to such a semiconductor device, the input / output transistor 80 forming the input / output circuit for inputting / outputting data is used. With respect to (1), the high electrostatic breakdown resistance can be further improved as compared with the related art while securing the driving ability.

[0024]

As described above, according to the present invention, it is possible to easily obtain a semiconductor device having an input / output transistor whose driving capability is ensured and whose electrostatic breakdown resistance is improved as compared with the prior art.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method for manufacturing a first conventional semiconductor device.

FIG. 2 is a diagram showing a structure of a second conventional semiconductor device.

FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a diagram further illustrating the method of manufacturing the semiconductor device according to the embodiment of the present invention;

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 element isolation insulating film 3 gate electrode 4 LDD region (low concentration diffusion region) 5 gate oxide film 6 medium concentration diffusion region 7, 7B insulation film 7A sidewall insulation film 8, 12 resist 9 high concentration diffusion region 9A n ⁺ Diffusion layer 10, 10A, 10B Silicide layer 13 Interlayer insulating film 14 Electrode contact hole 15 Conductor wiring pattern 80 Input / output transistor 90 Internal transistor

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA01 BB20 BB21 BB25 BB28 CC01 DD04 DD08 DD26 EE03 EE06 FF28 GG10 HH20 5F048 AA02 AA05 AB06 AB07 AC01 AC03 BA01 BB05 BC06 BC20 BF06 BF16 BG12 DA25

Claims (2)

[Claims] A semiconductor substrate; a first gate electrode formed in a first region on the semiconductor substrate; and first source / drain regions formed on both sides of the first gate electrode. I / O transistor having an internal transistor, a second gate electrode formed in a second region on the semiconductor substrate, and second source / drain regions formed on both sides of the second gate electrode And wherein the first source / drain region has an LDD region formed in a region adjacent to the first gate electrode and having a first impurity concentration, and an LDD region having a higher concentration than the first impurity concentration. A first diffusion region, the second source / drain region has a second diffusion region having a second impurity concentration higher than the first impurity concentration, the second gate electrode, With the second diffusion zone A third diffusion region formed between and having a third impurity concentration higher than the first impurity concentration and lower than the second impurity concentration, the first diffusion region and the second diffusion A semiconductor device in which a region has a contact region to which an ohmic electrode is joined. 2. A semiconductor device comprising: a first region formed on a semiconductor substrate;
An internal transistor having a first gate electrode and first source / drain regions formed on both sides of the first gate electrode, formed in a second region on the semiconductor substrate,
A method for manufacturing a semiconductor device comprising: an input / output transistor having a second gate electrode and second source / drain regions formed on both sides of the second gate electrode, wherein the semiconductor substrate includes Forming a first and a second gate electrode; and performing an impurity diffusion at a first concentration in the semiconductor substrate to form an LDD region in the first source / drain region and the second source / drain region. Forming, and after covering the internal transistor with a resist, the second source / drain region is diffused with an impurity having a second concentration higher than the first concentration in the second source / drain region. A first diffusion step of forming a first diffusion layer, a step of removing the resist and forming an insulating film over the entire surface of the semiconductor substrate, and masking the second gate electrode. Then, an etching step of anisotropically etching the entire surface of the insulating film; and performing an impurity diffusion of a third concentration higher than the second concentration on the semiconductor substrate to thereby form the first source / drain region and the second A second diffusion step of forming a second diffusion layer in the source / drain region of the semiconductor device, and a step of forming a silicide layer on the surface of the second diffusion layer.