JP2000298464A - Digital imaging control having luminance resolution selectively enhanced - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an adjusting method for digital imaging which improves the resolution of an image. SOLUTION: An image is automatically enhanced by correcting the reference voltage (VREF), gain, and integration period of a differential amplifier 24 so that an input using the whole dynamic range of a differential analog-digital converter(ADC) 32 is supplied to the ADC. When it is used together with a CMOS array, imaging logic 8 is manufactured on a single chip 20 together with the array by using fast and inexpensive combination logic for correction. The digital resolution of an image of a part of interest in spectrum is increased by enlarging a desired part (176-178) of the luminance spectrum of the image.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to digital imaging devices and, more particularly, to automatic and selective brightness resolution enhancement of digital images.
).

[0002]

2. Description of the Related Art Digital imaging devices are becoming increasingly popular for a variety of applications, including digital cameras, fingerprint recognition, digital scanners, copiers, and the like. A typical digital imaging device in the related art is a charge-coupled device (CCD).
e) Based on technology. CCD device is CCD
It has an array of cells, each cell constituting a pixel. Each CCD pixel outputs a voltage signal proportional to the intensity of the light striking the cell. This analog voltage signal can be converted to a digital signal for further processing, digital filtering, storage and the like. As is well known to those skilled in the art, a two-dimensional digital image can be constructed from a voltage signal output from a two-dimensional array of CCD cells, commonly referred to as a sensor array.

[0003] Ambient conditions such as temperature and lighting, and CC
Depending on the characteristics of the D-array, the resulting image may have poor resolution. Poor image resolution can result from very bright light striking the sensor array. In this case, the resulting image may appear to have been washed out. Or, poor image resolution may result from low light conditions. In this case, the resulting image may appear dark and hazy. Another factor in poor image quality may be due to insufficient contrast between bright and dark pixels, resulting in blurred or faint images. Digital signal processing may be used to compensate for certain image quality issues, but by adjusting how analog voltage signals coming from the sensor array are handled before entering the analog-to-digital converter. Can significantly improve the image.

[0004]

Accordingly, there is a need for a method for adjusting digital imaging that increases contrast illumination as a common technique for improving image resolution.

[0005]

SUMMARY OF THE INVENTION In one aspect, the present invention comprises a reference voltage input, a signal input, a programmable gain value, and a differential output coupled to an analog-to-digital converter (ADC). An automatic gain control method for an image processor comprising a programmable amplifier and an analog-to-digital converter for outputting a digital code corresponding to the output of the programmable amplifier, comprising: reading a frame of luminance data; Determining a luminance value and a digital code output from the ADC corresponding to the average luminance value. The method further includes: a reference voltage that causes the digital code output from the ADC to be a target value when the input of the programmable amplifier is set to the average luminance value;
Calculating a gain that causes the digital code output from the ADC to be at the target value when the input of the programmable amplifier is set to the average luminance value. The method also includes the steps of setting the reference voltage and gain to the calculated values and reading out the next frame.

In another aspect, the present invention is an image processor, comprising: a differential amplifier for receiving a luminance signal and a reference voltage signal as inputs and outputting an amplified differential signal; A differential analog-to-digital converter (ADC) for receiving a signal as an input and outputting a digital signal corresponding to the amplified differential signal; a programmable voltage source for outputting the reference voltage signal; A digital averager that outputs an average luminance value, a digital signal controller that receives the average luminance value, outputs a gain control signal to the differential amplifier, and outputs a reference voltage control signal to the programmable voltage source. So,
(1) Digital signal control in which the gain control signal and the reference voltage control signal are determined from the difference between the digital signal of the analog-digital converter when the luminance input is at the average luminance value and (2) the desired digital signal. An image processor comprising:

In another aspect, the present invention comprises an automatic gain amplifier having an amplifier that receives as input a frame of a luminance signal and a reference voltage signal and outputs a differential signal corresponding to the difference between the luminance signal and the reference voltage signal. A control circuit is provided. The amplifier amplifies the difference under the control of the gain control signal. The automatic gain control circuit receives a signal output from the amplifier and outputs a digital signal corresponding to a differential output of the amplifier, and calculates an average luminance value for the frame. Means for comparing a digital signal output from the ADC with a desired digital output when the luminance signal input of the amplifier is at the average luminance value, and generating a difference signal; and responsive to the difference signal. A means for adjusting the reference voltage signal and a means for adjusting the gain control signal in response to the difference signal are also provided.

The above features of the present invention will be more clearly understood from the following description with reference to the accompanying drawings.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The implementation and use of various embodiments will now be described. However, it should be understood that the invention provides a number of applicable inventive concepts that can be implemented in various specific contexts. The specific embodiments described herein are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

FIG. 1 shows a digital imaging device 2 utilizing a preferred embodiment of the present invention. The digital imaging device includes a lens mechanism 4. The lens mechanism 4 receives light coming out of the object to be imaged, that is, reflected from the object, and focuses incident light on the array sensor 6. Array sensor 6 is preferably a co-pending patent application 0
9 / 223,166, "Fast Frame Readout Architecture for Array Sensors with Integrated Correlated Double Sampling System" (Fast Frame)
Readout Architecture for
Array Sensors with Integr
added Correlated Double Sa
a CMOS sensor array of the type well described in US Pat. This application is incorporated herein by reference. As known to those skilled in the art, the sensor array 6 comprises a two-dimensional array of CMOS sensors. Each sensor outputs an analog voltage signal. This signal is proportional to the intensity of light falling on a particular sensor. As is well known to those skilled in the art, the voltage signal from each sensor can be scanned in a raster format to create an analog image signal. This analog image signal is provided to the imaging logic 8. In the imaging logic 8, the analog signal is buffered, amplified and then converted to a digital signal. After filtering or further processing, the digital signal is sent to an input / output (I / O) port 10 in the form of pixel luminance data.
Alternatively, with additional signal processing, the digital signal can be output in the form of a bitmap or other well-known digital screen format.

Alternatively, the digital signal can be sent to memory 12 for storage. The memory 12 is preferably a random access memory or a static RAM
It is. Alternatively, memory 12 may be a magnetic or optical storage device, such as a magnetic diskette device, CD-ROM, or other storage device. In such a case, a suitable device controller and interface (not shown) are included with the memory 12. Imaging logic 8, memory 12, and I / O port 10 are preferably under the control of microprocessor 14. Microprocessor 14 preferably has memory 12 or ROM 16
Is a general-purpose digital microprocessor that operates under the instructions stored in. The stored instructions may be provided directly to microprocessor 14 via I / O port 10 or
Alternatively, it can be stored in the memory 12 or the ROM 16.

In the preferred embodiment, the sensor array 6 is a CMO
Being composed of an array of S sensor cells, the imaging logic 8 can be formed together with the sensor array 6 on a single integrated circuit using a CMOS process. FIG. 2 shows a single integrated circuit (IC) 20. On this IC 20, both the sensor array 6 and the imaging logic 8 according to the preferred embodiment of the present invention are implemented. Internal control registers,
Other functions and circuits may be included in the IC 20, including microprocessor interface logic, memory interface logic, and the like. These features are not shown as they are not necessary for an understanding of the present invention.

Next, the details of the imaging logic 8 will be described with reference to FIG. The main path for the imaging signal is indicated by the thick arrow. The analog signal from the sensor array 6 is sent to a buffer 22, where the signal is strengthened and fixed pattern noise is removed. The buffered analog signal is sent from buffer 22 to a first input of a programmable gain differential amplifier 24. Amplifier 24
Receives a reference voltage. The reference voltage is controlled by the reference control block 2 under the control of the digital signal controller 28.
Given from 6. The amplifier also receives a gain control signal from gain control block 30. The gain control block 30 operates under the control of the digital signal controller 28.

Amplifier 24 maps the two inputs to fully differential outputs 25,27. In other words, outputs 25 and 2
Numeral 7 is a value obtained by multiplying the difference between the values of the two input signals (that is, the analog image signal and the reference voltage V _REF ) by the gain of the amplifier 24, and corresponds to a signal centered on the common mode voltage level. The fully differential outputs 25, 27 are then provided to the inputs of a differential analog-to-digital converter (ADC) 32. Differential analog-to-digital converter (ADC) 32
The differential value (ie, the difference between signals 25 and 27) is converted to a digital value. The resulting digital image signal is then sent to defective pixel filter. In the defective pixel filter 34, co-pending patent application Ser.
165, "Sequentially correlated double sampling method for CMOS area array sensor" (Sequential Co.)
related DoubleSampling T
etch for CMOS Area Ar
image errors are detected and corrected, as described in more detail in (Ray Sensors). This application is incorporated herein by reference.

Next, the corrected digital image signal is sent to the digital micro interface 36. The digital micro interface 36 includes an IC 20 and a digital imager such as the memory 12, the microprocessor 14, or the I / O port 10.
Provides an interface between two other components.

FIG. 2 shows a digital timing generator 42.
Are also shown. The digital timing generator 42
In order to suppress the fixed pattern noise of the CMOS sensor,
It provides timing signals for the operation of the sequentially correlated double sampling block 44. The row / column information register 46 includes a digital signal controller 28 and a digital averager 38.
Provide information about where the signal currently being processed occurred on the sensor array (ie, provide row and column information for each pixel).

The imaging logic 8 also includes a digital signal feedback loop. The digital signal feedback loop includes a digital average calculator 38, a digital signal controller 28,
It includes a reference control block 26, a gain control block 30, and an irradiation time controller 40. The use of a feedback loop optimizes the output of amplifier 24 to utilize the entire dynamic range of analog-to-digital converter (ADC) 32. This is accomplished by adjusting the gain of amplifier 24, one or both of the reference voltage V _REF inputs.
Done. Two distinct aspects of the image are optimized. The calibration of the optical black ensures that the ADC 32 outputs a value close to zero for the optically black pixel and uses the entire dynamic range of the ADC 32. The resolution enhancement takes into account the optimal contrast of the image.

In the first embodiment, the image resolution is performed automatically via a feedback loop. In an alternative embodiment, an image or a user may select a value to enhance a portion of the dynamic range of the image of interest, as described in further detail below.

In the automatic operation, three steps are performed for each input frame of data. First, an optical black calibration is performed on one or more rows of the frame that are known to be optically black. Second, after the entire frame has been scanned, an amplifier 24 is used to map the frame values over the entire dynamic range of the ADC 32.
Gain and V _REF input are adjusted. Finally, if applicable, the integration time of each subsequent frame, i.e., the frame exposure time, is adjusted to more closely map the frame values over the entire dynamic range of the ADC 32. Each of these steps will be described in more detail later.

Optical Black Calibration Optical black calibration is performed by detecting signals from pixels known to be "dark", ie, receiving no light (ie, CMOS sensors).
This is done by using a light shield 48 on a portion of the sensor array 6. In the preferred embodiment, light shield 48 covers the first four rows of pixels. However, the number of shielded pixels and rows is a matter of design choice. Since these rows are known to be dark, the imaging logic can be calibrated to treat these pixels as black, ie, to have the smallest digital value corresponding to them. For reasons that will become apparent, this minimum digital value should not be set to zero. In the preferred embodiment, the minimum digital value corresponding to a completely black or completely dark pixel is set to 64.

By adjusting the reference voltage V _REF input of the amplifier 24 to provide a calibration for optical black, A
The DC output is driven to its "black" value, preferably 64. The relationship between V _REF and the output of ADC 32 will be described with reference to FIG. FIG. 3 shows the amplifier 24 and the ADC 3
2 and the relationship between the reference control block 26.

As shown, the amplifier 24 has an input
The pixel luminance signal V _sigAnd its inversion
Reference voltage signal V at input_REFReceive. Next, the amplifier 24
Outputs a difference signal equal to the input difference multiplied by the gain
I do. The center of the differential output signals 25 and 27 is the differential ADC 32
Common mode level (CML: common mode)
level) 29.
You. In other words, amplifier 24 determines the difference between its input signals as C
Maps to a differential signal centered on ML. ADC32
The large and minimum operating thresholds are respectively V_TAnd V_BCalled
It is. CML level 29 is V_TAnd V_BIt is the center of.

The transfer equation for the amplifier 24 is given by the following equation.

(Equation 1) Here, g = gain of the amplifier 24. In the case shown, g = 1. Amplifier 24 is preferably 2,
It is programmable with gain values of 4, 8, or 16.
As apparent from FIG. 3, the outputs 25V _inp and 27V _inm are centered on CML. The maximum and minimum thresholds of the ADC 32 are centered on CML. Therefore,

(Equation 2) Since the input of ADC 32 is symmetric with respect to CML, A
The output of DC 32 can be obtained from only one of the input values. In other words, the normalized output of the ADC 32 is as follows:

(Equation 3) Preferably, the highest standards of ADC32 is selected to be (V _T -V _B), minimum standards is selected as zero. Therefore, equation (3), which is the normalized transfer function of the circuit including the amplifier 24 and the ADC 32, can be rewritten into the following equation by substituting the values from equations (1) and (2).

(Equation 4) By adjusting the reference voltage input V _REF of the amplifier 24 using the equation (4), the pixel signal V given the value D _outn is obtained.
_The desired level 64 for _sig and constant gain g can be achieved. As the known black pixel corresponding to the pixel under shield 48 is being scanned, an appropriate value for _VREF is obtained.

As shown in FIG. 3, the reference control block 26
Includes a variable voltage source 52 and a digital-to-analog converter (DAC) 54. The DAC 54 receives the digital signal and converts it into an analog signal. The analog signal is supplied to the variable voltage source 52. A reference voltage input _VREF is generated from the variable voltage source 52. The relationship between the normalization of ADC32 has been output D _outn the input D _inm is given as follows.

For a DAC 54 of size m,

(Equation 5) Here, D _inm is the digital input of the _DAC 54, VT _DAC is the highest reference for the _DAC 54, and VB _DAC is the lowest reference for the _DAC 54. Since DAC54 is designed to fit the ADC 32, VT _DAC = In (V _T -V _B), V
B _DAC = 0. Therefore,

(Equation 6)

Equation (6) can be substituted into equation (4). If ADC32 of size n is given, the relationship between the D _outn and D _inm is given by the following equation.

(Equation 7) This simplifies the D _inm solved by D _outn, the following equation is obtained.

(Equation 8)

In the preferred embodiment, ADC 32 is 10 bits and DAC 54 is 8 bits, and is approximated as follows:

(Equation 9)

According to the relationship of equation (9), D necessary to generate the reference voltage V _REF required for the calibration of the optical black is obtained.
The input of AC54 can be calculated quickly.

A more detailed description of the process steps for the calibration of the optical black will be explained with reference to FIG. The process begins with the start of a new frame in step 60. At decision step 62, the ADC 32 for the known optically black pixel (ie, the pixel shielded by the shield 48).
By comparing the output D _out to a threshold value or threshold range to determine whether the output is within an acceptable range for optically black pixels. Preferably, ADC 32 outputs a value of 64 for such a pixel, with a range of plus or minus 10 being allowed. If the output is within the acceptable range, there is no need to adjust the reference voltage V _REF input of amplifier 24. Therefore, as shown in step 64, the value for V _REF is frozen and the process proceeds to decision step 68. On the other hand, if the output of the ADC 32 is not within the permitted range, the process proceeds to step 66. At step 66, the output of ADC 32 is set to a value of 64 by adjusting the value for V _REF as described for equations (4) and (9). Next, the process proceeds to decision step 68, where it is determined whether the row being scanned is still within the optical black area. In the preferred embodiment, shield 48 dims the first four rows of pixels and the information from row / column information register 46 indicates whether the row being scanned is from one of the dimmed rows. . If the row being scanned is from one of the darkened rows, the process loops back to decision step 62 for the next row, until scanning proceeds to the undarkened row. The loop repeats. If it is determined in decision step 68 that the scan is no longer in the darkened row, processing proceeds to step 69. At this point, V _REF is frozen and the remainder of the frame row is scanned and analyzed until the end of the frame is reached, as indicated by decision step 70. When the end of the frame is reached, processing proceeds to step 72, where V _REF is again adjusted. However, instead of trying to optimize the optical black value, V _REF is adjusted to match the characteristics of the entire frame just scanned. To do this, the average luminance value for the pixels that make up the frame (ignoring the optically black pixels that make up the first four rows) is determined, and V _REF is calculated as the average pixel from which the output of ADC 32 was calculated. The value is set to be the median value of the input signal V _sig corresponding to the value.

This concept is illustrated graphically in FIGS. 5a and 5b.
It is shown. FIG. 5a shows the luminance against the elapsed time of the frame.
The values are plotted. FIG. 5b during one frame scan
V _REF3 shows a time chart. The frame in FIG.
For illustrative purposes only and represents a test pattern. This
In the test pattern shown in FIG.
The first four rows of pixels are darkened
After that (as indicated by the sloped portion of the brightness curve 76)
2) As the scan progresses through the frame, the remaining rows
Rise to bright white. Obviously, in the representative image,
Degree intensity varies widely and nonlinearly, but is described here.
The same principle applies as well.

As shown in FIG. 5b, the value of V _REF is initially
It is set to some default value, preferably to the common mode level of the ADC 32. After being the first four rows scanned, as indicated by the change in the value of V _REF at the time T _1, the new value of _VREF at step 66 of FIG. 4 is calculated. Alternatively, the value of V _REF can be updated after each pixel of the darkened row is scanned, or at the end of each darkened row. It should be noted that the latency between the end of the darkened row and the calculation of the value for V _REF is preferably the use of the fast operation allowed by equation (9) and the same chip as the sensor array 6 Minimization is achieved by using the high speed arithmetic logic 8 above. Once the value of V _REF has been determined for the optically black pixel, the value is frozen (step 64 in FIG. 4) and the rest of the frame is scanned as shown between times T ₁ and T _2. Is done.

At time T ₂ , the entire frame is read and a new value of V _REF is calculated based on the actual frame data. The average luminance value for the frame is first calculated, as indicated by point 78 in FIG. 5a. This value is given by equation (4)
Is assigned to the value of V _sig, A by adjusting the V _REF
The output of the DC 32 is set to a value at the center of the range. Preferred 10
For a bit ADC, the value in the middle of this range may be set to 512. ADC output value D _{out in the} center of the range
Is preferably a programmable value that can be selected according to the image being scanned and user preferences. Empirical evidence suggests that for best image enhancement, the ADC output value corresponding to the average luminance intensity 78 is about 75% of the range of the ADC (eg, 768 for a 10-bit ADC). ) Should be set to

At the end of the frame, V _REF is adjusted (step 72 in FIG. 4), as shown at time T ₂ in FIG. 5b,
The process is repeated for the next input frame of the luminance data. At the same time as adjusting V _REF at the end of the frame, the dynamic range of ADC 32 is also maximized by adjusting the gain of amplifier 24. This is explained in more detail in the following paragraphs.

Optimization of ADC Dynamic Range The relationship between the amplifier 24 and the ADC 32 is further illustrated in FIGS. 6a to 6d. Also in this case, in the illustrated test pattern, the frame gradually and uniformly changes from black to white as going from top to bottom (scanning direction). FIG.
Denotes the input of the amplifier 24 for scanning one whole frame. FIG. 6b shows the corresponding differential output 25 from the amplifier 24,
27 is shown. Note that V _REF is shown at the end of the first four rows as already adjusted for optical black calibration. Therefore, it should be noted is that the very close some or it below the threshold V _B of ADC32 as lower component 27 of the differential output signal is shown. However, it should also be noted that the differential output signals 25, 27 do not utilize the entire range of the ADC 32. To use the entire range of ADC 32, its input (in this case, differential outputs 25, 27 from amplifier 24) must change over its entire operating range, ie, from V _B to V _T. In this way, the contrast of the resulting image is enhanced.

Further, it is advantageous to calibrate the system so that the average image data is provided at or near the center of the ADC. These advantages are achieved as follows.

After the frame has been read, the average of the frame
A luminance value is calculated. This average luminance value 80 is shown in FIG.
Have been. FIG. 6c also shows the differential output 25 of the amplifier 24,
27 is shown. Average brightness value, ie avg_brt is calculated
The input luminance value V equal to the average luminance value_sigAgainst
Output of amplifier 24 drives ADC 32 to the center of its range
V_REFCan be adjusted. This is the figure
6c. As shown in FIG.
By shifting the symbols 25 and 27 upward, the average luminance value becomes A
DC32 common mode level, ie the level in the middle of the range
(For clarity, one of the differential output signals 25, 27)
Only one component 27 is shown). Preferably, the difference
By shifting the dynamic output signals 25 and 27 upward, the average brightness
V value _TAbout 75% of In this way, usually
The brighter areas of the image, the area of most interest,
Will be strengthened. In another alternative, the average luminance value is
Can be shifted anywhere in the range. This variability is
Reached through the use of user-programmable registers
Is done. Note that Figure 6c is for illustration only
Which corresponds to the actual output signal from the amplifier 24.
It does not respond. Figure shows first frame read
V after_REFAdjusting the next frame of data
It only shows the expected results).

The differential output signals 25, 27 are expanded to cover the entire range (or practical size) of the ADC 32 by increasing the gain of the amplifier 24. By increasing the gain in this manner, the slope of the differential outputs 25, 27 is adjusted as shown in FIG. 6d. FIG. 7 shows the details of the gain adjustment.

FIG. 7a is a flowchart illustrating a method of adjusting the differential output 25, 27 to the range of the ADC 32 for the luminance signal of the last scanned frame by adjusting the gain of the amplifier 24. The contrast is improved by using the gain calculated for the previous frame, since the next frame will have similar luminance values. In a first determination step 90, it is determined whether a chip reset has occurred. If so, the process proceeds to step 92, where the gain factor is set to a value stored in a register or other memory source. The gain factor is a 3-bit value, ie, 0 to 7. This is Figure 7
This corresponds to the gain of the amplifier 24 as shown in FIG. In the preferred embodiment, amplifier 24 imposes a 1X, 2X, 4X, 8X, or 16X gain. If a chip reset did not occur, the process proceeds to step 94, where it is determined whether the imaging logic is operating in a user controlled mode, ie, the automatic image intensifier function has been disabled. In that case, processing proceeds to step 92, where the gain factor is set to a value stored in a register or other memory source. Note that the value can be a pre-programmed default value or a value entered by a user of the system.

Assuming that the user does not disable the automatic gain, the process proceeds to decision step 96, where the system temporarily disables the automatic gain control function so that the system time can be stabilized after the integration interval has been adjusted. It is determined whether it has been disabled. If so, block 9
As shown in FIG. 8, the gain coefficient is not changed, and the process is stopped. If automatic gain control is enabled,
The process proceeds to decision step 100 where it is determined whether the entire frame has been scanned. Otherwise, as shown in step 101, the gain factor is not changed. If the end of the frame has been reached, as indicated by the end of the frame signal from row / column information register 45, the process proceeds to decision step 102 where the average luminance value is calculated. Next, this average luminance value is compared with a preset threshold value. As previously described, this preset threshold may correspond to the center of the ADC 32 range, or more preferably, to a range of 75%.

If the average luminance value is greater than a preset threshold, this indicates that the image is too bright, and the gain should be adjusted downward. In decision step 104, the gain factor corresponding to the minimum gain value of 2 × 2
It is determined whether: If the gain factor is greater than two, indicating that the gain of the amplifier 24 can be adjusted down, processing proceeds to step 108, where the gain factor is reduced by one (decremented). As can be seen from FIG. 7b, reducing the gain factor by one reduces the gain of amplifier 24 by half (gain factors of 3, 4,.
Or 5).

On the other hand, if it is determined in the determination step 102 that the average luminance is lower than the threshold value, the process reaches the second determination step 110. In the determination step 110, it is determined whether the threshold value is larger than twice the average luminance value. As previously explained, the gain of amplifier 24 can only be adjusted in multiples of two. Thus, if the threshold luminance value is less than or equal to twice the current average luminance, there is no reason to double the gain, and the gain coefficient remains unchanged as shown in step 112. Conversely, if the gain can be doubled (ie, if the threshold is greater than twice the current average luminance), processing proceeds to decision step 114, where the gain is already at its maximum gain value of 16 (Amplifier 24 is limited to a maximum gain of 16 as previously described). If the gain has not already reached its maximum value, the gain factor is increased by 1 (incremented) at step 118. If the gain has already reached its maximum value, the gain factor is set to five. This keeps the gain at its maximum value,
If the next frame image is much brighter (ie,
The gain can be halved to 8 in one step (if the process goes to step 108 when calculating the gain for the next frame).

As previously described, the gain of amplifier 24 can only be adjusted in multiples of two. More precise adjustment when adjusting the dynamic range of the ADC 32 can be obtained by adjusting the integration time for each frame, that is, the irradiation time. As the integration time increases, the input pixel signal V _sig increases proportionally. From the balance of the ADC input, this is equivalent to increasing the gain of the amplifier 24. However, it can be adjusted in finer increments compared to doubling or halving. In the preferred embodiment, a 5-bit integration coefficient corresponding to a value between 0 and 31 is used. Therefore, the integration cycle can be adjusted in 1/32 increments of the frame cycle. The frame period is preferably a programmable value. Preferably, the frame period is programmable from 3 frames per second to over 100 frames per second. In the preferred embodiment, the default value is 30 frames per second.

FIG. 8 is a flowchart illustrating a preferred process for adjusting the integration period. In the preferred embodiment, this adjustment is made immediately after the gain adjustment shown in FIG. 7a.
In a first decision step 130, it is determined whether the system has been reset. When the system is reset, the integration coefficient value is retrieved from the integration period register. In the preferred embodiment, the integration period value is set to 16 by default. Similarly, if it is determined in the determination step 134 that the user has bypassed the automatic integration time control, the value is retrieved from the integration period register in step 132.

At decision step 136, automatic gain control has been enabled (ie, automatic gain control has been enabled to allow system time to stabilize since the integration period was last adjusted), and It is determined whether the end of the frame has been reached. Otherwise, the integral remains unchanged, as shown in step 138. If so, processing proceeds to decision step 140, where the average luminance value is compared to a threshold. If the threshold is greater than the average luminance, indicating that the integration period should be increased, the process proceeds to decision step 142 where it is determined whether the integration period has already reached its maximum value. If not,
Since the integration value is incremented by one, as indicated by step 144, the integration period for the next frame is increased.

If the integrated value is at the maximum, the gain value of the amplifier 24 is checked at decision step 146. If the gain value is less than 16, indicating that the gain can be adjusted, step 148 restores the integrated value from the integration period register. The reason is that if the integration period is at its maximum but the gain is not at its maximum, the gain can be doubled after the next frame. Leaving the integral at its maximum value will probably overshoot the desired threshold by doubling the gain in the next frame. Conversely, if the gain value has already reached its maximum value, the process proceeds to step 150, where the integral value remains at that maximum value. This represents a situation where the image is very dark and the integral has been adjusted so that it is as high as the system allows.

Returning to decision step 140, if the average luminance value is greater than or equal to the threshold, this indicates that the integration period may need to be decremented. Processing proceeds to step 152, where it is determined whether the average luminance is greater than a threshold. If the result of this step is negative, this means that the average luminance is equal to the threshold (both decision 1
40, 142), and the integration value is not changed, as shown in step 138. Conversely, if the average luminance value is greater than the threshold (indicating the need to decrement the integration period), the process proceeds to decision step 154 where it is determined whether the integration period has already reached its minimum value. If not, the integral is decremented at step 156.

If the integration period has already reached its minimum value, the process proceeds to decision step 158 where it is determined whether the gain of amplifier 24 is at its minimum value.
If the integral is already at that endpoint, as described above for step 142, the gain may be further adjusted. However, if the gain has also reached its minimum value, indicating that no further adjustments can be made, the integration period is not changed, as shown in step 160. If the gain is greater than its minimum value, indicating that further adjustments can be made, then at step 162 it is stored in the integration period register, with the expectation that the gain value will be halved at the end of the next frame. The set integration period value is loaded.

FIG. 6d shows the ideal differential output 2 of amplifier 24 after adjustment of V _REF , the gain of amplifier 24, and the integration period.
5 and 27 are shown. In fact, by the time the new reference voltage, gain, and integration period are calculated, the frame under consideration will have already passed through ADC 32. However, in most cases, the next frame will be similar, so the adjusted value will give the best possible resolution.

Optional Brightness Resolution Enhancements FIGS. 9a and 9b illustrate another advantageous feature of the preferred embodiment. Selective brightness resolution enhancement allows the end user to specify portions of the brightness range for enhancement. FIG. 9a shows a typical luminance response of the system. For an optically black pixel 170, the minimum code is output from the ADC 32 (eg, 64 in the preferred embodiment), while for a perfectly bright pixel, the maximum code is output (for a 10-bit ADC, for example). 1024).
Between the darkest and lightest pixels, ADC 32 provides 1024 increments of luminance variation.

However, for the moment, it is assumed that the user is only interested in certain parts of the luminance spectrum. As an example, consider an image of an illuminated incandescent bulb on a dark surface. The brightness value of the brightest pixel encoded with the maximum code (1023) can be many orders of magnitude higher than the luminance value of the darkest pixel in the image encoded with the minimum code (62). Due to the large variations in the luminance values digitized to one of the 1024 values, much of the image detail is necessarily lost.

Assume that only a part of the actual image is of interest, for example the filament of an incandescent lamp. clearly,
The group of pixels corresponding to the filament is the pixel 176 in FIG.
And 178, the center of which is the upper end of the luminance spectrum. This portion of the spectrum may be encoded with perhaps 500, or 300, or less digital increments.

In FIG. 9b, the desired portion of the spectrum has been expanded to cover the entire range of 64 to 1023 ADC outputs. At this time, the boundary pixel 176 has the minimum output code, and the boundary pixel 178 has the maximum output code. Thus, this portion of the entire spectrum is now represented by 1024 digital levels, while the original image is represented by 500, or 300, or less. As is apparent from FIG.
Any pixel with a luminance value less than the luminance value of 76 appears as black, and any pixel with a luminance value greater than the luminance value of pixel 178 appears as bright white. Thus, no detail or resolution appears outside the portion of the luminance spectrum defined by pixels 176 and 178.

The automatic gain control and optical black calibration described above must be disabled to achieve advantageous features. The input pixel signal V _sig has a pixel value of 176
When the ADC 32 has the minimum code (for example, 64)
By adjusting V _REF to output _{?, The} lower boundary for the desired portion of the spectrum can be defined. The user then manually adjusts the gain, integration time, and luminance voltage so that the luminance range between pixels 176 and 178 is mapped to the entire dynamic range of ADC 32.

While the invention has been described with reference to illustrative embodiments, this description is not to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. For example, while the circuits and systems of the preferred embodiment are embodied in combinatorial logic using a CMOS fabrication process, other fabrication processes are explicitly contemplated. Furthermore, the functions described may be implemented using a general-purpose microprocessor or digital signal processor that executes instructions stored in memory. As those skilled in the art will appreciate, the teachings contained herein apply equally to black and white and color image processing, and still and moving image imaging. The functions described may be performed on a frame-by-frame basis, or on selected frames, or on all frames or portions of selected frames. Various other modifications and embodiments will be apparent to those skilled in the art. It is therefore contemplated that the appended claims will cover any such modifications or embodiments.

This application is hereby incorporated by reference as of March 15, 1999.
Claim the benefit of U.S. Provisional Patent Application 60 / 124,538, filed on even date.

This application is filed concurrently with the present application and is hereby incorporated by reference, and is hereby incorporated by reference, and is assigned to the same assignee as co-pending application Ser. No. 60 / 124,408. , “Defective Pixel Filtering for Digital Imagers” (Defective
Pixel Filtering for Digit
al Images) (agent file number TI-2)
9034).

With respect to the above description, the following items are further disclosed. (1) a programmable amplifier having a reference voltage input, a signal input, a programmable gain value, and a differential output coupled to an analog-to-digital converter (ADC);
An automatic gain control method for an image processor having an analog-to-digital converter for outputting a digital code corresponding to an output of a programmable amplifier, comprising: reading a frame of luminance data; Determining the digital code output from the ADC corresponding to the value; and calculating a reference voltage that causes the digital code output from the ADC to reach a target value when the input of the programmable amplifier is set to the average luminance value. Calculating the gain so that the digital code output from the ADC is at the target value when the input of the programmable amplifier is set to the average luminance value; and converting the reference voltage and the gain to the calculated value. Setting and reading out the next frame.

(2) The automatic gain control method according to (1), further comprising: reading out an optically black portion of a frame whose luminance value is a known luminance reference value; Calculating a reference voltage that sets the output of the ADC to a desired minimum value when is set to a known reference value.

(3) The automatic gain control method according to item 2, wherein the steps are automatically performed at the beginning of each frame. (4) The automatic gain control method according to (1), wherein automatically determining an average luminance value after each frame is read, calculating a reference voltage, and calculating a gain. Setting the reference voltage and the gain to the calculated values.

(5) The automatic gain control method according to (1), wherein (1) a digital code output from the ADC when the signal input of the programmable amplifier is set to the average luminance value, and (2) a digital code output from the ADC. An automatic gain control method in which a gain is calculated from a difference from an output predetermined digital code. (6) The automatic gain control method according to (1), wherein the ADC
Wherein the predetermined output is the center of the range of ADC output values. (7) The automatic gain control method according to (1), wherein the ADC
Wherein the predetermined output is 75% of the maximum ADC output value.

(8) The automatic gain control method according to (1), wherein the luminance data covers a range of luminance values, and further selecting a part of the range of luminance values for enhancement. A selection step in which the portion has a minimum desired luminance value and a maximum desired luminance value; and A when the signal input of the programmable amplifier is the maximum desired luminance value.
The reference is set so that the digital code output from the DC has its maximum value, and the digital code output from the ADC has its minimum value when the signal input of the programmable amplifier has the minimum desired luminance value. Adjusting the voltage and the gain.

(9) An image processor, which receives a luminance signal and a reference voltage signal as inputs and outputs an amplified differential signal, and receives the amplified differential signal as inputs, A differential analog-to-digital converter (ADC) for outputting a digital signal corresponding to the amplified differential signal, a programmable voltage source for outputting the reference voltage signal, and receiving the digital signal and outputting an average luminance value A digital averager that receives the average luminance value, outputs a gain control signal to the differential amplifier, and outputs a reference voltage control signal to the programmable voltage source. From the difference between the digital signal of the analog-to-digital converter when the input is at the average luminance value and (2) the desired digital signal, the gain control signal and the Image processor and a digital signal controller and the reference voltage control signal is determined.

(10) An automatic gain control circuit which receives a frame of a luminance signal and a reference voltage signal as inputs, outputs a differential signal corresponding to the difference between the luminance signal and the reference voltage signal, and An amplifier that amplifies the difference under control, and a differential analog that receives a signal output from the amplifier and outputs a digital signal corresponding to the differential output of the amplifier.
A digital converter (ADC), means for calculating an average luminance value for the frame, and comparing the digital signal output from the ADC with a desired digital output when the luminance signal input of the amplifier is at the average luminance value. An automatic gain comprising means for generating a difference signal, means for adjusting a reference voltage signal in response to the difference signal, and means for adjusting a gain control signal in response to the difference signal. Control circuit.

(11) By calibrating the reference voltage and gain of the differential amplifier and the integration period so as to provide the ADC with an input utilizing the entire dynamic range of the differential analog-to-digital converter (ADC), Augmentation is achieved automatically. When used with CMOS arrays, imaging logic can be fabricated on a single chip with arrays that use combinational logic for fast and inexpensive calibration. Another convenient feature is:
By enlarging the desired portion of the luminance spectrum of the image, the digital resolution of the resulting image for that portion of the spectrum of interest can be increased.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a digital imaging device that can use a preferred embodiment of the present invention.

FIG. 2 is a block diagram of the single-chip CMOS imager of the preferred embodiment.

FIG. 3 is a block diagram of the amplifier and analog-to-digital converter of the preferred embodiment.

FIG. 4 is a flowchart for reference voltage adjustment.

5 graphically illustrates certain concepts of the preferred embodiment, where a is the output of the preferred embodiment amplifier and b is a timing diagram for a reference voltage. FIG.

6 shows the input and output of the amplifier of the preferred embodiment when the reference voltage and gain are adjusted, wherein a shows the input of the amplifier for a scan of an entire frame, and b shows the corresponding difference of the amplifier. FIG. 3C shows a dynamic output, FIG.
FIG. 9 is a diagram showing that the slope of the differential output is adjusted by increasing the gain.

FIGS. 7A and 7B are diagrams showing the details of the gain adjustment, wherein a is a flowchart for the gain adjustment, and b is a diagram showing the relationship between the gain coefficient and the programmable gain of the amplifier of the preferred embodiment. .

FIG. 8 is a flowchart for adjusting an integration period.

FIG. 9 illustrates the advantageous features of the preferred embodiment, wherein a shows the entire luminance spectrum of the image, and b shows the analog of the preferred embodiment,
FIG. 4 is a diagram illustrating a state where the entirety of the dynamic range of the digital converter is expanded.

[Explanation of symbols]

 2 Digital Imaging Apparatus 6 Sensor Array 8 Imaging Logic 24 Programmable Gain Differential Amplifier 26 Reference Control Block 28 Digital Signal Controller 30 Gain Control Block 32 Differential Analog-to-Digital Converter 38 Digital Averaging

 ──────────────────────────────────────────────────続 き Continuing the front page (72) Inventor Stephen Derek Krines Abel Dene Drive, Texas, Allen, USA 1222 (72) Inventor Henri Rhu, USA Texas, Plano, Porte Lane 4804

Claims (2)

[Claims] 1. A reference voltage input, a signal input, a programmable gain value, and an analog-to-digital converter (AD).
An automatic gain control method for an image processor comprising: a programmable amplifier having a differential output coupled to C); and an analog-to-digital converter for outputting a digital code corresponding to the output of the programmable amplifier. Reading the frame of data; determining the average luminance value of the frame and the digital code output from the ADC corresponding to the average luminance value; and determining the average luminance value from the ADC when the input of the programmable amplifier is set to the average luminance value. Calculating a reference voltage that causes the output digital code to have the target value; and setting the digital code output from the ADC to the target value when the input of the programmable amplifier is set to the average luminance value. Calculating the gain, setting the reference voltage and gain to the calculated values, Reading out the frames of the image processor. 2. An image processor, comprising: a differential amplifier for receiving a luminance signal and a reference voltage signal as inputs and outputting an amplified differential signal; and receiving the amplified differential signal as an input, A differential analog-to-digital converter (ADC) that outputs a digital signal corresponding to the obtained differential signal, a programmable voltage source that outputs the reference voltage signal, and receives the digital signal and outputs an average luminance value A digital averager, receiving the average luminance value, outputting a gain control signal to the differential amplifier, and outputting a reference voltage control signal to the programmable voltage source, (1)
A digital signal controller for determining the gain control signal and the reference voltage control signal from the difference between the digital signal of the analog-to-digital converter when the luminance input is at the average luminance value and (2) the desired digital signal. Image processor.