JP2000292497A - Semiconductor integrated circuit apparatus and method for measuring pulse - Google Patents

Abstract

PROBLEM TO BE SOLVED: To highly accurately measure a pulse width of internally generated pulse signals in a simple circuit constitution. SOLUTION: Outputs of AND circuits 11 and 12, OR circuits 14 and 15, AND circuits 17-20 and NAND circuits 22 and 23 set to a write pulse generation circuit 4 are controlled by decode signals DS0-DS9 of a diagnosis control decoder CD, thereby forming each oscillation loop of a single route in the write pulse generation circuit 4. Oscillation waveforms outputted from the formed oscillation loops are measured, and a pulse width generated by the write pulse generation circuit, 4 is calculated from a cycle of the oscillation waveforms. A data write pulse WP can be easily evaluated accordingly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stable operation technique for a semiconductor integrated circuit device, and more particularly to a technique effective when applied to an evaluation technique for an internally generated clock signal.

[0002]

2. Description of the Related Art As a technique for measuring the delay time of a signal in a logic circuit of a semiconductor integrated circuit device, the inventors of the present invention have studied a technique of connecting an input section and an output section of a logic circuit to an oscillation loop. There is a method of determining the delay time of a signal by forming the signal and measuring the oscillation frequency.

For example, when the frequency of the measured oscillation waveform is f (Hz), 1 / f (second) is the time required to make two rounds of the measured loop logic circuit. , 1 / f / 2 (seconds).

Examples of this type of semiconductor integrated circuit device delay time measurement technology are described in detail in the September 29, 1987, published by Nikkan Kogyo Shimbun, CMOS Device Handbook Editing Committee (ed.) There are "CMOS Device Handbook" P564 to P569, and this document describes a method for calculating a delay time in a logic circuit.

[0005]

However, it has been found by the present inventors that the following problems are encountered in the technique for measuring the delay time in the semiconductor integrated circuit device as described above.

That is, in order to measure the oscillation frequency, it is necessary to oscillate the circuit by applying negative feedback to the circuit, so that the loop formed must be a single path. However, an accurate oscillation waveform cannot be obtained with a configuration of a logic circuit having a plurality of oscillation loops, such as an internal clock generation circuit for generating an internal clock signal provided in a memory or the like.

[0007] Therefore, it is impossible to evaluate the semiconductor integrated circuit device at the time of product shipment or the like, and there is a possibility that the operation cycle performance and the data write characteristic are greatly affected.

It is an object of the present invention to provide a semiconductor integrated circuit device capable of measuring the pulse width of an internally generated pulse signal with a simple circuit configuration and with high accuracy.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the semiconductor integrated circuit device of the present invention, an internal pulse signal is generated from an input clock signal, and a signal output is controlled based on a first control signal. A pulse generation control unit formed on each of the signal paths, and an input unit and an output unit of the pulse generation control unit are connected based on the second control signal, and a single unit formed on the pulse generation control unit is connected. And a signal path control unit for forming an oscillation loop by the signal path of (1).

Further, in the semiconductor integrated circuit device according to the present invention, the pulse signal generating means is provided with a control signal generating section for generating first and second control signals to be output to a pulse generation control section and a signal path control section. It is a thing.

Further, the semiconductor integrated circuit device of the present invention
The internal pulse signal generated in the pulse generation control unit,
It consists of an internal clock signal.

Further, the semiconductor integrated circuit device of the present invention generates a pulse signal from an input clock signal, controls signal output based on a first control signal, and connects a plurality of signal paths to a single signal path. A pulse generation control unit formed on each of the signal paths, an extended pulse signal generated by expanding the pulse signal generated by the pulse generation control unit based on the pulse control signal, and a signal output based on the third control signal And a pulse expansion unit that forms a plurality of signal paths into a single signal path, an input unit of the pulse generation control unit based on a second control signal, and an output unit of the pulse expansion unit. And a signal path control unit for switching and controlling the signal path so as to form an oscillation loop.

Further, the semiconductor integrated circuit device according to the present invention
A control signal generating unit configured to generate a first control signal to be output to a pulse generation control unit, a pulse control signal to be output to a pulse expansion unit, and a second control signal to be output to a signal path control unit; Is provided.

Further, in the semiconductor integrated circuit device according to the present invention, the expansion pulse signal generated in the pulse expansion unit comprises a data write pulse used when writing data.

Further, according to the pulse measuring method of the present invention, a plurality of signal paths in a pulse generation control unit for generating an internal pulse signal from an input clock signal are controlled to be switched, so that an oscillation loop with a single signal path is controlled. The oscillation frequency of each oscillation loop is measured, and the pulse width of the pulse signal generated by the pulse signal generation means is calculated from the cycle of the oscillation frequency.

Further, according to the pulse measuring method of the present invention, a pulse generation control section for generating a pulse signal from an input clock signal, and an expanded pulse signal generated by expanding the pulse signal generated by the pulse generation control section are generated. A plurality of signal paths in the pulse expansion unit are formed in oscillation loops with a single signal path by switching control, and the oscillation frequency of each oscillation loop is measured. The pulse width of the pulse signal generated by the generation means is calculated.

As described above, the pulse width of the pulse signal generated by the pulse signal generation means can be measured with high accuracy and easily, so that the evaluation of the pulse signal at the time of product shipping inspection or failure analysis can be performed. Can be easier.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of a memory provided in a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 3 is an explanatory diagram when the write pulse generation circuit according to the embodiment of the present invention generates the pulse width tw0, and FIG. 3 is a diagram when the write pulse generation circuit according to the embodiment of the present invention generates the pulse width tw1. FIG. 4 is an explanatory diagram when a write pulse generation circuit according to an embodiment of the present invention generates a pulse width tw2, and FIG. 5 is a diagram in which a write pulse generation circuit according to an embodiment of the present invention uses a pulse. Width tw3
FIG. 6 to FIG. 10 are explanatory diagrams when the write pulse generation circuit according to the embodiment of the present invention forms oscillation loops with different signal paths.

In the present embodiment, the semiconductor integrated circuit device 1 comprises a microcomputer and an SRAM (Stati
c Random Access Memory), and is used for, for example, an electronic computer.

The microcomputer has a CPU (Cen).
(Tral Processing Unit), CPU control, serial interface, timer, and other general circuit blocks.

The memory 2 includes a general peripheral circuit 3 including a memory cell array, a column (column) address decoder, a column address buffer, a sense amplifier, a row (row) address decoder, a row address buffer, etc., and a write pulse generation circuit. (Pulse signal generation means) 4, a clock pulse generation circuit 5, and buffers 6 to 10.

The write pulse generation circuit 4 includes the peripheral circuit 3
A data write pulse (expansion pulse signal) WP to be used when writing data to the memory cell array is generated. The clock pulse generation circuit 5 generates a signal synchronized with a clock signal CLK input from the outside, and generates an internal clock signal CLKi that is a basis of the operation of the memory 1.

The buffers 6 to 10 are provided with address signals AD,
The input data DIN, the write enable signal WE, the output data DOUT and the like are transferred at the timing of the internal clock signal CLKi.

The write pulse generation circuit 4 includes a diagnosis control decoder (control signal generation unit) CD and a write pulse generation unit WPS. The diagnostic control decoder CD, for example, decode signals (first control signals) DS0, DS1, DS9 and a decode signal (second control signal) based on a diagnostic control signal output from CPU control or the like.
, And decode signals (pulse control signals) DS5 to DS8.

Further, these decode signals DS0-DS
9 are not generated by the diagnostic control decoder CD, for example, the decode signal DS directly from an external input pin.
0 to DS9 may be input.

The write pulse generator WPS includes AND circuits 11 and 12, OR circuits 13 to 15, and AND circuit 17
, An OR circuit 21, NAND circuits 22, 23,
It comprises delay gates 24-27. AND circuits 11 and 12, OR circuits 13 to 15, AND circuit 17 to
20, the NAND circuits 22 and 23 have two inputs, the AND circuit 16 has three inputs, and the OR circuit 21 has four inputs. The delay gate 24 outputs an inverted signal of the input signal, and the delay gates 25 to 27 output signals of the same level as the input signal.

The AND circuits 11 and 12, the OR circuit 14,
15, decode circuits DS0 to DS9 output from the diagnostic control decoder CD are input to the other input units of the AND circuits 17 to 20, the NAND circuit 22, and one input unit of the NAND circuit 23, respectively. Connected to be.

One input of the AND circuit 12 has an internal clock signal CL generated by the clock pulse generation circuit 5.
It is connected so that Ki can be input. AND circuit 1
1 is connected to the output of the NAND circuit 23, and the output of the NAND circuit 23 is
This is an output section of the signal waveform, and the waveform is monitored.

The output of the AND circuit 11 has an OR circuit 1
3 is connected to one input, and the output of the AND circuit 12 is connected to the other input of the OR circuit 13. The output of the OR circuit 13 has a delay gate 24
And one input of the OR circuit 15 are connected.

The output of the delay gate 24 is connected to one of the inputs of the OR circuit 14 and the NAND circuit 22, respectively. Output units of the OR circuits 14 and 15 and the NAND circuit 22 are connected to respective input units of the AND circuit 16. The output of the AND circuit 16 includes:
The delay gate 25 and one input of the AND circuit 17 are connected.

The input of the delay gate 26 and one input of the AND circuit 18 are connected to the output of the delay gate 25. The output of the delay gate 26 has a delay gate 2
7 and one input of the AND circuit 19 are connected, and the output of the delay gate 27 is connected to the AND circuit 20.
Are connected.

The outputs of the AND circuits 17 to 20 are connected to the respective inputs of the OR circuit 21. The output of the OR circuit 21 is connected to the other end of the NAND circuit 23. Are connected. OR circuit 21
Is also the output of the write pulse generation circuit 4, and the output of the OR circuit 21 outputs the data write pulse WP.

The signal path control unit S is operated by the AND circuits 11, 12, the OR circuit 13, and the NAND circuit 23.
KC is configured. Also, OR circuits 14, 15,
AND circuit 16, NAND circuit 22, delay gate 24
Constitutes a pulse generation control unit PB. The AND circuits 17 to 20, the OR circuit 21, the delay gates 25 to
27 constitutes a pulse expansion unit PD.

Next, the operation of the present embodiment will be described.

First, the pulse widths tw0 to tw3 generated by the write pulse generation circuit 4 will be described.

When the minimum pulse width tw0 is to be generated, as shown in FIG.
00 'is output.

As a result, the signal path shown by the bold line in FIG. 2 is formed, and the pulse signal generated by the pulse generation control unit PB is output without passing through the delay gate of the pulse expansion unit PD. The data write pulse WP having the minimum pulse width tw0 is output.

When a pulse width tw1 larger than the minimum pulse width tw0 is generated, as shown in FIG.
9 is output so as to become '0100011000'.

Accordingly, a signal path shown by a thick line in FIG. 3 is formed. The pulse signal generated by the pulse generation control unit PB is output via a delay gate 25 provided in the pulse expansion unit PD.

The data write pulse WP having a pulse width tw1 larger than the pulse width tw0 due to the delay time of the delay gate 25 is applied to the write pulse generation circuit 4.
Will be output.

Further, when generating a pulse width tw2 larger than the pulse width tw1, as shown in FIG. 4, the diagnostic control decoder CD outputs the decode signals DS0 to DS9.
Is output as '0100011100', and a signal path indicated by a thick line is formed.

The pulse signal generated by the pulse generation control unit PB is applied to the delay gates 25 and 2 of the pulse expansion unit PD.
6 is output. The data write pulse WP having the pulse width tw2 larger than the pulse width tw1 due to the delay times of the delay gates 25 and 26 is output from the write pulse generation circuit 4.

The pulse width tw having the largest pulse width is
3, the decode signals DS0 to DS9 are output from the diagnostic control decoder CD as' 010, as shown in FIG.
0011110 '.

Therefore, the signal path shown by the bold line in FIG. 5 is formed, and the pulse signal generated by the pulse generation control unit PB is passed through the delay gates 25 to 27 provided in the pulse expansion unit PD. Is output.

The data write pulse WP having the maximum pulse width tw3 by being output through all the delay gates 25 to 27 becomes the write pulse generation circuit 4
Will be output.

Next, a case where a single-path oscillation loop for measuring an oscillation waveform in the write pulse generation circuit 4 is formed will be described.

When the oscillation frequency measurement mode is set,
As shown in FIGS. 6 to 10, five oscillation loops are formed.

As shown in FIG. 6, the first oscillation loop includes a decode signal DS0 from the diagnostic control decoder CD.
To DS9 become '1010010001'. As a result, a signal path shown by a thick line in FIG. 6 is formed.

The pulse signal generated without passing through the delay gate 24 in the pulse generation control unit PB is output to the pulse expansion unit PD and output without passing through all the delay gates 25 to 27 of the pulse expansion unit PD. . The cycle of the oscillation waveform obtained by the signal path of the oscillation loop is defined as cycle tα.

As a second oscillation loop, FIG.
As shown in (1), the decode signals DS0 to DS9 are output from the diagnostic control decoder CD so as to be '1011110001'.

As a result, a signal path shown by a bold line in FIG. 7 is formed, and the pulse signal generated through the delay gate 24 in the pulse generation control unit PB is changed to the pulse expansion unit PB.
D is output.

The pulse signal output from the pulse generation control section PB is output without passing through all the delay gates 25 to 27 of the pulse expansion section PD. The cycle of the oscillation waveform obtained by the signal path of this oscillation loop is defined as cycle tβ
And

As shown in FIG. 8, the third oscillation loop includes a decode signal DS0 from the diagnostic control decoder CD.
.. DS9 are output so as to be “1010001001”, and a signal path indicated by a thick line is formed.

Thus, the pulse signal generated without passing through the delay gate 24 in the pulse generation control unit PB is output through the delay gate 25 of the pulse expansion unit PD. The cycle of the oscillation waveform obtained by the signal path of this oscillation loop is defined as cycle tγ.

As shown in FIG. 9, the fourth oscillation loop includes a decode signal DS0 from the diagnostic control decoder CD.
To DS9 become '1010000101', and a signal path shown by a thick line is formed.

Thus, the pulse signal generated without passing through the delay gate 24 in the pulse generation control unit PB is output through the delay gates 25 and 26 of the pulse expansion unit PD. The cycle of the oscillation waveform obtained by the signal path of this oscillation loop is defined as cycle tδ.

Further, as the fifth oscillation loop, as shown in FIG. 10, the decode signals DS0 to DS9 are output from the diagnostic control decoder CD so as to be '1010000011', and a signal path shown by a thick line is formed. .

As a result, the pulse signal generated without passing through the delay gate 24 in the pulse generation control unit PB is applied to all the delay gates 25 to 27 of the pulse expansion unit PD.
Is output via. The cycle of the oscillation waveform obtained by the signal path of this oscillation loop is defined as cycle tε.

Then, the pulse widths tw0 to tw of the data write pulse WP generated by the write pulse generation circuit 4
3 can be obtained from the periods tα, tβ, tγ, tδ, and tε of the oscillation waveforms measured in the five oscillation loops by using the following equation.

Tw0 = {(tβ / 2) − (tα / 2)} (Equation 1) tw1 = {(tβ / 2) − (tα / 2)} + ｛(tγ / 2) − (tα / 2) {(Equation 2) tw2 = {(tβ / 2) − (tα / 2)} + {(tδ / 2) − (tα / 2)} (Equation 3) tw3 = ｛(tβ / 2) − (tα / 2) ｛+ ｛(tε / 2)-(tα / 2) 式 (Equation 4) In this embodiment, the pulse width of the data write pulse WP generated by the write pulse generation circuit 4 can be adjusted with high accuracy. In addition, since the measurement can be easily performed, the evaluation of the data write pulse WP at the time of a product inspection or the like can be easily performed.

Further, since the pulse width of the data write pulse WP can be variably controlled, it is possible to generate a pulse width of the data write pulse WP that satisfies the operation cycle performance and the data write characteristics.

Further, in the present embodiment, the variable control of the pulse width in the write pulse generation circuit 4 and the formation of the single-path oscillation loop have been described.
A signal path control unit may also be provided in a clock pulse generation circuit that generates an internal clock signal CLKi that is an internal pulse signal.

In this case, the clock pulse generation circuit (pulse signal generation means) 5a is composed of a diagnosis control decoder CDa, a signal path control unit SKC1, and a pulse generation control unit PB1, as shown in FIG. .

From the diagnostic control decoder CDa, decode signals (second control signals) DS10, DS11, DS1
5. Decode signals (first control signals) DS12 to DS1
4 is output. The signal path control unit SKC1, like the signal path control unit SKC in the present embodiment, includes AND circuits 11, 12, an OR circuit 13, and a NAND circuit 23, and the pulse generation control unit PB1 also includes Similarly to the pulse generation control unit PB of the present embodiment, the OR circuit 1
4 and 15, an AND circuit 16, a NAND circuit 22, and a delay gate 24.

The output of the AND circuit 16 is connected to the other input of the NAND circuit 23. AND circuits 11 and 12, OR circuit 14, NOT AND circuit 2
2, the other input of the OR circuit 15, the NAND circuit 2
3 are connected to the decode signals DS10 to DS1.
5 are connected so as to be inputted.

A single-path oscillation loop in the clock pulse generation circuit 5a is formed by each of the decode signals DS10 to DS15 of the diagnostic control decoder CDa, and the oscillation frequency is measured, thereby generating the clock pulse generation circuit 5a. Internal clock signal CLKi
Can be measured with high precision and easily.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

In the above embodiment, a microcomputer provided with an SRAM memory has been described. However, a semiconductor integrated circuit device other than this microcomputer may be used, or a semiconductor integrated circuit device provided with a circuit for generating an internal pulse signal. If so, the pulse width of the generated internal pulse signal can be measured with high accuracy and easily.

[0072]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, even a pulse signal generating means having a plurality of signal paths can form a single signal path and measure the oscillation frequency of its oscillation loop. The pulse width of the pulse signal generated by the means can be measured with high precision and easily.

(2) Further, according to the present invention, the pulse width of the pulse signal generated by the pulse signal generating means can be variably controlled, so that the operation cycle performance and data write characteristics can be stabilized.

(3) Further, in the present invention, by the above (1) and (2), the evaluation of the pulse signal at the time of product shipping inspection or failure analysis can be facilitated.
The reliability of the semiconductor integrated circuit device can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a memory provided in a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram when a write pulse generation circuit according to one embodiment of the present invention generates a pulse width tw0.

FIG. 3 is an explanatory diagram when a write pulse generation circuit according to one embodiment of the present invention generates a pulse width tw1.

FIG. 4 is an explanatory diagram when a write pulse generation circuit according to one embodiment of the present invention generates a pulse width tw2.

FIG. 5 is an explanatory diagram when a write pulse generation circuit according to one embodiment of the present invention generates a pulse width tw3.

FIG. 6 is an explanatory diagram of a signal path in which a frequency output from an oscillation loop formed in a write pulse generation circuit according to one embodiment of the present invention has a period tα.

FIG. 7 is an explanatory diagram of a signal path in which a frequency output from an oscillation loop formed in the write pulse generation circuit according to the embodiment of the present invention has a period tβ.

FIG. 8 is an explanatory diagram of a signal path in which a frequency output from an oscillation loop formed in the write pulse generation circuit according to one embodiment of the present invention has a period tγ.

FIG. 9 is an explanatory diagram of a signal path in which a frequency output from an oscillation loop formed in the write pulse generation circuit according to one embodiment of the present invention has a period tδ.

FIG. 10 is an explanatory diagram of a signal path in which a frequency output from an oscillation loop formed in a write pulse generation circuit according to one embodiment of the present invention has a period tε.

FIG. 11 is a circuit diagram of a clock pulse generation circuit in a memory provided in a semiconductor integrated circuit device according to another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit device 2 Memory 3 Peripheral circuit 4 Write pulse generation circuit (pulse signal generation means) 5 Clock pulse generation circuit 5a Clock pulse generation circuit (Pulse signal generation means) 6-10 Buffer 11, 12 Logical product circuit 13-15 OR circuit 17 to 20 AND circuit 21 OR circuit 22, 23 NAND circuit 24 to 27 Delay gate WPS Write pulse generator CD, CDa Diagnosis control decoder (control signal generator) SKC, SKC1 Signal path controller PB , PB1 pulse generation control unit PD pulse expansion unit DS0, DS1, DS9 decode signal (second control signal) DS2 to DS4 decode signal (first control signal) DS5 to DS8 decode signal (pulse control signal) DS10, DS11, DS15 decode signal (second control signal) D 10~DS15 decoded signal (first control signal) WP data writing pulse (internal pulse signal) CLK clock signal CLKi internal clock signal tw0~tw3 pulse width

Claims (8)

[Claims] 1. A pulse generator for generating an internal pulse signal from an input clock signal and controlling a signal output based on a first control signal to form a plurality of signal paths into a single signal path. A control unit, based on a second control signal, connects an input unit and an output unit of the pulse generation control unit, and forms an oscillation loop with a single signal path formed in the pulse generation control unit. A semiconductor integrated circuit device comprising a pulse signal generating means including a signal path control unit. 2. The semiconductor integrated circuit device according to claim 1, wherein said pulse signal generating means generates first and second control signals to be output to said pulse generation control section and said signal path control section. A semiconductor integrated circuit device comprising a generation unit. 3. The semiconductor integrated circuit device according to claim 1, wherein the internal pulse signal generated by the pulse generation control unit is an internal clock signal. 4. A pulse generation control for generating a pulse signal from an input clock signal and controlling a signal output based on a first control signal to form a plurality of signal paths into a single signal path. A pulse signal generated by the pulse generation control unit based on a pulse control signal to generate an expanded pulse signal; and controlling a signal output based on a third control signal. A pulse expansion unit that forms a single signal path, an input unit of the pulse generation control unit, and an output unit of the pulse expansion unit, based on a second control signal,
A semiconductor integrated circuit device comprising: a pulse signal generation unit including a signal path control unit that controls switching of a signal path so as to form an oscillation loop. 5. The semiconductor integrated circuit device according to claim 4, wherein said pulse signal generation means includes a first control signal output to said pulse generation control section, a pulse control signal output to said pulse expansion section, and A semiconductor integrated circuit device, comprising: a control signal generation unit that generates a second control signal to be output to a signal path control unit. 6. The semiconductor integrated circuit device according to claim 4, wherein the extension pulse signal generated in the pulse extension unit is a data write pulse used when writing data. Integrated circuit device. 7. A plurality of signal paths in a pulse generation control unit for generating an internal pulse signal from an input clock signal are formed into oscillation loops with a single signal path by controlling switching, and each oscillation loop is formed. A pulse width of a pulse signal generated by the pulse signal generation means is calculated from a period of the oscillation frequency for each pulse. 8. A pulse generation control section for generating a pulse signal from an input clock signal, and a plurality of signal paths in a pulse expansion section for generating an expansion pulse signal obtained by expanding the pulse signal generated by the pulse generation control section. Are respectively formed in oscillation loops by a single signal path by switching control, an oscillation frequency in each oscillation loop is measured, and a pulse in a pulse signal generated by the pulse signal generation means from a cycle of the oscillation frequency is measured. A method for measuring a pulse, comprising calculating a width.