JPH11306797A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor memory device in which a high-speed test can be made easily by using a low-speed tester even without using a high- speed tester exceeding 100 MHz. SOLUTION: In a 2-bank 16-Mbit SDRAM which is composed of a memory array bank and its peripheral circuit, a test-mode setting circuit in which a double-cycle-clock generation circuit, an internal-column-command generation circuit, an address arithmetic circuit and a test-data generation circuit are contained is provided. When a command, an address and data are input in the rise of an external clock signal CLK, a command, an address and data can be generated at the inside of a chip when the external clock signal CLK falls. An operating timing which is equivalent to an example in which a test command 'WW6' is input in synchronization with an internal clock signal ICLK, data 'D' is written into an address 'A' in a first cycle, and data '/D' (inverted) is written into an address '/A' (inverted) in a second cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test mode technology for a semiconductor memory device, and more particularly, to a synchronous DRAM (SDRAM) and the like which can cope with a higher operating frequency in a memory operating in synchronization with an external clock signal. The present invention relates to a technology that is effective when applied to a semiconductor memory device.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, in an SDRAM, a technique for checking a specific timing using a test mode such as a DoubleCLK test mode is considered. According to this summary, when a test is performed, all test items are checked in a minimum cycle. Therefore, if the memory becomes faster, it is necessary to prepare a high-speed tester in proportion thereto. However, some items are checked by a low-speed tester using a test mode. For example, in the Double CLK test mode, it is possible to simply input a command and an address when the clock signal rises and falls.

Incidentally, as a technique relating to such a semiconductor memory device such as an SDRAM, for example,
"Advanced Electronics I-9 Ultra LSI Memory" published by Baifukan Co., Ltd. on January 5, P344-P3
48 and the like.

[0004]

In a semiconductor memory device such as the SDRAM described above, when a memory operating at a high speed of, for example, 100 MHz or more is tested, a tester used in a conventional EDODRAM cannot measure. It's getting harder. Also, Double
In the CLK test mode, for example, as shown in FIG. 10, it is necessary to input a command and an address at the time of rising and falling of the external clock signal CLK, and it is conceivable that test restrictions and test pattern complexity increase.

Therefore, an object of the present invention is to input a command, address, and data only at the rising edge of an external clock signal, and to internally generate a command, address, and data even at the falling edge of the external clock signal.
Even without using a high-speed tester that exceeds 00 MHz,
An object of the present invention is to provide a semiconductor memory device that can easily perform a high-speed test even with a low-speed tester.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor memory device according to the present invention is capable of responding to a clock cycle by an external clock signal.
To operate the internal unit twice, simply input a command, address, and data at the rising edge of the external clock signal. , A test mode setting circuit for generating data.

In this configuration, the target to be tested in the shortest cycle is a column command (read / write command). Therefore, considering a combination of these commands, a continuous command is input inside the chip by inputting a single command. The column operation is performed. Also, in consideration of the case where the address and data also change between this cycle and the next cycle, the address is held / incremented / inverted,
Data can be held / inverted in combination. As a method of entering the test mode in the test mode setting circuit, there are a case where a mode register set command is used and a case where a command combined with an address is used.

Therefore, according to the semiconductor memory device, when the external clock signal rises, the command, address,
Command, address, and data are generated inside the chip even when the external clock signal falls just by inputting data, making it possible to easily perform high-speed tests with a low-speed tester compared to the simple Double CLK test mode. become. Thus, the conventional EDO DR can be used without using a high-speed tester exceeding, for example, 100 MHz.
It can be measured with the low-speed tester used for AM. As a result, there are few or no items that need to be measured at high speed. In addition, since it can be mass-produced with existing equipment, testing costs can be reduced.

[0011] In this method, a column command (read / write command) is to be tested in a minimum cycle.
This is because a continuous column operation can be performed inside the chip by one command input. In particular, the present invention can be applied to SDRAMs, SSRAMs, and the like synchronized with an external clock signal.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is an overall block diagram showing a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of a double-period clock signal generating circuit in the semiconductor memory device according to the present embodiment. 3 is a waveform diagram showing a clock signal, FIG. 4 is a timing diagram showing an outline of a test command operation, FIG. 5 is an explanatory diagram showing an example of a test command, and FIGS.
(b) is a timing chart showing an operation example of a test command and an equivalent operation example thereof, FIG. 7 is a timing chart showing a method of entering a test command, FIG. 8 is an explanatory diagram showing an example of an address code, and FIG. FIG. 11 is a timing chart showing another entry method.

First, the configuration of the semiconductor memory device according to the present embodiment will be described with reference to FIG.

The semiconductor memory device according to the present embodiment is, for example, a 2-bank 16-Mbit SDRAM, and has memory array banks 1 and 2, row decoders 3 and 4 corresponding to each of the memory array banks 1 and 2, column decoder 5 and the like. 6, sense amplifier & input / output buses 7, 8 and a common row address buffer 9, column address buffer 10, column address counter 11, refresh counter 12, input buffer 13, output buffer 14, control logic & timing generator 15, etc. And is formed on one semiconductor chip by a well-known semiconductor manufacturing technique.

An address signal Ai is input from the outside to the SDRAM, a row address signal XA and a column address signal YA are generated and input to a row address buffer 9 and a column address buffer 10, respectively. An arbitrary memory cell in memory array banks 1 and 2 is selected via column decoders 5 and 6. The input / output data I / Oi is input via the input buffer 13 during a write operation, and is supplied to the sense amplifier & input / output buses 7 and 8 and the output buffer 14 during a read operation.
Is output via.

The control signals include an external clock signal CLK, a clock enable signal CKE, a chip select signal / CS, a row address strobe signal / RAS,
A column address strobe signal / CAS, a write enable signal / WE, a data mask signal DQM, and the like are input from the outside, and a command and an internal control signal are generated by the control logic & timing generator 15 based on these control signals. The operation of the internal circuit is controlled by an internal control signal.

In particular, the control logic & timing generator 15 in the present embodiment has a built-in test circuit 16 for testing, and this test circuit 16 has a function in a test mode using an external clock signal CLK having a predetermined cycle. , With respect to the clock cycle by the external clock signal CLK,
The external clock signal CL
A test mode setting circuit that generates a command, an address, and data inside the chip only when a command, an address, and data are input when K rises, and also when the external clock signal CLK falls after the rise of the external clock signal CLK. include.

More specifically, the double-period clock signal generating circuit 17 shown in FIG.
7, an internal column command generating circuit 18 for generating an internal column command, an address operation circuit 19 for generating a test address, and a test data generating circuit 20 for generating test data. A test mode setting circuit is configured. As shown in FIG. 1, the double cycle clock signal generation circuit 17 is built in the control logic & timing generator 15, the internal column command generation circuit 18 is connected to the control logic & timing generator 15, and the address operation circuit 19 is a column address generation circuit. The test data generation circuit 20 is built in the counter 11 and is connected between the input and output of the input buffer 13.

As shown in FIG. 2, for example, the double period clock signal generating circuit 17 includes a NAND gate NAND, inverters IV1 to IV7, and NOR gates NOR and P.
MOS transistor TP, NMOS transistor TN1
TN4, a delay circuit DLY, and flip-flop circuits FF1 and FF2. An external clock signal CLK as shown in FIG. 3A is input, and an internal clock signal ICLK as shown in FIG. 3B is output. Further, a double cycle operation enable signal and first and second clock control signals are input as control signals, and the double cycle operation enable signal is set to “L” level to perform a double cycle operation, and the first and second clocks are operated. The clock control signal is normally at “H” level,
When the level is set to “L” level, the internal clock signal ICLK is stopped.

In this double cycle clock signal generation circuit 17, when an external clock signal CLK is input and the double cycle operation enable signal is set to "L" level, the external clock signal CLK is output via a NAND gate NAND and an inverter IV1. The rising is detected, and the PMOS transistor TP, the NMOS transistors TN1 and TN2, the inverter IV2, the delay circuit DLY, and the inverter IV
4. A pulse signal having a delay time width t of the delay circuit DLY is generated at the time of rising of the external clock signal CLK through a path formed by the flip-flop circuit FF1 and the inverter IV5.

On the other hand, the falling of the external clock signal CLK is detected via a NAND gate NAND, an inverter IV1, and a NOR gate NOR, and NMOS transistors TN3 and TN4, an inverter IV2, a delay circuit DLY, an inverter IV4, and a flip-flop are detected. A pulse signal having a delay time width t of the delay circuit DLY is generated at the time of falling of the external clock signal CLK through a path formed by the flip-flop circuit FF2 and the inverter IV6. Thereby, the internal clock signal ICLK having a double cycle which becomes “H” level when the external clock signal CLK rises and falls.
Can be generated.

Next, regarding the operation of the present embodiment, an outline of the test command operation, an example of the test command, an example of the operation of the test command and its equivalent operation, and a method of entering the test command are shown in FIGS. It will be described based on the following.

In the test command operation, as shown in FIG. 4, when the external clock signal CLK rises, a test command Command for setting a test mode, "A" is input as an address Address, and "D" is input as data Din. With this alone, the external clock signal CL
Commands, addresses, and data can be generated inside the chip even when K falls.

FIG. 5 shows an example of the test command. In FIG. 5, a write command is represented by "Write", a read command is represented by "Read", and arbitrary addresses are represented by "A" (hold), "A + 1" (increment), "/".
A ”(inverted), and arbitrary data as“ D ”(hold),
This is shown as “/ D” (inversion). Further, in the case of a read command, since there is no input data, it is indicated by "-",
In addition, the display of “D *” means that the write data is taken in first.

For example, test commands "WW1" to
With the input of “WW6”, the write command Wri is used at both the rising and falling of the external clock signal CLK.
te occurs. In each of the write commands Write at the time of rising of the external clock signal CLK, data “D” is assigned to the address “A”. The write command Write at the time of the falling edge of the external clock signal CLK includes data “D” and “/ D” for the address “A”, data “D” and “/ D” for the address “A + 1”, Data “D” and “/ D” are assigned to the address “/ A”, respectively.

Similarly, the test commands "WR1" to "W
At the input of R3 ", a write command Write occurs when the external clock signal CLK rises, and a read command Read occurs when the external clock signal CLK falls. The write command Write corresponds to the data" D "for the address" A ", and the read command Read corresponds to the address" A "," A + 1 ",
Data “−” is assigned to “/ A”.

The test commands "RR1" to "RR1"
At the input of "3", a read command Read is generated at the time of rising and falling of the external clock signal CLK.
Data “−” is assigned to addresses “A”, “A + 1”, and “/ A”.

Further, the test commands "RW1" to "R
At the input of W3 ", a read command Read is generated when the external clock signal CLK rises, and a write command Write is generated when the external clock signal CLK falls. The read command Read is data" D * "for the address" A ", and the write command Write is the address. "A", "A +
Data “−” is assigned to “1” and “/ A”.

By inputting the test commands assigned as described above, a read command and a write command can be executed. That is, the target to be tested in the minimum cycle is a read / write column command. Therefore, considering a combination of these commands, a continuous column operation can be performed inside the chip by inputting a single command. .

FIG. 6A shows an operation example of the test command in this column operation, and FIG. 6B shows the timing of an operation example equivalent to this. FIG. 6A shows an example in which a test command “WW6”, an address “A”, and data “D” are input. The operation timing equivalent to this is as shown in FIG.
In synchronization with CLK, data “D” is written to address “A” in the first cycle, and address “/” is written in the second cycle.
Data "/ D" is written to A. Also, in consideration of the case where the address and the data change between this cycle and the next cycle, the address is held / incremented / inverted and the data is Are provided with types such as hold / reverse.

As a method of entering the test mode as described above, there are a case where a mode register set command is used and a case where an address and a column command are combined. FIG. 7 shows an example in which a mode register set command is used. The example of the address code is as shown in FIG. 8, and FIG. 9 shows an example in which a command combined with an address is used.

As shown in FIG. 7, when the mode register set command is used, the test command Com shown in FIG.
The address code of the test mode corresponding to each command is set. 8, the test commands "WW1" to "W1" shown in FIG.
W6 "," WR1 "to" WR3 "," RR1 "to" RR
In correspondence with “3” and “RW1” to “RW3”, the address code is “# 7” in hexadecimal “A7” to “A0”, respectively.
C0 "to"#CE"are assigned.

In the entry method using the mode register set command, after the mode register set MRS for setting the normal burst length, latency, etc. (address "22"), the MRST (MRS for Test) of the operation used during the operation period is performed. Input (address “C0”). As a result, the test mode “WW1” corresponding to the address code “C0” is set (E
ntry). Further, when it is desired to successively execute read / write commands in different test modes, MRST is executed each time to execute different test modes “WW2” to “WW6”, “W
R1 ”to“ WR3 ”,“ RR1 ”to“ RR3 ”,“ RW
1 "to" RW3 "can be easily entered.When the test mode is finally ended, the setting is cleared by the mode register set MRS (address" 22 ") (Exi
t).

On the other hand, when a command combined with an address is used as shown in FIG. 9, if there is a spare address pin not used for a column address, the read / write command in the test mode shown in FIG. , The address "B" by the spare address pin, for example, is taken in at the same time. Thus, it is possible to directly enter a desired test mode. In the entry method using the command combined with the address, the MRST setting is not required as compared with the entry method using the MRS command, so that the entry can be realized easily and easily.

Therefore, according to the semiconductor memory device of the present embodiment, the test mode setting circuit including the double cycle clock signal generating circuit 17, the internal column command generating circuit 18, the address arithmetic circuit 19, and the test data generating circuit 20 is provided. As a result, the internal clock signal ICLK having the double cycle is generated from the external clock signal CLK, and the command, address,
Just by inputting data, commands, addresses, and data are generated inside the chip even at the time of falling of the external clock signal CLK, so that a high-speed test can be easily performed even with a low-speed tester.

Thus, for example, 133 MHz
Even if a high-speed tester exceeding 100 MHz is not used, measurement can be performed with a tester used in a conventional EDO DRAM or the like. Since it can be mass-produced with equipment, testing costs can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above embodiment, 2
Although the description has been given of the example of the 16 Mbit SDRAM in the bank, the present invention is not limited to this, and there is a tendency to increase the number of banks to four banks, eight banks, and 64 Mbits, 256 banks.
The present invention is widely applicable to M-bit SDRAMs which have a tendency to have a larger capacity, and the effect of the present invention is further increased by adopting such a multi-bank, large-capacity configuration.

Further, the test command is not limited to the one shown in FIG. 5, and the address code is not limited to the example shown in FIG. 8, but it can be changed according to the product to be tested. Not even.

Although the description has been given of the case where the present invention is applied to an SDRAM, the present invention can be applied to other semiconductor memory devices such as an SSRAM which operate in synchronization with an external clock signal.

[0042]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) A test mode setting circuit for internally generating a command, an address and data at the falling edge of the external clock signal following the input of the command, address and data at the rising edge of the external clock signal Therefore, since the internal operation can be performed at twice the clock cycle of the external clock signal, a high-speed test can be easily performed even with a low-speed tester.

(2) According to the above (1), for example, 100 MH
Even without using a high-speed tester that exceeds z, measurement can be performed with a low-speed tester, so there are few or no items that need to be measured at high speed, so mass production can be performed with existing equipment. It becomes possible to reduce.

(3) By applying to a read / write column command to be tested in the minimum cycle,
With this combination of column commands, it becomes possible to execute a continuous column operation internally by one command input.

(4) In consideration of the combination of the address and the data and the command, the address has the type of holding / increment / inversion and the data has the type of holding / inversion.
It is possible to cope with a case where the address and data change in the next cycle.

(5) When the test mode is entered using the mode register set command, it is possible to easily set the test mode by using an address code corresponding to the test command.

(6) When an entry is made using a command in which a test mode is combined with an address, it is possible to set the address simply and easily using an address using a spare address pin.

(7) According to the above (1) to (6), in a semiconductor memory device such as an SDRAM or an SSRAM operating in synchronization with an external clock signal, a high-speed test can be performed with a low-speed tester, and the testing cost can be reduced. Can be reduced, and it is possible to cope with an increase in operating frequency.

[Brief description of the drawings]

FIG. 1 is an overall block diagram showing a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a double cycle clock signal generation circuit in the semiconductor memory device according to one embodiment of the present invention;

FIG. 3 is a waveform diagram showing a clock signal in the semiconductor memory device according to one embodiment of the present invention;

FIG. 4 is a timing chart showing an outline of a test command operation in the semiconductor memory device according to one embodiment of the present invention;

FIG. 5 is an explanatory diagram showing an example of a test command in the semiconductor memory device according to one embodiment of the present invention;

FIGS. 6A and 6B are timing charts showing an operation example of a test command and an equivalent operation example thereof in the semiconductor memory device according to the embodiment of the present invention;

FIG. 7 is a timing chart showing a method for entering a test command in the semiconductor memory device according to one embodiment of the present invention;

FIG. 8 is an explanatory diagram showing an example of an address code in the semiconductor memory device according to one embodiment of the present invention;

FIG. 9 is a timing chart showing another method for entering a test command in the semiconductor memory device according to one embodiment of the present invention;

FIG. 10 is a timing chart showing an operation example of a test command in a semiconductor memory device as a premise of the present invention.

[Explanation of symbols]

 1, 2 memory array bank 3, 4 row decoder 5, 6 column decoder 7, 8 sense amplifier & input / output bus 9 row address buffer 10 column address buffer 11 column address counter 12 refresh counter 13 input buffer 14 output buffer 15 control logic & Timing generator 16 Test circuit 17 Double cycle clock signal generation circuit 18 Internal column command generation circuit 19 Address operation circuit 20 Test data generation circuit NAND NAND gates IV1 to IV7 Inverter NOR NOR gate TP PMOS transistors TN1 to TN4 NMOS transistors DLY delay circuit FF1, FF2 flip-flop circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI G11C 11/413 G01R 31/28 V 11/407 G11C 11/34 341D 11/401 362S 371A

Claims (6)

[Claims] 1. A semiconductor memory device equipped with a test mode using an external clock signal having a predetermined period, wherein a command, an address,
When data is input, a test mode setting circuit that internally generates a command, an address, and data at the time of falling of the external clock signal following the rising of the external clock signal is provided. A semiconductor memory device characterized in that the inside operates with twice the number of clock cycles. 2. The semiconductor memory device according to claim 1, wherein the command is a read / write column command, and a continuous column operation is internally executed by a single command input by a combination of the column commands. A semiconductor memory device characterized in that: 3. The semiconductor memory device according to claim 2, wherein said address has a type of hold / increment / inversion, and said data has a type of hold / inversion, and said address and data and said command and Semiconductor storage device, which also considers combinations of the following. 4. The semiconductor memory device according to claim 1, wherein a test mode in said test mode setting circuit is entered using a mode register set command. 5. The semiconductor memory device according to claim 1, wherein the test mode in said test mode setting circuit is entered using a command combined with an address. 6. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is a synchronous DRAM.