JP2000286686A - Transition detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transition detection circuit which is effective to increase the access speed by the reduction of capacitance of an input circuit and also to improve the noise characteristics by detecting the rise or fall of an input signal and expanding the pulse width of an output signal. SOLUTION: When an input terminal T1 falls, an output pulse is generated by a rise pulse detection circuit of a circuit block B2 and a pulse expansion circuit of the block B2 expands the output pulse. When the terminal T1 rises, an output pulse is generated by a rise pulse detection circuit of a circuit block B1 and a pulse expansion circuit of the block B1 expands the output pulse. The output waveforms of both blocks B1 and B2 are logically synthesized to obtain an output waveform of a transition circuit. Thereby the output pulse of a transition detection circuit having a sufficient reset time can be generated even with the pulse width that is generated by the noise of an input terminal that does not satisfy the reset time. Furthermore, the load capacitance of an input circuit can be optimized and accordingly the access speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a transition detection circuit for detecting a change in an input signal applied to an input terminal.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram of an address transition detection circuit of a semiconductor memory device. T1 is an address input terminal, 2
Is a low power supply voltage (the low power supply voltage is 0 V and is abbreviated to GND hereinafter), and T2 is a NOR circuit control signal input terminal for selecting an active / inactive state of the NOR circuit L1. NOR circuit L
Reference numeral 1 denotes an active state at GND and an inactive state at a high power supply voltage (hereinafter abbreviated to VDD). C1 is the load capacity, L2 and L3
Is an inversion circuit. T3 is an input circuit output terminal connected to the address buffer. B5 and B6 represent circuit blocks of the rising pulse detection circuit. L4 is a NOR circuit having a function of logically synthesizing output waveforms of the circuit blocks B5 and B6. T4 is the output terminal of the transition detection circuit,
N4 represents a contact point. FIG. 6 shows a circuit diagram of the circuit blocks B5 and B6 of the rising pulse detection circuit. D6 to D1
Numeral 0 denotes a delay inverting circuit which constitutes a delay circuit block B7. S6i to S8i (i = for circuit block B5)
5, i = 6 in the case of the circuit block B6) represents a contact, and the correspondence of the contacts N1 to N4 in FIG. 5 is as follows.
Contact S65 and contact N1, contact S66 and contact N2, contact S
The contact 85 and the contact N3 are the same as the contact S86 and the contact N4.
L10 is a NAND circuit having a function of logically synthesizing the waveforms of the contacts S6i and S7i, which are the input and output of the delay circuit block. In the delay inverting circuits D6 to D10,
The capability of the P-channel transistor of the odd-numbered delay inverting circuit is greater than the capability of the N-channel transistor.
Since the capability of the P-channel transistor of the even-numbered delay inverting circuit is set smaller than that of the N-channel transistor, when the falling waveform is input to the contact S6i, the waveform of the contact S7i is changed from GND to VDD. When the rising waveform is immediately input to the contact S6i, the waveform at the contact S7i falls with a delay from the rising waveform at the contact S6i. Hereinafter, the former delay amount is referred to as a fast path delay amount, and the latter delay amount is referred to as a slow path delay amount. The delay amount of the slow path is set to a time necessary for sufficiently initializing the internal circuit in the semiconductor memory device before starting reading or writing data after the address changes. The initialized state means that a pair of signal lines (for example, a bit line, a data line, and an input and output line of a sense amplifier) in a circuit inside a semiconductor device are made to have the same voltage, and a word line and a column line for selecting a memory cell are used. Is abbreviated as “reset” in the following.

FIG. 7 shows operation waveforms of the circuit of FIG. 5 when a normal waveform is applied to the address input terminal T4. In the figure, the vertical axis represents voltage, and the horizontal axis represents time. Contacts N1 and N2
When the waveform of the contacts S75 and S76 falls, the waveform of the contacts S75 and S76 rises with a delay of the delay amount of the fast path, and when the waveforms of the contacts N1 and N2 rise, the waveforms of the contacts S75 and S76 rise with a delay amount of the delay of the slow path. When the address input terminal T1 falls, a pulse is generated at the contact S86, and when the address input terminal T1 rises, a pulse is generated at the contact S85. The waveform of the output terminal T4 of the transition detection circuit is a waveform logically synthesized with the contacts S85 and S86. The period of VDD of the waveform of the output terminal T4 of the transition detection circuit is the reset time.

FIG. 8 shows operation waveforms when a signal applied to the address input terminal T1 contains noise having a width equal to or less than the delay amount of the slow path of the delay circuit block B7.
In the figure, the vertical axis represents voltage, and the horizontal axis represents time.

When the input voltage of the address input terminal T1 is VD
In the case of D, noise enters and becomes GND, and again VD
The operation for recovering to D will be described. The waveform of the contact N1 serving as an input to the delay circuit block B5 changes from VDD to GND and then to VDD. When the contact N1 changes from VDD to GND, the waveform of the contact S75 changes from GND to VDD with a delay of the fast path, and when the contact N1 changes from GND to VDD, the waveform of the contact S75 delays the delay of the slow path. As a result, the pulse changes from VDD to GND, so that a pulse formed with a delay in the slow path is output to the node N3. On the other hand, the waveform at the contact N2 changes from GND to VDD and GND. When the voltage at the contact N2 changes from GND to VDD, a delay occurs on a slow path, so that the voltage at the contact S76 does not change immediately. Since the time during which the contact N2 is at VDD is shorter than the delay amount of the slow path, the contact N2 is at VDD.
Since the change of GND from is transmitted through a fast path, the contact N
Before the change from GND to VDD of No. 2 is output to the contact S76, the change from VDD to GND is transmitted to the contact S76. Since the waveform at the contact S76 remains at VDD, a pulse at the contact N2 is output to the contact N4. As a waveform at the output terminal T4 of the transition detection circuit, a composite waveform of the waveforms at the contacts N3 and N4 is output.

[0006]

The address input terminal T
A pulse is generated in the input waveform due to the noise applied to 1,
A capacitor C1 is connected between the circuits L1 and L2 in order to prevent the semiconductor memory device from malfunctioning due to the pulse, and a pulse signal having a small width that cannot sufficiently reset the semiconductor memory device.
Had been absorbed.

In order to speed up access, it is necessary to reduce the load capacity of the input circuit. When the load capacitance in the input circuit is reduced, a pulse signal having a small width is input to the circuit L2. FIG. 9 shows an operation waveform when the pulse width generated by noise is equal to the delay time of the fast path.

The operating waveforms of the contacts N1 to N4, S75 and S76 are almost the same as those of FIG. 8, but the respective waveforms of the contacts N3 and N4 are output to the output terminal T4 of the transition detection circuit. In the case of FIG. 9 as compared with the reset time at the time of a normal input signal, the delay time of the path whose reset time is fast is short, and sufficient reset is not performed, thereby causing a malfunction.

To eliminate the malfunction, the delay time of the slow path is increased to secure the reset time, or the delay amount of the fast path is reduced, that is, the transmission speed of the fast path is increased. When the above-described method is used, the capability of the N-channel transistor of the odd-numbered delay inverting circuit of the delay circuit block and the capability of the P-channel transistor of the even-numbered delay inverting circuit may be reduced. Since the logic level of the inverting circuit approaches VDD or GND, malfunction of the delay circuit occurs due to power supply noise. When the method described later is used, the capability of the P-channel transistor of the odd-numbered delay inverting circuit of the delay circuit block and the capability of the N-channel transistor of the even-numbered delay inverting circuit may be increased. Logic level is VD
Since the voltage approaches D or GND, a malfunction of the delay circuit occurs due to noise of the power supply. In the above method, the delay amount of the fast path and the reset time have opposite characteristics, so it is difficult to set them.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problem of a malfunction that occurs when an input terminal is affected by noise. The object of the present invention is to increase the speed of access and improve noise characteristics by reducing the capacity of an input circuit. And an effective transition detection circuit.

[0011]

In a transition detection circuit for detecting a change in an input signal applied to an input terminal, a pulse detection circuit having a function of detecting a rise or a fall of an input signal; It is characterized by comprising a pulse expansion circuit having a function of expanding the pulse width of the output signal.

In the pulse stretching circuit, a drain of a first conductivity type transistor or a drain of a second conductivity type transistor is connected to an input terminal or an output terminal of an inversion circuit having a function of delaying an output signal of the pulse detection circuit. The source of the first conductivity type transistor is connected to a first power supply voltage, the source of the second conductivity type transistor is connected to a second power supply voltage, and the gate of the first conductivity type transistor is connected to the pulse. It is connected to the output terminal of the detection circuit, and the gate of the second conductivity type transistor is connected to the output terminal of the inversion circuit whose input terminal is connected to the output terminal of the pulse detection circuit.

In the pulse stretching circuit, a gate length of a transistor of a first conductivity type and a transistor of a second conductivity type connected to an output terminal of the pulse detection circuit may be a first conductivity type and a second conductivity type constituting the pulse stretching circuit. 2 is smaller than the maximum gate length of the second conductivity type transistor.

[0014]

FIG. 1 shows a circuit diagram of the present invention. B
Reference numerals 1 and B2 denote circuit blocks each including a rising pulse detection circuit and a pulse expansion circuit. Symbols in the figures other than those described above have the same meaning as in FIG. FIG. 2 shows a circuit diagram of circuit blocks B1 and B2 each including a rising pulse detection circuit and a pulse expansion circuit.

B3 indicates a rising pulse detection circuit block, and B4 indicates a pulse expansion circuit block.

1 is a high power supply voltage, D1 to D5 are delay inverting circuits, L6 to L8 are inverting circuits, L5 and L9 are NAND circuits, TR1 and TR2 are P channel transistors, and TR3 and TR4 are N channel transistors. 3 shows a transistor. S1i to S5i (where i is i = 1 for the circuit block B1 and i = 2 for the circuit block B2) represent contacts, and the correspondence of the contacts N1 to N4 in FIG. 1 is as follows. The contacts S11 and N1, the contacts S12 and N2, the contacts S51 and N3, and the contacts S52 and N4 are the same.

In the delay inverting circuits D1 to D3 in the rising pulse detection circuit block B3, the capacity of the P-channel transistor of the odd-numbered delay inverting circuit is greater than the capacity of the N-channel transistor, and the delay of the even-numbered stage is inverted. Since the capability of the P-channel transistor of the inverting circuit is set smaller than that of the N-channel transistor, when the falling waveform is input to the contact S1i, the waveform of the contact S2i immediately rises and the rising waveform changes to the contact S1i.
, The contact S2i is set to fall with a delay from the rising waveform of the contact S1i. The delay amount of the former is the delay amount of the fast path, and the delay amount of the latter is the delay amount of the slow path.

If the capabilities of the P-channel transistor and the N-channel transistor of the delay inverting circuits D1, D2 and D3 are the same as those of the delay inverting circuits D6, D7 and D8 constituting the delay circuit block B7 in FIG. The delay amount and the delay amount of the slow path are smaller than before. The amount of extension of the pulse in the pulse extension circuit is a time obtained by subtracting the output pulse width of the pulse detection circuit from the reset time when a normal input is applied in the circuit of FIG.

In the pulse expansion circuit block B4, P
Channel transistors TR1 and TR2 and inverting circuit L6
When the gate lengths of the P-channel transistor and the N-channel transistor of L7 are smaller than the maximum gate length in the same circuit block, and the gate width is further reduced, the circuit block reacts to a narrow input pulse to extend the pulse. Each contact in the circuit can be VDD or GND. As a result, the pulse expansion circuit operates normally even for a pulse having a small width. FIG. 3 shows an operation waveform when the same waveform as that of FIG. 9 is input to the address input terminal T1. In the figure, the vertical axis represents voltage, and the horizontal axis represents time.

The address input terminal T1 has an input voltage of VD
In the case of D, noise enters and becomes GND, and again VD
It is a signal that recovers to D.

The waveform at the contact N1 changes from VDD to GND and then to VDD. In the inverting circuits D1 to D3 for delay in the rising pulse detection circuit on the circuit block B1 side, the falling side of the contact point N1 is a fast path, so that the contact point S21 changes from GND to VDD. When the contact N1 rises, the path is a slow path, so that the contact S21 changes from VDD to GND with a delay of the delay of the path slower than the contact N1. Due to the waveforms of the contacts N1 and S21, a pulse having a width corresponding to the delay amount of the slow path is generated at the contact 31. When the contact S31 changes from VDD to GND, the gates of the P-channel transistors TR1 and TR2 change from VDD to GND, and the gates of the N-channel transistors TR3 and TR4 change from GND to VDD. Since the P-channel transistor and the N-channel transistor become conductive, the contact to which the drain of the transistor is connected becomes VDD or GND, and the contact S
41 changes from VDD to GND. When the contact S31 changes from GND to VDD, the P-channel transistor TR1
And the gate of TR2 goes from GND to VDD, and the gates of the N-channel transistors TR3 and TR4 go from VDD to GND. The P-channel transistor and the N-channel transistor are cut off, and the delay inverting circuit D
4 and D5 are delayed, so that the contact S41 changes from GND to VDD with a delay from the contact S31 by the set delay amount. On the other hand, the waveform at the contact N2 changes from GND to VDD and GND. Since the rising pulse detection circuit on the circuit block B2 side cannot detect the waveform of the contact N2,
The contact S22 remains at VDD. Since the inverted signal of the waveform of the contact 12 is output, the waveform of the contact S32 changes from VDD to GND and VDD. Contact S32 is VDD
Changes from GND to GND, the P-channel transistor TR
1 and the gate of TR2 change from VDD to GND, and N
The gates of the channel transistors TR3 and TR4 are GND
To VDD. Since the P-channel and N-channel transistors are conductive, the contact to which the drain of the transistor is connected becomes VDD or GND, and the contact S42 changes from VDD to GND. Contact S32 is GND
From VDD to VDD, the P-channel transistor TR
The gates of 1 and TR2 go from GND to VDD, and N
The gates of the channel transistors TR3 and TR4 are connected to VDD.
To GND. The P and N channel transistors are cut off, and the delay inverting circuits D4 and D5 have a delay, so that the contact S42 changes from GND to VDD with a delay from the contact S32 by the set delay amount. The waveform of the output terminal T4 of the transition detection circuit becomes a waveform obtained by combining the waveforms of the contacts N3 and N4, and has a sufficient reset time.

FIG. 4 shows operation waveforms when a normal address is input.

When the input terminal T1 falls, an output pulse is generated by the rising pulse detection circuit of the circuit block B2, and the pulse expansion circuit of the block expands the output pulse. When the input terminal T1 rises, the circuit block B2 generates the output pulse. B
An output pulse is generated by the rising pulse detection circuit of 1 and
The pulse expansion circuit of the block expands the output pulse, logically synthesizes the output waveforms of the blocks B1 and B2, and becomes the output waveform of the transition circuit.

As described above, even if the pulse width is generated by the noise of the input terminal which does not satisfy the reset time in the conventional circuit, the output pulse of the transition detection circuit having a sufficient reset time is generated by using the circuit of the present invention. It becomes possible. In addition, since the load capacity of the input circuit can be optimized, the access can be speeded up.

[0025]

As described above, according to the present invention, each contact of the pulse detection circuit and the inverting circuit forming the delay circuit by the output signal of the pulse detection circuit is connected to the first power supply voltage or the second power supply voltage. By providing a pulse expansion circuit having a function of connecting to the power supply voltage of the transition detection circuit, an output pulse of the transition detection circuit having a sufficient reset time can be generated even if a pulse having a small width caused by noise occurs in the input signal. .

Also, by making the gate lengths of the P-channel transistor and the N-channel transistor of the circuit connected to the output terminal of the pulse detection circuit smaller than the maximum gate lengths of the P-channel transistor and the N-channel transistor constituting the pulse extension circuit, Since an output pulse of the transition circuit having a sufficient reset time can be obtained even for a pulse having a smaller width, there is an effect of preventing a malfunction due to noise applied to the input terminal. Further, the load capacitance of the input circuit can be optimized, which is effective in increasing the access speed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of the present invention.

FIG. 2 is a circuit diagram of a circuit block according to the present invention.

FIG. 3 is an operation waveform diagram for an input waveform having the same pulse width as a fast path delay according to the present invention.

FIG. 4 is an operation waveform diagram with a normal input waveform of the present invention.

FIG. 5 is a conventional circuit diagram.

FIG. 6 is a circuit diagram of a conventional circuit block.

FIG. 7 is an operation waveform diagram with a conventional normal input waveform.

FIG. 8 is an operation waveform diagram for an input waveform having a pulse width equal to or less than the delay of a conventional slow path.

FIG. 9 is an operation waveform diagram for an input waveform having the same pulse width as a conventional fast path delay.

[Description of Signs] 1: High power supply voltage 2: Low power supply voltage T1: Address input terminal T2: NOR circuit control signal input terminal T3: Input circuit output terminal T4: Output terminal of transition detection circuit S1i, S2i, S3i, S4i , S5i, S6i, S
7i, S8i: Contact L1, L4: NOR circuit L2, L3, L6, L7, L8: Inverting circuit D1, D2, D3, D4, D5, D6, D7, D8, D
9, D10: delay inverting circuit L5, L9, L10: NAND circuit B1, B2, B3, B4, B5, B6, B7: circuit block TR1, TR2: P-channel transistor TR3, TR4: N-channel transistor C1: load capacitance

Claims (3)

[Claims] A transition detection circuit for detecting a change in an input signal applied to an input terminal, wherein the pulse detection circuit has a function of detecting a rise or a fall of the input signal, and a pulse of an output signal of the pulse detection circuit. A transition detection circuit comprising a pulse expansion circuit having a function of expanding a width. 2. The pulse expansion circuit according to claim 1, wherein the drain of the first conductivity type transistor or the drain of the second conductivity type transistor has a function of delaying an output signal of the pulse detection circuit. And the source of the first conductivity type transistor is connected to the first power supply voltage, the source of the second conductivity type transistor is connected to the second power supply voltage, and the gate of the first conductivity type transistor is connected to the first power supply voltage. It is connected to the output terminal of the pulse detection circuit, and the gate of the second conductivity type transistor is connected to the output terminal of the inversion circuit whose input terminal is connected to the output terminal of the pulse detection circuit. The transition detection circuit according to claim 1, wherein 3. The pulse stretching circuit according to claim 1, wherein a gate length of a transistor of a first conductivity type and a transistor of a second conductivity type connected to an output terminal of said pulse detection circuit is a first conductivity type of said pulse stretching circuit. 2. The transition detection circuit according to claim 1, wherein the gate length is smaller than the maximum gate length of the transistor of the second conductivity type.