JP2000285144A - Digital circuit and clock signal control method therefor - Google Patents

Digital circuit and clock signal control method therefor

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Publication number
JP2000285144A
JP2000285144A JP11086167A JP8616799A JP2000285144A JP 2000285144 A JP2000285144 A JP 2000285144A JP 11086167 A JP11086167 A JP 11086167A JP 8616799 A JP8616799 A JP 8616799A JP 2000285144 A JP2000285144 A JP 2000285144A
Authority
JP
Japan
Prior art keywords
digital circuit
delay
clock signal
delay time
plurality
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11086167A
Other languages
Japanese (ja)
Inventor
Tetsuya Higuchi
Masahiro Murakawa
Eiichi Takahashi
Kenji Toda
賢二 戸田
正宏 村川
哲也 樋口
栄一 高橋
Original Assignee
Agency Of Ind Science & Technol
Tetsuya Higuchi
Eiichi Takahashi
Kenji Toda
工業技術院長
賢二 戸田
哲也 樋口
栄一 高橋
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency Of Ind Science & Technol, Tetsuya Higuchi, Eiichi Takahashi, Kenji Toda, 工業技術院長, 賢二 戸田, 哲也 樋口, 栄一 高橋 filed Critical Agency Of Ind Science & Technol
Priority to JP11086167A priority Critical patent/JP2000285144A/en
Priority claimed from US09/519,463 external-priority patent/US6658581B1/en
Publication of JP2000285144A publication Critical patent/JP2000285144A/en
Application status is Pending legal-status Critical

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10Distribution of clock signals, e.g. skew
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0008Synchronisation information channels, e.g. clock distribution lines
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0016Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033Correction by delay
    • H04L7/0037Delay of clock signal
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019Variable delay
    • H03K2005/00026Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • H03K2005/00032Dc control of switching transistors
    • H03K2005/00039Dc control of switching transistors having four transistors serially
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019Variable delay
    • H03K2005/00058Variable delay controlled by a digital setting

Abstract

PROBLEM TO BE SOLVED: To deal with the phase shift of a clock signal. SOLUTION: Concerning this clock signal control method, a variable delay element 6 is installed in the clock input of a circuit constituting digital separation, A test pattern signal is applied to the input of a digital circuit, and by comparing a circuit output with a value expected to provide in the normal operation, the presence/absence of abnormality in the operation of the circuit is decided. Until normal decision is provided concerning the setting value of delay time of the delay element, the setting value of respective delay elements is changed by a delay setting circuit 7. As a method for searching the setting value of such delay time, any method based on genetic algorithm or all search is used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a digital circuit for synchronizing circuit operations based on a clock signal and a method for adjusting the clock signal.

[0002]

2. Description of the Related Art Digital circuits which have a plurality of circuits and which operate based on a clock signal are widely known. In recent years, high speed has been required for digital circuits, and LSIs are sometimes used.

When a clock signal is supplied to a plurality of circuits constituting a digital circuit, it is preferable that the phases of the input signals to each circuit all match. For this purpose, the circuits are arranged so that the clock signal lines from the clock generator to the multiple circuits are equidistant, and care is taken so that there is no phase difference in the clock signal supplied to each circuit. are doing.

[0004]

However, the necessity of making the clock signal lines equidistant places restrictions on the arrangement of the circuits. Furthermore, the clock signal lines may not be completely equidistant due to unevenness in the material of the signal lines or manufacturing errors.

[0005] If the distance between the clock signal lines becomes non-uniform due to such factors, a phase difference occurs between the clock signals supplied to the respective circuits, leading to malfunction of the digital circuit. Further, after the digital circuit is formed into an LSI, the timing of the clock signal cannot be adjusted.

In view of the above, it is an object of the present invention to make the signal lines for supplying a clock signal to a digital circuit not to be equidistant, and to adjust the timing of the clock signal even after forming the LSI. And a clock signal adjusting method therefor.

[0007]

In order to achieve the above object, according to the first aspect of the present invention, a clock signal is inputted,
A plurality of circuits operating in synchronization with the clock signal,
In the digital circuit in which the plurality of circuits are in a connection relationship, a plurality of delay elements capable of variably setting a delay time are provided on an input signal line of the clock signal of the plurality of circuits,
A phase shift of a clock signal is compensated by variably setting delay times of the plurality of delay elements.

According to a second aspect of the present invention, in the digital circuit according to the first aspect, the plurality of circuits include a circuit that does not input a clock signal, and an input and / or an output of the circuit that does not input the clock circuit. A delay element capable of variably setting a delay time is further provided on the signal line.

According to a third aspect of the present invention, in the digital circuit according to the first or second aspect, a delay time setting means for automatically setting a set value of the delay time of the plurality of delay elements is provided inside or outside the digital circuit. It is further characterized by the following.

According to a fourth aspect of the present invention, in the digital circuit according to the third aspect, the delay time setting means supplies a test pattern signal to the digital circuit as an input, and output values of the plurality of circuits are predetermined. Automatically set the delay time of the plurality of delay elements by performing a delay time search that changes the delay time of the plurality of delay elements by trial and error until a match determination is obtained. It is characterized by doing.

According to a fifth aspect of the present invention, in the digital circuit according to the fourth aspect, the delay time search is performed according to a full search method in which a small change is made from an initial value relating to a predetermined delay time until the coincidence determination is obtained. It is characterized by.

According to a sixth aspect of the present invention, in the digital circuit according to the fourth aspect, the delay time search is performed according to a random search method of randomly changing a set value of a delay element until the coincidence determination is obtained. And

According to a seventh aspect of the present invention, in the digital circuit according to the fourth aspect, in the delay time search, when the relationship between the delay time of the delay element and the set value is a monotonically increasing function, the larger delay time is used. If the relationship between the delay time of the delay element and the set value is not a monotonically increasing function, the set value to be changed at random is selected.
The method is characterized by the following method.

According to an eighth aspect of the present invention, in the digital circuit according to the fourth aspect, the delay time search is performed using a new set value obtained by determining whether or not the set values of a plurality of delay elements match. It is characterized by following a genetic algorithm method for creating a combination of set values.

According to a ninth aspect of the present invention, in the digital circuit according to the first or second aspect, the digital circuit is virtually created as a simulation model on a computer, and the plurality of delay elements are created by the simulation model. Is determined.

According to a tenth aspect of the present invention, there is provided a clock signal adjusting method for a digital circuit having a plurality of circuits inputting a clock signal and operating in synchronization with the clock signal, wherein the plurality of circuits are connected. A plurality of delay elements capable of variably setting a delay time are provided on an input signal line of the clock signal of the plurality of circuits, and a phase shift of the clock signal is compensated by variably setting the delay times of the plurality of delay elements. It is characterized by the following.

According to an eleventh aspect of the present invention, in the clock signal adjusting method of the digital circuit according to the tenth aspect, the plurality of circuits include a circuit that does not input a clock signal, and the plurality of circuits include a circuit that does not input the clock circuit. The input and / or output signal lines further include a delay element capable of variably setting a delay time.

According to a twelfth aspect of the present invention, in the clock signal adjusting method for a digital circuit according to the tenth or eleventh aspect, the delay time setting circuit for automatically setting the set values of the delay times of the plurality of delay elements is provided. The circuit is further provided inside or outside the circuit.

According to a thirteenth aspect of the present invention, in the clock signal adjusting method for a digital circuit according to the twelfth aspect, the delay time setting circuit supplies a test pattern signal to the digital circuit as an input, and outputs the test pattern signal from the plurality of circuits. Determine whether the value matches a predetermined expected value, until a match determination is obtained, by performing a delay time search to change the delay time of the plurality of delay elements by trial and error, by performing a delay time search of the plurality of delay elements The delay time is set automatically.

According to a fourteenth aspect of the present invention, in the clock signal adjusting method for a digital circuit according to the twelfth aspect, the delay time search is changed slightly from an initial value relating to a predetermined delay time until the coincidence determination is obtained. It is characterized by following the full search method.

According to a fifteenth aspect of the present invention, in the clock signal adjusting method for a digital circuit according to the twelfth aspect, the delay time search is a random search in which the set value of the delay element is randomly changed until the coincidence determination is obtained. It is characterized by following the method.

According to a sixteenth aspect of the present invention, in the clock signal adjusting method for a digital circuit according to the twelfth aspect, the delay time search is performed when a relationship between a delay time of the delay element and a set value is a monotonically increasing function. When the relation between the delay time of the delay element and the set value is not a monotonically increasing function, the DP value is randomly selected from the larger delay time to the smaller delay time. And

According to a seventeenth aspect of the present invention, in the clock signal adjusting method for a digital circuit according to the twelfth aspect, the delay time search is performed by using a set value for which a match is obtained with respect to set values of a plurality of delay elements. The method is characterized by following a genetic algorithm method of creating a new combination of set values using the method.

According to an eighteenth aspect of the present invention, in the clock signal adjusting method for a digital circuit according to the tenth or eleventh aspect, the digital circuit is virtually created as a simulation model on a computer, and A delay time of the plurality of delay elements is determined.

[0025]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a configuration example of a digital circuit to which the present invention is applied. In FIG. 1, reference numerals 1, 3, and 5 denote registers for holding and outputting data input in synchronization with a clock signal. Reference numeral 2 denotes a decoder for identifying an operation instruction transferred by a function signal. 4 is an arithmetic circuit (ALU) for performing arithmetic processing according to the identified arithmetic instruction
It is. The digital operation circuit constituted by the above circuits is the same as the conventional one, and the circuit portion relating to the present invention will be described below.

Reference numeral 6 denotes a delay element, which uses a delay element capable of variably setting a delay time.

A delay element for inputting a clock signal;
In this example, they are installed on the input clock signal lines of the registers 1, 3, and 5. Further, a delay element 6 is provided on each data signal line on the input and / or output side (only the output side in this example) of the circuit (ALU4) not using a clock signal.

The delay time of each delay element 6 is set by a delay amount setting circuit 7.

The delay amount setting circuit 7 automatically sets the delay amounts (delay times) of the plurality of delay elements when receiving a setting execution instruction signal from the outside. Therefore, the delay amount setting circuit 7
Supplies a data signal for adjustment (referred to as a test pattern signal) via a signal line 8 to a data input of the entire digital circuit, in this case, a data input side of the register 1. When the test pattern signal is given as a data input, the output of the register 1, the output of the register 3, the output of the delay element 6 on the data line, and the output of the register 5 are transferred to the signal line group 9.
Via the delay amount setting circuit 7.

The delay amount setting circuit 7 compares the output (expected value) expected to be obtained during normal operation with the fetched output in response to the test pattern signal to determine whether the circuit is normal or not. More specifically, it is determined whether or not the delay amounts of the plurality of delay elements are appropriate. If the determination is no, the delay amount of the delay element is slightly changed. In this way, the delay amounts of the plurality of delay elements are changed from the initial set values until the expected value is obtained. The digital circuit is used with the set value at the time when the expected value is obtained.

FIG. 2 shows a functional configuration of the delay amount setting circuit 7. In the present embodiment, the circuit shown in FIG. 2 is realized by using a programmable LSI as disclosed in Japanese Patent Application Laid-Open No. 9-294069. In FIG. 2, reference numeral 11 denotes a control unit for controlling a circuit described later. Reference numeral 12 denotes a comparator, which is the same as normal data (expected value) output from a circuit in the digital circuit when a test pattern signal is given to the digital circuit for timing adjustment of a clock signal; The data (actually measured values) actually output from the above circuit are compared. Reference numeral 13 denotes a signal generator, which is a test pattern signal for adjusting timing and a selector 1.
5 generates a data signal indicating the expected value corresponding to the circuit output selected by 5, ie, the circuit output in the digital circuit. The control unit 11 instructs which data signal of the expected value is to be generated.

The selector 15 selects a circuit output to be compared with an expected value according to a connection s with each circuit output (reference numeral 9 in FIG. 1) in the digital circuit and a selection signal from the control unit 11 via the buffer 16. . The selector 14 selects a delay element (one of reference numerals 6 in FIG. 1) corresponding to the circuit output selected by the selector 15 by a selection signal from the control unit 11, and selects a data signal indicating the set delay amount. Output to the delay element.

The circuit operation of FIG. 2 will be described with reference to FIG. The control unit 11 first transmits a selection signal to the selector 15 to select the circuit output of the register 1 in FIG. 1 (Step S10).

Next, a selection signal is transmitted to the selector 14 to select a delay element corresponding to the selected circuit output, in this case, a delay element on the clock signal line to the register 1. Further, an initial setting value of the delay amount for the delay element is output via the selector 14 (step S20). In synchronization with the clock signal, the control unit 11 outputs a 4-bit test pattern signal to the signal line 8 as a data input.
Since the register 1 only holds the input data, the register 1 outputs the held data in a normal operation. This output value is compared with the expected value generated by the signal generator 13 by the comparator 12. If the register 1 operates normally and the set value of the delay amount of the delay element is appropriate, the comparator 12 outputs a determination result of coincidence (YES determination in step S40).

On the other hand, when the judgment result of the comparator 12 does not match, the control unit 11 sets the current set value A of the delay amount to ΔA
(Or -ΔA) set value A +
Change to ΔA (or A−ΔA) (Step S5
0). The control unit 11 outputs the same pattern signal to the signal generator 13.
And compares the circuit output with the expected value (steps S30 → S40). In this way, the processes of steps 30 to S50 are repeated until a match determination is obtained.

When a match is obtained, register 1 in FIG.
Since the setting of the delay amount has been completed, the control unit 11
Selects the delay element used for the output of register 3 and its clock input (steps S40 → S60 →
S70).

After the delay amount of the selected delay element is initialized, the optimum delay amount of the delay element of the register 3 is searched for and set by the above-described loop processing of steps S30 to S50. At this time, the optimum delay amount is determined by comparing the output value of the register 3 with the expected value corresponding to this output value. Thereafter, the delay elements to be set are sequentially switched, and when the delay amount of the last delay element is set, the processing in FIG. 3 ends (YES determination in step S60).

In the present embodiment, the same processing as that of the circuit of FIG. 2 can be executed by configuring the programmable logic LSI so as to execute the above-described processing procedure of FIG.

With respect to the setting of the delay time of the delay element described above, various embodiments described below can be implemented.

A) Adjustment Method by Full Search Method This is a method for adjusting the timing of the clock signal described above, and there is no restriction on the digital circuit to be used. Test chip function using test pattern signal for all delay settings Select and use any delay setting from delay settings that work as expected. This method has a merit that although it takes time to search for the amount of delay to be set, the set value can be reliably found.

B) Adjustment Method Using Random Search Method There is no restriction on the digital circuit to be used. The delay setting amount is randomly selected by a random number device or the like, and an adjustment test is performed using the test pattern signal. The set value is slightly changed in the full search method, but the random search method is different from the full search method in that the set value is randomly changed. This method has the advantage that the search time is shorter than the full search method, but has the disadvantage that the amount of delay varies from digital to digital.

C) DP (Dynamic Program)
Adjustment by Searching Method Using mming (also called Dynamic Programming) A digital circuit searchable by DP is a circuit having a configuration such that the entire signal flows in one direction, such as a pipeline configuration. The target digital circuit is divided into blocks for each stage as in a pipeline configuration. Next, the set values of the delay elements are adjusted in order from the previous stage.

When the relationship between the delay time of the delay element and the set value is a monotonically increasing function, the set value is randomly selected from the larger delay time to the smaller delay time. Function verification is performed using the test pattern signal for each set value of each delay element. If the stage does not function as expected, the next set value is prepared and the function verification using the test pattern is repeated. If it functions as expected, the adjustment of the delay element at that stage ends. After the adjustment of the delay element in that stage is completed, the process proceeds to the adjustment of the delay element in the subsequent stage. In addition,
For details on the method of DP itself, see Bellma
n, "Dynamic Programming," Pr
inceton Univ. pressNewJers
ey, 1957.

D) GA (Generic Algori)
thm (Genetic Algorithm)) There is no restriction on the target digital circuit. A plurality of optional delay settings (amounts) are prepared. For each delay setting, test the function of all delay elements using the test pattern signal (comparison and comparison between the circuit output value and the expected value), and find the circuit that contains the expected value (determined the match) Find the ratio of the total number of circuits to the number. The delay setting prepared in advance is selected according to the ratio, and the function test is repeated. A new set of delay settings is generated by performing a genetic operation (a method of a genetic algorithm) on the selection result of the delay settings. More specifically, each time a value of the set delay amount obtained by the coincidence determination is found, a new combination of set values to be set for all delay elements is created by using the value. If a delay setting that works as expected 100% is found, the setting is terminated. The genetic algorithm is described in "Evolving Hardware", 1995 BIT (1)
0) and JP-A-9-294069.

E) Search Method Utilizing Information from CAD In the above-described embodiments A) to D), the delay amount is searched only by the delay amount setting circuit 7, but in this embodiment, the CAD (C
Omputer Aided DesignSystem
m) provides search support. In this embodiment, the digital circuit actually manufactured does not require the delay amount setting circuit 7 and the circuit output signal line (reference numeral 9). There is only a signal line for instructing the delay amount to the delay element, and a delay amount finally set from the outside is given from this signal line.

In this embodiment, a simulation model of the digital circuit shown in FIG. 1 is virtually created on a CAD.
The circuits using the delay elements are regarded as networks connecting data signal lines. Therefore, the signal lines connecting the circuits are treated as paths in a network. C
AD calculates a delay time from data input to data output from the circuit. Further, a delay amount setting circuit 7 is also provided on the network to perform an optimal search for the delay amount. At this time, all the delay elements may be set.
A delay time (amount) search may be performed by selecting a circuit related to a path having a delay amount equal to or greater than a certain value on the network.
As the search method, any of the above methods A) to D) may be used.

In addition to the embodiment described above, the following embodiment can be implemented.

1) In the circuit example of the delay amount setting circuit shown in FIG. 2, since the number of comparators 12 is one, a selector 15 for selecting a circuit output is used.
Is provided, and the delay amounts of the plurality of delay elements are set in time series. However, if you want to shorten the set time,
Alternatively, when the delay amount is set by digital circuit simulation using a computer, a plurality of delay elements may be provided in one-to-one correspondence.

2) In the circuit configuration of FIG. 2, the data output of each circuit is selected by the selector 15. However, when the number of circuits is small, the outputs of all circuits are given to the comparator 12.
You may compare with the expected value corresponding to each output.

3) In the above-described embodiment, only one type of test pattern signal is used for comparison. However, a plurality of types of test pattern signals are prepared. Of course, a combination of the delay amounts of the delay elements may be searched. In this case, the search takes time, but the reliability of the operation of the circuit is further increased.

4) The delay amount setting circuit 7 shown in FIG. 1 may be provided in a digital circuit, or may be connected to the digital circuit from the outside to automatically set the set value of the delay time of the delay element. .

5) If an optimum set value cannot be obtained even after the above-described delay time search, the circuit itself in the digital circuit is damaged, the signal line is damaged, and the clock signal line and the delay element are damaged. Occurs. In such a case, an abnormality of the digital circuit can be detected by generating a warning signal from the delay amount setting circuit 7. When it is determined that the optimum set value cannot be obtained, the following may be performed. For example, in the full search method, the set value is slightly changed from the initial value, but if the expected value and the circuit output value do not match even if the set value is changed to the maximum delay value of the delay element,
The circuit can be determined to be abnormal.

In the random search method, it is possible to determine that the optimum set value cannot be obtained (circuit abnormality) because the number of times the set value is switched has reached the predetermined number. In other search methods, it is possible to determine that the optimum set value cannot be obtained by determining whether the set value has been switched or whether the set value has reached the upper limit. Further, a circuit for performing these determination processes may be provided in the delay amount setting circuit, and a logic circuit may be configured to execute such a processing procedure in the programmable logic array.

[0055]

As described above, claims 1 and 10
According to the invention, the phase of the clock signal constituting the digital circuit can be adjusted to be the same for all the circuits or at a predetermined timing by the delay of the delay element regardless of the length of the signal line.

According to the second and eleventh aspects of the present invention, even if there is a circuit that does not use a clock signal in the digital circuit, the operation of the entire digital circuit can be achieved by providing a delay element at the data input and / or output of the circuit. The timing can be adjusted.

According to the third and twelfth aspects of the present invention, by providing means for automatically setting the delay times of the plurality of delay elements in the digital circuit, the timing of the clock signal can be adjusted even if the digital circuit is LAI.

According to the fourth and thirteenth aspects of the present invention, a test pattern signal is supplied to the digital circuit, and a value output from the circuit in accordance with the pattern signal is compared with a predetermined value (expected value) to thereby obtain the value. It is possible to automatically determine whether or not the setting value of the delay element of the circuit is appropriate. When a determination of no is obtained, the set value can be automatically searched for by changing the set value to a predetermined value by trial and error.

According to the inventions of claims 5 to 8, and 14 to 17, the full set search method, the random search method, the DP method, and the genetic algorithm method are used in changing the delay set value, so that the optimum Setting value search can be performed.

According to the ninth and eighteenth aspects of the present invention, the simulation calculation of the digital circuit is performed by the computer, so that the delay time of the delay element can be determined even at the design stage. Further, it becomes possible to determine a set value to be given to a digital circuit having only a variable delay element by a computer.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a circuit configuration of a delay amount setting circuit.

FIG. 3 is a flowchart illustrating a setting processing procedure of a delay amount setting circuit.

[Explanation of symbols]

 1, 3, 5 register 2 decoder 3 ALU 6 delay element 7 delay amount setting circuit 8, 9 signal line 11 control unit 12 comparator 13 signal generator 14, 15 selector 16 buffer

 ──────────────────────────────────────────────────続 き Continuing from the front page (71) Applicant 599045811 Kenji Toda 1-1-4 Umezono, Tsukuba, Ibaraki Pref. Electronic Technology Research Institute (72) Inventor Tetsuya Higuchi 1-1-1, Umezono, Tsukuba, Ibaraki 4 Within the Institute of Technology, Electronic Technology Research Institute (72) Inventor Eiichi Takahashi 1-4-1, Umezono, Tsukuba, Ibaraki Prefecture Within the Institute of Technology, Electronic Technology (72) Kenji Toda Umezono, 1-chome, Tsukuba City, Ibaraki Prefecture 1-4 In-house Electronic Technology Research Institute (72) Inventor Masahiro Murakawa 1-4-1 Umezono, Tsukuba-city, Ibaraki Pref. CC08 CC14 CC16 DD06 DD13

Claims (18)

[Claims]
1. A digital circuit having a plurality of circuits that receive a clock signal and operate in synchronization with the clock signal, wherein the plurality of circuits are connected to each other, wherein the input of the clock signal to the plurality of circuits is performed. On the signal line,
A digital circuit, comprising: a plurality of delay elements capable of variably setting a delay time, and compensating for a phase shift of a clock signal by variably setting the delay times of the plurality of delay elements.
2. The digital circuit according to claim 1, wherein the plurality of circuits include a circuit that does not input a clock signal, and a delay time is provided on an input and / or output signal line of the circuit that does not input the clock circuit. A digital circuit, further comprising a delay element capable of variably setting the delay time.
3. The digital circuit according to claim 1, further comprising a delay time setting means for automatically setting a set value of the delay time of the plurality of delay elements, inside or outside the digital circuit. A digital circuit characterized by the following.
4. The digital circuit according to claim 3, wherein said delay time setting means supplies a test pattern signal to said digital circuit as an input, and output values of said plurality of circuits coincide with predetermined expected values. Determining whether the delay times of the plurality of delay elements are automatically set by performing a delay time search to change the delay times of the plurality of delay elements by trial and error until a match determination is obtained. Digital circuit.
5. The digital circuit according to claim 4, wherein the delay time search is performed according to a full search method in which a small change is made from an initial value relating to a predetermined delay time until the coincidence determination is obtained. circuit.
6. The digital circuit according to claim 4, wherein said delay time search is performed according to a random search method of randomly changing a set value of a delay element until said coincidence determination is obtained.
7. The digital circuit according to claim 4, wherein the delay time search is performed from a larger delay time to a smaller delay time when the relationship between the delay time of the delay element and the set value is a monotonically increasing function. A digital circuit according to a DP method in which when the relationship between the delay time of the delay element and the set value is not a monotonically increasing function, a set value to be changed at random is selected in the case.
8. The digital circuit according to claim 4, wherein, in the delay time search, a new combination of set values is determined using set values obtained by determining whether or not the set values of the plurality of delay elements match. A digital circuit according to a genetic algorithm method to be created.
9. The digital circuit according to claim 1, wherein the digital circuit is virtually created as a simulation model on a computer, and the delay time of the plurality of delay elements is determined based on the simulation model. A digital circuit characterized by:
10. A clock signal adjusting method for a digital circuit having a plurality of circuits that receive a clock signal and operate in synchronization with the clock signal, wherein the plurality of circuits are connected to each other. On the input signal line of the clock signal,
A method for adjusting a clock signal of a digital circuit, comprising: providing a plurality of delay elements capable of variably setting a delay time, and compensating for a phase shift of a clock signal by variably setting the delay time of the plurality of delay elements.
11. The method for adjusting a clock signal of a digital circuit according to claim 10, wherein the plurality of circuits include a circuit that does not input a clock signal, and an input and / or output of the circuit that does not input the clock circuit. A clock signal adjusting method for a digital circuit, further comprising a delay element capable of variably setting a delay time on a signal line.
12. The clock signal adjusting method for a digital circuit according to claim 10, wherein a delay time setting circuit for automatically setting a set value of the delay time of the plurality of delay elements is provided inside or outside the digital circuit. A method for adjusting a clock signal of a digital circuit, the method further comprising:
13. The method for adjusting a clock signal of a digital circuit according to claim 12, wherein the delay time setting circuit supplies a test pattern signal to the digital circuit as an input, and output values of the plurality of circuits are predetermined. Automatically set the delay time of the plurality of delay elements by performing a delay time search that changes the delay time of the plurality of delay elements by trial and error until a match determination is obtained. A clock signal adjusting method for a digital circuit.
14. The clock signal adjusting method for a digital circuit according to claim 12, wherein the delay time search is performed according to a full search method in which a small change is made from an initial value relating to a predetermined delay time until the coincidence determination is obtained. A method for adjusting a clock signal of a digital circuit, the method comprising:
15. The clock signal adjusting method for a digital circuit according to claim 12, wherein the delay time search is performed according to a random search method of randomly changing a set value of a delay element until the coincidence determination is obtained. Clock signal adjustment method for a digital circuit.
16. The method for adjusting a clock signal of a digital circuit according to claim 12, wherein in the delay time search, when the relationship between the delay time of the delay element and a set value is a monotonically increasing function, the larger delay time is used. The digital circuit according to the DP method, wherein if the relationship between the delay time of the delay element and the set value is not a monotonically increasing function, the set value to be changed randomly is selected. Clock signal adjustment method.
17. The method for adjusting a clock signal of a digital circuit according to claim 12, wherein in the delay time search, a new set value obtained by determining a match with a set value of a plurality of delay elements is used. A method for adjusting a clock signal of a digital circuit according to a genetic algorithm method for creating a combination of set values.
18. The clock signal adjusting method for a digital circuit according to claim 10, wherein the digital circuit is virtually created as a simulation model on a computer, and the plurality of delay elements are created by the simulation model. And a method for adjusting a clock signal of a digital circuit.
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US09/519,463 US6658581B1 (en) 1999-03-29 2000-03-06 Timing adjustment of clock signals in a digital circuit
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US7460630B2 (en) 2004-08-02 2008-12-02 Fujitsu Limited Device and method for synchronous data transmission using reference signal
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JP4815326B2 (en) 2006-10-31 2011-11-16 富士通株式会社 Integrated circuit timing failure improvement apparatus, integrated circuit timing failure diagnosis apparatus and method, and integrated circuit
US8261222B2 (en) 2007-11-26 2012-09-04 Nec Corporation Methods for analyzing and adjusting semiconductor device, and semiconductor system
JP2010073761A (en) 2008-09-17 2010-04-02 Fujitsu Ltd Semiconductor device, and method of controlling the same
JP5278271B2 (en) * 2009-09-29 2013-09-04 富士通株式会社 Design support program, design support apparatus, and design support method
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US7460630B2 (en) 2004-08-02 2008-12-02 Fujitsu Limited Device and method for synchronous data transmission using reference signal
US10256798B2 (en) 2015-12-02 2019-04-09 Fujitsu Limited Test method of delay circuit including delay line

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