JP2000276736A - Device and method for recording information on optical disk - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make performable a high quality data recording on an optical disk such as a DVD while appropriately maintaining the edge position of recording pulses regardless of the fluctuation in power supply voltage level and surrounding temperature. SOLUTION: The optical disk device is provided with a laser driving section 108, which drives a laser to record data on an optical disk, a recording pulse generating section 111, which generates recording pulse signals to control the switching of laser power of the section 108 using a prescribed delay circuit, a delay amount measuring section 113, which measures the amount of delay in the delay circuit of the section 111, and a recording pulse position compensating section 112 which compensates for a prescribed edge position of the recording pulses based on the measurement result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technique for recording information on an information recording medium such as an optical disk.

[0002]

2. Description of the Related Art In recent years, optical disks such as DVD-RAMs have attracted attention as large-capacity information recording media, and are being developed and commercialized as external storage devices for computers and for recording video and audio. Generally, in an optical disk, a spiral or concentric track is provided on a disk surface, and information is recorded / reproduced by irradiating a laser beam along the track. Further, the track is further divided into a plurality of sectors which are the minimum unit for recording / reproducing information data.

As one method of recording information on an optical disk, an optical modulation recording method of modulating the intensity of a laser beam applied to a track on which data is to be recorded in accordance with the data to be recorded is generally known. Include phase-change optical disks, organic dye-type optical disks, magneto-optical disks, etc.
This is a recording method applicable to a wide range of optical disc materials.

[0004] As a method for recording data on an optical disk at a high density, a pulse width modulation method (hereinafter referred to as a "PWM method") is known. The PWM method is a method in which the leading and trailing edges of a recording mark are modulated so as to correspond to 1 of a digital signal. In comparison, more bits can be allocated to recording marks of the same length, which is suitable for higher density.

[0005] In the PWM method, since the width of a recording mark has information, it is necessary to form the recording mark without distortion, that is, at the front end and the rear end uniformly. However, due to the heat storage effect of the recording film on a phase-change optical disk or the like, when recording a particularly long mark, there is a problem that the width of the recording mark in the radial direction becomes larger in the latter half and is distorted in a so-called teardrop shape. In order to solve this, a recording method has been proposed in which one recording mark is formed by irradiating a plurality of short pulse trains (for example, there is a method disclosed in JP-A-3-185628).

In addition, by changing the pulse positions corresponding to the start and end portions of the recording mark in the recording pulse train for each mark length / space length of the data to be recorded, recording is performed so that the heat between the marks is reduced. A method of compensating for a peak shift due to interference or frequency characteristics during reproduction has also been proposed (for example, there is a method disclosed in Japanese Patent Application Laid-Open No. 7-129959). As described above, forming a recording mark with high quality by changing the position of a recording pulse is generally referred to as “recording compensation”.

[0007]

When the position of a recording pulse is changed for recording compensation, it is necessary to change the edge position of the recording pulse in a time unit shorter than one channel bit of the recording data. It is difficult to generate a recording pulse by a synchronous circuit using a clock signal of one channel bit period. Therefore, in general, a configuration is employed in which the position of the recording pulse is changed using a signal delay unit capable of controlling the delay amount (for example, see Japanese Patent Application Laid-Open No.
No. 129959. ).

However, in the signal delay means, the amount of delay generally tends to change in response to a change in power supply voltage, temperature, or the like. If the change in the delay amount due to power supply voltage fluctuation, temperature fluctuation, etc. is relatively small, it does not affect the quality of the recorded data, but if the change in the delay amount is relatively large, the position of the recording pulse is appropriate. Therefore, the recording mark cannot be formed correctly, and the recording / reproducing characteristics are deteriorated.

In the conventional optical disk recording apparatus, the setting of the delay amount for a specific mark length / space length is fixedly determined. There was no means to correct it.

Further, in the conventional optical disk recording apparatus, when a plurality of pulse parts in a recording pulse are changed with different delay amounts, a separate signal delay means is provided for each pulse part and individually controlled. . Therefore, separate signal delay means are required for the number of pulse portions that need to be changed independently, and the circuit scale tends to be large. Further, as the position variable range of the pulse portion becomes larger, the delay length required for each signal delay means becomes longer, and there is a problem that the circuit scale becomes enormous.

[0011]

SUMMARY OF THE INVENTION In view of the above problems, an information recording apparatus and an information recording method according to the present invention have an object to provide means for solving the following problems. (Purpose 1) To perform high-precision recording even due to environmental changes such as power supply voltage fluctuations and temperature fluctuations of a device that records information on an optical disk. (Purpose 2) To realize high-accuracy and wide-range position control of recording pulses with a small circuit scale.

In order to achieve the above (Object 1), an information recording apparatus according to the present invention provides an optical disc by irradiating a laser beam modulated to at least two kinds of power values modulated according to data to be recorded. This is an information recording device for recording data in the information recording device. The information recording apparatus includes a delay unit, modulates data to be recorded, generates a pulse signal, corrects a predetermined edge position of the pulse signal by the provided delay unit, and outputs the corrected recording pulse. Recording pulse generating means, a laser driving means for driving a laser while switching a power value by a recording pulse signal, a delay amount measuring means for measuring a delay amount in the delay means, and a delay amount measuring result in the delay amount measuring means. And a recording pulse position correcting means for correcting a predetermined edge position of the recording pulse.

[0013] The laser driving means may include a plurality of current sources and a plurality of switches for independently turning on / off the supply of the output current from each current source to the laser. The recording pulse may be output to the laser driving unit, and the ON / OFF of a plurality of switches may be controlled by the plurality of recording pulses. Further, the recording pulse generating means includes a pulse timing generating means for modulating data to be recorded and generating a reference pulse signal, and a delay pulse having the reference pulse signal as input and having a variable delay amount from outside. And a delay amount variable type delay means for outputting.

The delay means of the recording pulse generating means may comprise a plurality of inverter elements each having an input / output connected in series, and a selection means for selecting an output of each inverter element. The predetermined edge position of the recording pulse may be corrected by controlling the output selection of the selecting means by the position correcting means.

Alternatively, the delay means of the recording pulse generating means may include a plurality of buffer elements each having an input / output connected in series, and a selection means for selecting an output of each buffer element.

Alternatively, the delay means of the recording pulse generating means may be constituted by a voltage control type delay element, and the recording pulse position correcting means controls the control voltage of the voltage control type delay element to thereby determine a predetermined recording pulse. May be corrected.

The delay amount measuring means may measure a delay amount between input and output of the delay means of the recording pulse generating means using a clock signal for delay measurement.

Alternatively, the delay amount measuring means may measure a delay difference between two types of outputs having different delay amounts of the delay means built in the recording pulse generating means, using a clock signal for delay measurement.

The recording pulse position correcting means uses the delay amount measurement result by the delay amount measuring means to determine that the delay between input and output of the delay means built in the recording pulse generating means is about one channel bit time. A predetermined delay setting value may be obtained, and the predetermined edge position of the recording pulse may be corrected based on the delay setting value.

Further, the recording pulse position correcting means uses the delay amount measurement result by the delay amount measuring means to determine a delay difference between two types of outputs having different delay amounts of the delay means built in the recording pulse generating means. It is also possible to determine a delay set value that is approximately one channel bit time and correct a predetermined edge position of a recording pulse based on the delay set value.

Further, the recording pulse position correcting means sets the predetermined edge position of the recording pulse generated by the recording pulse generating means to a different position depending on the bit length of the recording mark, the immediately preceding space length, or the immediately succeeding space length. The correction may be made.

Further, the information recording method according to the present invention uses the recording pulse generated by the recording pulse generating means,
An information recording method for recording data on an optical disc while controlling laser power, wherein a recording pulse correction step for correcting an edge position of a recording pulse during a period in which data is not recorded, and an edge recording method comprising the steps of: A data recording step of recording data using the recording pulse whose position has been corrected.

Further, another information recording method according to the present invention comprises:
An optical disc recording method for recording data on an optical disc while controlling laser power using a recording pulse generated by a recording pulse generating means, comprising: a data recording step of recording data; A verifying step of performing a verifying operation of the read data, a determining step of determining whether to correct an edge position of a recording pulse based on an error state of reproduced data in the verifying step, and an edge position of the recording pulse in the determining step. And a recording pulse correction step of correcting the edge position of the recording pulse only when it is determined that the correction is performed.

In the determination step, preferably, it is determined whether or not to correct the edge position of the recording pulse by referring to an error state of the reproduced data in a plurality of verification steps executed in the past.

The recording pulse correcting step preferably measures a delay amount of a delay unit built in the recording pulse generating unit, and corrects a predetermined edge position of the recording pulse based on the measurement result of the delay amount.

Preferably, the recording pulse correction step comprises the steps of: setting a selection signal value for determining a delay amount of the delay means of the recording pulse generation means; and measuring a delay amount with respect to the set selection signal value. Is read, and the delay amount is Tw (Tw) using the measurement result of the delay amount.
Is a time equal to one cycle of a clock used by the recording pulse generating means), and a time table relating to the edge position of the recording pulse given in advance is selected based on the obtained selection signal value. And converting the signal value into a set value table.

The time Tw may be a time corresponding to one channel bit of the recording data. Further, it is preferable that the time table includes all time information on at least a variable edge position among the respective edges of the recording pulse. Further, the time table may have individual time information for each mark length of data to be recorded, or may have individual time information for each combination of the mark length of data to be recorded and the immediately preceding space length. May be provided, or individual time information may be provided for each combination of the mark length of the data to be recorded and the immediately following space length.

In the pulse correcting step, in the recording pulse generating means comprising a plurality of stages of delay means, a delay amount is measured for each delay means group including a predetermined number of delay means. The output of the delay unit for determining the edge position of the recording pulse given in advance may be controlled based on the delay amount. At this time, in the pulse correction step, preferably, in the recording pulse generating means including a plurality of delay means, a delay amount is measured for each delay means group including a predetermined number of delay means, and the measured delay means A delay profile of the entire delay unit is calculated based on the delay amount, and an output of the delay unit for determining an edge position of a given recording pulse is controlled based on the calculated delay profile. . Further, the calculated delay profile may be a function represented by the same number of polygonal lines as the number of delay means groups. Further, in the pulse correction step, an area where the delay time of the delay means substantially coincides with one cycle of the clock signal is detected using a clock signal having a cycle equal to or less than half the total delay time of the delay means of the recording pulse generation means. The output of the delay means may be controlled based on the detection result to determine the edge position of the recording pulse given in advance.

In order to achieve the above (Object 2), a further information recording method according to the present invention forms each mark by irradiating a laser beam whose power is controlled according to a recording pulse composed of a plurality of pulse trains to an optical disk. An information recording method for performing high-precision recording of data by adaptively controlling a predetermined edge position of the recording pulse, wherein a Tw / n cycle (Tw is 1 of recording data) used for modulation of recording data.
A delay clock is generated by delaying the recording clock of the channel bit period (n is a natural number) while adaptively controlling the delay amount, and a predetermined edge position of the recording pulse is determined based on the timing of the delay clock.

Another information recording method is to delay a recording clock of Tw / n period used for modulation of recording data while adaptively controlling a delay amount, where Tw is a channel bit period of recording data. And a reference axis window signal which is a pulse-like signal of at least Tw / n time width synchronized with the rising edge or falling edge of the recording clock and whose start position can be variably controlled in Tw / 2n time units. The predetermined edge position of the recording pulse is determined based on the timing of the delay clock and the reference axis window signal.

When it is necessary to adaptively control the predetermined edge position of the recording pulse in a time range of at least d × Tw / 2n (d and n are natural numbers), the reference axis window signal is set to Tw / 2n. It is desirable to control (d + 1) types of timings in units of time.

Further, according to a different information recording method according to the present invention, a laser beam whose power is controlled according to a recording pulse obtained by synthesizing at least one of a first pulse, a multi-pulse train having a repetitive waveform of Tw period, and a last pulse. Is irradiated onto the optical disc to form one mark, and at least one of the starting edge position of the first pulse and the ending edge position of the last pulse is adaptively controlled to perform highly accurate data recording. Is an optical disc recording method defined based on a relative relationship between the start edge position of the multi-pulse train and the end edge position of the last pulse. The method includes: a) a first pulse reference clock having a Tw / n cycle whose delay is controlled at least by a relative time within a range of ± Tw / 4n with respect to a rising phase of a multi-pulse train or a phase delayed about 180 degrees from the rising phase; A Tw pulse last pulse reference clock whose delay is controlled at least within a time range of ± Tw / 4n with respect to a phase delayed by approximately 180 degrees from the rising or rising phase of the pulse train, and approximately 180 degrees from the rising or rising phase of the multi-pulse train A first pulse reference axis window signal which is synchronous with the delay phase and whose start position is at least one cycle width of the first pulse reference clock and whose start position can be variably controlled in Tw / 2n time units, and a rising phase of a multi-pulse train Or approximately 180 from the rising phase A pulse-like signal synchronized with the delay phase and having at least one cycle width of the last pulse reference clock, and a last pulse reference axis window signal whose start position can be variably controlled in a time unit of Tw / 2n; b. The start edge position of the first pulse is determined by the timing of the first pulse reference clock and the first pulse reference axis window signal, and the end edge position of the last pulse is determined by the timing of the last pulse reference clock and the last pulse reference axis window signal. Good.

Another information recording apparatus according to the present invention is an optical disk recording apparatus that records data by irradiating the optical disk with laser light whose power value is switched by a recording pulse obtained by modulating data to be recorded. . The optical disc apparatus includes: a recording clock generating unit configured to generate a recording clock having a Tw / n period; a clock delay unit configured to delay the recording clock to generate m types (m is a natural number) of delayed clocks having different delay amounts; Pulse reference signal generating means for generating m types of pulse reference signals having at least one cycle width of the recording clock by using the recording data and the recording clock; and any one of the m types of delayed clocks and m
Pulse timing signal generating means for generating m kinds of pulse timing signals in correspondence with any one of the kinds of pulse reference signals; delay amount controlling means for controlling the delay amounts of m kinds of delay clocks; Recording pulse synthesizing means for synthesizing a recording pulse by using a pulse timing signal, wherein a predetermined edge position at m positions in the recording pulse is made variable.

Further, another different information recording device is Tw
/ N recording clock generating means for generating a recording clock having a period of / n, and a total delay amount Tw / 2n for delaying the recording clock to generate m types of delayed clocks having different delay amounts from each other.
Using clock delay means having the above length, recording data and a recording clock, m kinds of pulse-like signals having a width of at least one cycle of the recording clock and having a start position variable in a time unit of Tw / 2n A pulse reference signal generating means for generating a pulse reference signal, and a pulse timing for generating m types of pulse timing signals by associating one of the m types of delayed clocks with one of the m types of pulse reference signals Signal generation means, delay amount control means for controlling the delay amounts of m kinds of delay clocks and timing of m kinds of pulse reference signals, and recording pulse synthesis means for synthesizing recording pulses using m kinds of pulse timing signals. In this case, m predetermined edge positions in the recording pulse are made variable.

Here, the pulse timing signal generating means is composed of m D flip-flops, and m kinds of delayed clocks are respectively connected to clock input terminals of the m D flip-flops, and m kinds of pulse references are provided. Signals are respectively connected to the D input terminals of the D flip-flops,
Alternatively, m types of pulse timing signals may be extracted from the Q output terminals of the m D flip-flops.

Further, a delay amount measuring means for measuring the delay amount of the clock delay means may be further provided, and the delay amount controlling means determines the m kinds of delay clocks based on the result of the delay amount measurement by the delay amount measuring means. The amount of delay may be controlled.

Another information recording method according to the present invention is an optical disk recording method for recording data on an optical disk while controlling laser power using a recording pulse modulated in accordance with recording data. Detecting the temperature of the device to be performed; determining the detected temperature change; and correcting the edge position of the recording pulse only when the temperature change is determined to be equal to or greater than a predetermined value based on the determination of the temperature change. And recording data using a recording pulse whose edge position has been corrected. At this time, instead of the temperature of the device that records data on the optical disk, the power supply voltage may be measured, a change in the measured power supply voltage may be determined, and the edge position of the recording pulse may be corrected.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an optical disk apparatus for recording information on an optical disk according to the present invention will be described below in detail with reference to the accompanying drawings.

<Structure of Optical Disk Apparatus> FIG. 1 is a block diagram showing the structure of an optical disk apparatus according to the present invention. In FIG. 1, a disk motor 102 is
1 is rotated at a predetermined rotation speed. The optical head 103 includes a semiconductor laser, an optical system, a photodetector and the like (not shown), and laser light emitted from the semiconductor laser is condensed by the optical system to form an optical spot on the recording surface of the optical disk 101. To perform data recording and reproduction. Also, the reflected light from the recording surface is condensed by an optical system in the optical head 103, and then converted into a current by a photodetector.
Further, the voltage is converted and amplified by the amplifier 104 and output as a reproduced signal.

The servo control unit 105 controls the disk motor 1
02, control for moving the optical head 103 in the radial direction of the optical disk 101, focus control for focusing the light spot on the recording surface, and tracking control for tracking the light spot at the center of the track. Note that the focus control and the tracking control include a focus error signal (an electric signal indicating a shift of a light spot from a recording surface in a direction substantially perpendicular to the recording surface of the optical disc 101) among reproduction signals output from the amplifier 104. Tracking error signal (optical disk 101
(Electrical signal indicating the deviation of the light spot from a predetermined track on the recording surface).

The reproduction signal processing unit 106 extracts a signal component corresponding to data recorded on the optical disk 101 from the reproduction signal output from the amplifier 104, binarizes the extracted signal, binarizes the binary signal with the reference clock, From, built-in PLL (short for Phase Locked Loop: phase locked loop)
Thus, a read clock and read data synchronized with the read clock are generated.

The laser drive unit 108 generates a laser drive signal so that a semiconductor laser incorporated in the optical head 103 emits light at the power for reproduction at the time of reproducing addresses and data, and at the power for recording at the time of recording.

Format encoder / decoder 107
Reproduces address information recorded on the optical disk 101 from the read clock and read data output from the reproduction signal processing unit 106, and performs recording and reproduction at a timing synchronized with a sector of the optical disk 101 based on the reproduced address position. It has a role of generating and supplying each necessary timing signal. For example, a timing signal such as a read gate necessary for binarization / PLL processing of an address or data is output to the reproduction signal processing unit 106, and light emission of recording power is permitted to the laser driving unit 108 during recording. By outputting a timing signal from a write gate or the like, data can be recorded and reproduced at a correct timing.

Further, at the time of recording, the format encoder / decoder 107 adds a redundant data such as an error correction code to user data supplied from the outside of the apparatus through the host interface 109, and further converts a bit sequence modulated according to a predetermined format. The recording pulse signal is processed into a predetermined recording pulse signal by a built-in recording pulse generation unit 111 and output to a laser driving unit 108. During reproduction, address information and data recorded on the optical disk 101 are demodulated and error-corrected based on the read clock and read data output from the reproduction signal processing unit 106, and the corrected data is transmitted to the external device via the host interface 109. Send to

Format encoder / decoder 1
07 incorporates a recording pulse position correction unit 112 and a delay amount measurement unit 113. Recording pulse position correction unit 11
Reference numeral 2 sets the position of the recording pulse signal generated by the recording pulse generation unit 111 and makes a specific edge position of the recording pulse signal variable. Delay amount measurement unit 113
Has a role of measuring a pulse delay amount by the recording pulse generation unit 111. Specific operations of the delay amount measurement and the recording pulse position correction will be described later.

The system control unit 110 interprets commands (commands) supplied from outside the apparatus through the host apparatus 109, that is, through the host interface 109, and records and reproduces data with respect to a predetermined sector of the optical disk 101. As described above, the servo control unit 105, the reproduction signal processing unit 106, the format encoder / decoder 107,
Laser drive unit 108 and host interface 109
And the like to control the operation of each part of the device.

FIG. 2 is a block diagram illustrating an example of the internal configuration of the laser driving unit 108. Laser drive unit 108
The input to the controller is a power setting 205 for determining a laser power value, and three types of recording pulses 20 modulated according to data to be recorded in the recording pulse generator 111.
6a, 206b, and 206c. Recording pulse generator 1
The method of generating the recording pulses 206a, 206b, and 206c by 11 will be described later in detail. The output from the laser driving unit 108 is an output current 20 for causing the semiconductor laser 201 built in the optical head 103 to emit light.
There are seven.

The laser driving unit 108 includes the current value control unit 2
04, four current sources 203a, 203b, 203c, 2
03d, and three switches 202a, 202b, 2
02c is built in. The current value control unit 204 receives the power setting 205 from the system control unit 110,
The output current value of each of the two current sources 203a, 203b, 203c, and 204d is controlled. Switch 202a
Turns on / off the supply of the output current of the current source 203a to the semiconductor laser 201 in accordance with the recording pulse 206a supplied from the recording pulse generator 111.

Similarly, the switch 202b turns on / off the supply of the output current of the current source 203b to the semiconductor laser 201 according to the recording pulse 206b. Similarly, the switch 202c turns on / off the supply of the output current of the current source 203c to the semiconductor laser 201 according to the recording pulse 206c. The current source 203d is
The output current of the current source 203d is always supplied to the semiconductor laser 201 as a base current.

Each switch 202a, 202b, 2
02c is connected in parallel to the anode side of the semiconductor laser 201. As a result, the output current 207 flowing to the semiconductor laser 201 is controlled by the switches 202a, 202b,
Each current source 203a, 203 supplied through 202c
b, 203c and the output current of the current source 203d. In this manner, according to the value of the current flowing through the semiconductor laser 201, it goes without saying that the power of the laser light,
As a result, the power of the light spot focused on the optical disk is controlled.

FIG. 3A shows an example of the generation timing of the recording pulses 206a, 206b, and 206c by the recording pulse generator 111, and an example of the emission waveform of the semiconductor laser 201.
FIG. 4 is a diagram schematically illustrating a recording mark formed on an optical disk with the recording. In this example, the run length (the number of bits 0 continuing from bit 1 to bit 1) is changed to a bit sequence of 1, 0 modulated according to a modulation rule in which the run length (the number of bits 0 continuing from bit 1 to bit 1) is restricted in the range of 2 to 10. On the other hand, NRZ which inverts the logic of the signal only when bit 1
It is assumed that data is modulated in the form of I (Non Return to Zero Inverted), and recording is performed by the PWM method described in the related art. That is, the NRZI H level / L
It is assumed that the width of the level, that is, the recording mark length / space length is limited in the range of 3T to 11T, respectively.

In FIG. 3A, it is assumed that time flows from left to right, and the modulated data 208 is an input to the recording pulse generating unit 111. In the figure, a waveform corresponding to a 6T mark is shown. The pulse reference clock 301 is a clock whose cycle is a time length of one channel bit,
It is used as a reference for the recording pulse generation processing in the recording pulse generation unit 111. Each recording pulse 206a, 206
b and 206c are generated at the timing shown in FIG. 3 according to the timing of the modulation data 208 and the pulse reference clock 301. The light emission waveform of the semiconductor laser 201 has a shape as shown in the figure according to the timing of each of the recording pulses 206a, 206b, 206c.

The light emission waveform for recording one mark (6T mark in this example) is divided into a plurality of pulse portions, and the first pulse portion, the multi-pulse portion, and the last They are called a pulse part and a cooling pulse part. It is known that in a recording method such as a phase change type optical disk in which a recording film is changed by heat, a method of forming one recording mark by a plurality of pulse portions in a time series as in this example is effective. ing. For example,
The multi-pulse section intermittently applies a high power and a low power to prevent a mark from becoming a teardrop shape when a relatively long mark is recorded as described in the related art. In addition, the cooling pulse section plays a role of blocking the influence of heat when recording the next mark.

On the other hand, in FIG. 3A, the vertical direction of the emission waveform, that is, the amplitude, indicates the emission power of the laser, and the power values are in ascending order of bias power 3, bias power 2, bias power 1, and peak power. Power is divided into four types. In the case of phase change recording, the phase of the recording film is crystallized by irradiating the power corresponding to the bias power 1 and the phase of the recording film is made amorphous by irradiating the power corresponding to the peak power. Basically, a portion which is made amorphous by irradiation of peak power is called a recording mark. The power of the bias power 2 or the bias power 3 temporarily reduces the heat applied to the recording film.

<Operation of Laser Driving Unit> Next, the relationship between the four types of power and the operation of the laser driving unit 108 described with reference to FIG. 2 will be described. First, bias power 3
Are the switches 202a, 202b,
202c are turned off, that is, the recording pulses 206a,
This is realized by setting all 6b and 206c to L (LOW) level. At this time, only the output current of the current source 203d is supplied to the semiconductor laser 201, and the semiconductor laser 201 emits light with power corresponding to the amplitude Pd.

The bias power 2 turns on only the switch 202a and turns off both the switches 202b and 202c.
That is, this can be realized by setting the recording pulse 206a to H (High) level and setting the recording pulses 206b and 206c to L level. At this time, the output current of the current source 203a and the current source 2
The sum with the output current of 03d is supplied to the semiconductor laser 201, and the semiconductor laser 201 emits light with power corresponding to the amplitude Pa + Pd.

The bias power 1 is applied to the switch 202a,
This can be realized by turning on both the switch 202b and turning off the switch 202c, that is, setting the recording pulses 206a and 206b to H level and the recording pulse 206c to L level. At this time, the sum of the output currents of the current sources 203a, 203b, and 203d is supplied to the semiconductor laser 201, and the amplitude Pa + Pb
The semiconductor laser 201 emits light with a power corresponding to + Pd. The peak power is equal to the switches 202a, 202b, 2
02c are turned on, that is, the recording pulses 206a, 206
This can be realized by setting all of b and 206c to the H level.
At this time, the four current sources 203a, 203b, 203
The sum of all the output currents of c and 203d is the semiconductor laser 2
01 and emits light with a power corresponding to the amplitude Pa + Pb + Pc + Pd.

Here, the power amplitudes Pa, Pb, Pc, P
d is controlled by a power setting 205 performed on the current value control unit 204, respectively. For example, the current value control unit 204 separately holds the set values for the respective power amplitudes Pa, Pb, Pc, and Pd, and sets each of the current sources 203a, 203a, and 207 to have a power amplitude corresponding to the value set by the power setting 205. The currents of 203b, 203c and 203d are controlled independently. With this configuration, the power amplitudes Pa, Pb,
Pc and Pd can be controlled independently.

Further, a first pulse rising position (hereinafter referred to as "SFP"), a first pulse falling position (hereinafter referred to as "EFP"), a multi-pulse width (hereinafter referred to as "MPW"), a last pulse rising position (hereinafter referred to as "MPW"). The “SLP”), the last pulse falling position (hereinafter “ELP”), and the cooling pulse rising position (hereinafter “ECP”)
The recording pulses 206a, 206b, and 206c can be independently changed depending on the timing.

FIG. 3B is an enlarged timing chart of the recording pulse 206a in the rising portion of the first pulse, and is for explaining an example of the first pulse rising position SFP. In the figure, the center position is a timing synchronized with the fall of the pulse reference clock 301 (see FIG. 3A), and is coded to a set value SFP = 0 for the SFP. Also, SFP
Is set a predetermined number of steps before and after the center position, for example, 10 steps are provided every 500 picoseconds,
Each set value is coded to a value indicating -10 to +10. Therefore, by giving the set value of the SFP to the recording pulse generation unit 111 as an integer in the range of -10 to +10, the rising position is changed from, for example, -5 nanoseconds to +5 nanoseconds as shown in FIG. Within the range of 5
It is possible to change in increments of 00 picoseconds.

In the example of FIG. 3B, the first pulse rising position (SFP) has been described, but other settings that can be changed (EFP, MPW, SLP, ELP, ELP).
The same applies to CP). For example, the last pulse falling position (ELP) corresponds to the pulse reference clock 301.
Is set in synchronization with the falling edge of the shift. At this time, the center position of the shift is made to correspond to the set value of ELP of 0,
By setting the set value of ELP within a predetermined integer range centered on 0, the fall position can be changed before and after the center position as a reference.

As for the duty ratio of each pulse of the multi-pulse section (hereinafter referred to as “multi-pulse”), the rising timing of the multi-pulse is synchronized with the rising timing of the pulse reference clock 301.
The falling position of the multi-pulse can be made variable by the multi-pulse width set value MPW. For example, when the multi-pulse width setting value MPW = 0, the multi-pulse duty ratio is 50%, that is, in the laser emission waveform of FIG. 3A, the emission time of the peak power and the emission time of the bias power 3 are one pair. When the set value is determined to be 1, the width can be changed before and after the duty ratio of 50% by setting the MPW in a predetermined integer range centered on 0.

Changing the position or duty ratio of the recording pulse as described above is generally called "recording compensation", and the amount of change in the position or duty ratio of the recording pulse is called "recording compensation amount". Attempts to reduce the effect of thermal interference between recording marks and increase the recording density by this recording compensation have already been made.

<Operation of Recording Pulse Generating Unit> FIG. 4 is a block diagram showing an example of the internal configuration of the recording pulse generating unit 111 according to the present invention. FIG. 12 shows the recording pulses 206 a, 206 b, and 206 from the modulated data 208 using the recording pulse generation unit 111 having the internal configuration shown in FIG.
FIG. 9 is a signal timing chart for explaining a specific operation example up to generation of c. Note that FIG. 12 shows an example of a waveform when a 6T mark is recorded in a case where PWM recording is performed using a modulation rule whose run length is limited in the range of 2 to 10, as in FIG.

In FIG. 4, the pulse timing generator 4
01 receives modulated data 208 supplied from another block and a clock 410 (one cycle is one channel bit) synchronized with the modulated data 208, and outputs four types of reference timings, that is, a first pulse reference timing 411a, a multi-pulse reference timing 412a, Last pulse reference timing 4
13a, a cooling pulse reference timing 414a is generated and output. The four types of reference timings are timings serving as references for forming timings of portions corresponding to a first pulse portion, a multi-pulse portion, a last pulse portion, and a cooling pulse portion.

First pulse reference timing 411a
Is a pulse signal having an H level for one cycle of the clock 410 from the rising edge of the modulation data 208, as shown in FIG.

The multi-pulse reference timing 412a is
As shown in FIG. 12, the clock 410 is counted from the rising edge of the modulation data 208, and the third and fourth clock waveforms are output as they are, and the other portions are kept at the L level. However, the above is a case corresponding to the 6T mark, and more generally,
The multi-pulse reference timing 412a for the mT mark (m is an integer from 3 to 11) corresponds to the modulation data 208.
From the rising edge of the clock 410, the clock waveform for (m-4) cycles from the third wave is output as it is, and the other portions are kept at the L level. m =
In the case of 3, 4 or 3T mark or 4T mark, the multi-pulse reference timing 412a remains at the L level.

The last pulse reference timing 413a is
As shown in FIG. 12, the pulse signal has an H level for one cycle from the falling position of the clock 410 2.5 cycles before the falling edge of the modulation data 208.

Cooling pulse reference timing 414a
12, the clock 41 that is 1.5 cycles before the falling edge of the modulation data 208, as shown in FIG.
This is a pulse signal having an H level for one cycle from the 0 falling position.

The pulses 411a, 412a, and 413 generated by the pulse timing generation unit 401
a and 414a respectively correspond to the corresponding pulse delay units 40
2, 403, 404, and 405 are input. Also, the SFP and EFP set by the recording pulse position correction unit 112 are given to the first pulse delay unit 402, the MPW is similarly given to the multi-pulse delay unit 403, and the last pulse delay unit 404 is given to Similarly SLP
And ELP, and a cooling pulse delay unit 405
Are similarly given an ECP.

The first pulse delay section 402 has SFP and E set by the recording pulse position correction section 112.
First pulse reference timing 41 based on FP
A first pulse start edge reference signal 411b and a first pulse end edge reference signal 411c obtained by delaying 1a by a predetermined time are output. The first pulse start edge reference signal 411b and the first pulse end edge reference signal 411c are signals for determining the start edge and the end edge of the first pulse portion, respectively.
The signal is input to the first logic element 406a. In the first logic element 406a, when the set value SFP is larger than the EFP, the logical product of the two inputs is obtained.
When the value is smaller than P, the logical sum of the two inputs is obtained and output as a first pulse signal 415. FIG. 12 shows the latter as an example. The OR of the first pulse start edge reference signal 411b and the first pulse end edge reference signal 411c is the first pulse signal 415.

The multi-pulse delay section 403 outputs a multi-pulse end edge reference signal 412c obtained by delaying the multi-pulse reference timing 412a by a predetermined time based on the set value of MPW set by the recording pulse position correction section 112. I do. When the set value of MPW is 0 or a positive value, that is, when the duty ratio of the multi-pulse portion is 50% or more, the multi-pulse end edge reference signal 412c
Falling edge determines the end edge of the multi-pulse section. When the MPW set value is a negative number, that is, the multi-pulse duty ratio is less than 50%, the rising edge of the multi-pulse end edge reference signal 412c determines the end edge of the multi-pulse part. The multi-pulse reference timing 412a and the multi-pulse end edge reference signal 412c are input to the second logic element 407a. In the second logic element 407a, when the MPW set value is 0 or a positive number, the logical sum of the two inputs is obtained. Conversely, when the MPW set value is a negative number, the multi-pulse reference timing 412a and the multi-pulse end The logical product with the inversion of the edge reference signal 412c is obtained. FIG. 12 shows the former as an example.
The logical sum of 12a and the multi-pulse end edge reference signal 412c is the multi-pulse signal 416.

The last pulse delay section 404 is based on the set value of the SLP and the set value of the ELP set by the recording pulse position correcting section 112, and delays the last pulse reference timing 413a by a predetermined time to obtain the start edge of the last pulse. The reference signal 413b and the last pulse end edge reference signal 413c are output. The last pulse start edge reference signal 413b and the last pulse end edge reference signal 413c are signals for determining the start edge and the end edge of the last pulse portion, respectively, and are input to the first logic element 406b. In the first logic element 406b, when the set value SLP is a value larger than ELP, the logical product of the two inputs is obtained. Conversely, when the set value SLP is smaller than the ELP, the logical sum of the two inputs is obtained. Output as signal 417. FIG. 12 shows the former as an example, in which the last pulse starting edge reference signal 4
The logical product of 13b and the last pulse end edge reference signal 413c is the last pulse signal 417.

The cooling pulse delay unit 405 is configured to delay the cooling pulse reference timing 414 a by a predetermined time on the basis of the ECP set by the recording pulse position correction unit 112, and provide a cooling pulse end edge reference signal 4.
14c is output. When the ECP is a positive number, the falling edge of the cooling end edge reference signal 414c determines the end edge of the cooling pulse section. Also EC
When P is a negative number, the rising edge of the cooling pulse end edge reference signal 414c determines the end edge of the cooling pulse portion. The cooling pulse reference timing 414a and the cooling pulse end edge reference signal 414c are input to the second logic element 407b. Here, when the set value ECP is a positive number, the two inputs are ORed, and conversely, the ECP is calculated. Is a negative number, the logical product of the cooling pulse reference timing 414a and the inversion of the cooling pulse end edge reference signal 414c is obtained. FIG. 12 shows the latter as an example, and the logical product of the cooling pulse reference timing 414 a and the inversion of the cooling pulse end edge reference signal 414 c is the cooling pulse signal 418.

The first pulse signal 415, the multi-pulse signal 416, the last pulse signal 417, and the cooling pulse signal 418 generated as described above are input to the pulse synthesizer 408. The pulse synthesizing unit 408 outputs three recording pulses 206a and 20 from the above four types of signals.
6b and 206c are combined and output. FIG. 12 shows a waveform example of the combined recording pulses 206a, 206b, and 206c.

As described above with reference to FIG. 4, the recording pulse generation section 111 can easily generate a recording-compensated pulse by incorporating a pulse delay section for delaying the pulse. is there.

<Specific Configuration of Pulse Delay Unit> Next, a configuration example of each of the pulse delay units 402 to 405 will be described by taking the first pulse delay unit 402 as an example. FIG. 20 is a block diagram showing an example of the internal configuration of the fast pulse delay unit 402, which is a component of the recording pulse generation unit 111 shown in FIG.

In FIG. 20, a first pulse delay section 402 is a delay circuit in which a plurality of inverter elements 2001 are connected in series, and a first pulse reference timing 411a, which is an external input, is connected to the first-stage inverter element 2001. ing. Inverter element 200
The number of stages of 1 is the number of stages that can at least obtain the delay amount that satisfies the variable range of the rising and falling edge positions of the first pulse portion. For example, the variable range of the rising edge position of the first pulse portion is the modulation data 20.
Assuming that the variable range of the falling edge position is within a range from one channel clock cycle after the rising edge of the modulated data 208 to 20 nanoseconds within the range from the rising edge of FIG. 20 nanoseconds are required. On the other hand, the inverter element 2001
Assuming that the delay amount of the two stages is 0.5 nanoseconds, 20
÷ 0.5 = 40, and the inverter element 2001 requires at least 80 stages.

The selector 2002 selects each inverter element 200
1 is connected to the output of the even-numbered stage, and selects one of the outputs of the inverter elements 2001 of the even-numbered stage according to the selection signal 419a corresponding to the first pulse start position setting SFP. Output as a reference signal 411b. The selection unit 200
3 is similarly connected to the output of the inverter element 2001 of the even-numbered stage, and according to the selection signal 419b corresponding to the first pulse end position setting EFP, the inverter elements 2
001 is selected and output as the first pulse end edge reference signal 411c.

As described above, the first pulse delay unit 4
02 can be easily configured by combining an inverter element 2001 for sequentially delaying the first pulse reference timing 411a, which is an input pulse, and selectors 2002 and 2003 for selecting an output of each inverter element. . This configuration can be similarly applied to other delay units used in the recording pulse generation unit 111 shown in FIG. 4, that is, the multi-pulse delay unit 403, the last pulse delay unit 404, and the cooling pulse delay unit 405. However, since the multi-pulse delay unit 403 and the cooling pulse delay unit each have only one delay output, only one selection unit may be used to select the output of each inverter element.

Further, the minimum adjustment step of each edge position of the recording pulse, which is the resolution of the recording compensation amount, corresponds to a delay time passing through approximately two inverter elements.

Although the inverter element 2001 is used as a delay element in the example of FIG. 20, it is possible to use another element.

FIG. 21 is a block diagram showing an example in which the first pulse delay section 402 is configured using a buffer element 2101 instead of the inverter element 2001. FIG.
1 as well as the configuration shown in FIG.
By selecting and outputting a part or all of the output of the buffer element 2101 using the selection unit 2002 and the selection unit 2003, a pulse delay output with a variable delay amount can be obtained.

FIG. 22A shows a voltage controlled delay element 2201 instead of an inverter element or a buffer element.
FIG. 9 is a block diagram showing an example in which a first pulse delay unit 402 is configured by using FIG. Voltage control type delay element 2201
22B, for example, as shown in FIG. 22B, an inductor 2202 inserted between the input and output, a variable capacitor 2203 inserted in parallel with the inductor 2202, and an inductor 2202 inserted between an intermediate position of the inductor 2202 and the ground voltage. Is a kind of phase filter composed of variable capacitance capacitors 2204, and two kinds of variable capacitance capacitors 2203,
The amount of phase shift between input and output, that is, the amount of delay between input and output, is made variable by controlling the capacity of 204 with the delay control voltage. When it is desired to obtain two types of pulse delay outputs, it can be realized by incorporating two voltage-controlled delay elements 2201 and controlling the amount of delay with separate external control voltages.

In a configuration using an inverter element or a buffer element as a delay element as shown in FIGS. 20 and 21, a configuration is generally realized by combining elements prepared as standard cells in a CMOS process, a bipolar process, or the like. However, there is an advantage that the integrated circuit (integrated circuit) can be formed relatively easily and at low cost, but the resolution of the recording compensation amount, that is, the minimum adjustment step of the recording pulse is delayed by two inverter elements or one buffer element. Because the amount is specified by the amount, the desired delay resolution may not be obtained depending on the fineness of the process. On the other hand, in the configuration using the voltage control type delay element as shown in FIG. 22, since the delay amount can be changed in an analog manner by the external control voltage, an infinitely small resolution is theoretically achieved. can get. However, it is very difficult to construct an ideal phase filter, and a relatively accurate element is required to construct an element with a good delay resolution, so that it is relatively expensive. It is desirable to select and use the most appropriate element in consideration of the required performance such as resolution and delay accuracy and the cost of the apparatus.

The recording pulse generator 11 will now be described with reference to FIG.
Although an example of the internal configuration of FIG. 1 has been described, a configuration in which the circuit size required for the delay unit can be reduced compared to the configuration of delaying the pulse as in the example of FIG. 4 will be described.

<Another Specific Configuration of Recording Pulse Generating Unit> FIG. 5 shows a recording pulse generating unit 11 different from that shown in FIG.
FIG. 2 is a block diagram showing an example of the internal configuration of FIG. FIG.
Is a recording pulse generator 111 having the internal configuration shown in FIG.
, The recording pulse 206a,
FIG. 9 is a signal timing chart for describing a specific operation example up to the generation of 206b and 206c. Note that FIG. 13 shows a case where PWM recording is performed using a modulation rule whose run length is limited in the range of 2 to 10, as in FIG.
4 shows a waveform example when recording a T mark.

In FIG. 5, the pulse timing generator 5
01 is the first pulse start end reference timing 511 upon receiving the modulation data 208 supplied from another block.
a, first pulse end reference timing 512a, multi-pulse reference timing 513a, last pulse start end reference timing 514a, last pulse end / cooling pulse start end reference timing 515a, and cooling pulse end reference timing 516a are generated and output.

The clock delay section 502 receives the modulated data 20
, An SFP, an EFP, an MPW, an SLP, an ELP, and an EC, which are set by the recording pulse position correction unit 112 with the clock 510 (one cycle being one channel bit) synchronized with the clock signal 510
Seven types of delayed clocks based on P, that is, a first pulse start position reference clock 511b, a first pulse end position reference clock 512b, a multi-pulse start position reference clock 513b, and a multi-pulse end reference clock 5
13c, last pulse start position reference clock 514b,
The last pulse end position / cooling pulse start position reference clock 515b and the cooling pulse end position reference clock 516b are output.

Here, the multi-pulse start-end reference clock 513b is a clock signal that defines the rising edge position of the multi-pulse part and serves as a reference for all pulse edges, and includes SFP, EFP, MPW, SLP,
Each set value of ELP and ECP is defined based on the time relationship with the multi-pulse start-end reference clock 513b. For example, in the case of the waveform example of FIG. 13, each set value of SFP and EFP is defined by a time relationship with respect to a falling edge of the multi-pulse start position reference clock 511b.
Each set value of LP, ELP and ECP is defined by a time relationship with respect to a rising edge of the multi-pulse start position reference clock 511b.

Further, as shown in FIG. 13, the first pulse start end reference timing 511a is
This is a pulse signal having an H level for one cycle from the rising edge of the first multi-pulse reference clock 513b from the rising edge of 08.

First pulse end reference timing 51
As shown in FIG. 13, reference numeral 2a denotes a pulse signal having an H level for one cycle from the rising edge of the modulation data 208 to the falling edge of the first multi-pulse start reference clock 513b.

The multi-pulse reference timing 513a is
As shown in FIG. 13, the multi-pulse start-point reference clock 51 of the third wave from the rising edge of the modulation data 208
The gate signal is at the H level during a period from the rising edge of 3b to the rising edge of the fifth multi-pulse start reference clock 513b. However, the above is a case corresponding to the 6T mark, and more generally,
The multi-pulse reference timing 513a for the MT mark (M is an integer from 3 to 11) corresponds to the modulation data 208.
From the rising edge of the third multi-pulse starting reference clock 513b from the rising edge of (M−
4) It becomes H level during the channel bit period. However,
In the case of M = 3, 4, that is, in the case of the 3T mark or the 4T mark, the multi-pulse reference timing 412a remains at the L level.

The last pulse start end reference timing 5
As shown in FIG. 13, the last pulse 14a, the last pulse / cooling pulse start timing reference timing 515a, and the cooling pulse end reference timing 516a stand out from the rising edge of the modulation data 208, respectively, in the multi-pulse start timing reference clock 513b. The pulse signal has the H level for one cycle longer than the falling edge, the rising edge of the fifth wave, and the falling edge of the sixth wave. However, the above is a case corresponding to the 6T mark. More generally, the last pulse start timing reference timing 5 for the MT mark (M is an integer from 3 to 11) will be described.
14a, last pulse end / cooling pulse start end reference timing 515a, and cooling pulse end reference timing 516a are the falling edges of the (M-2) th wave of the multi-pulse start end reference clock 513b from the rising edge of the modulation data 208, respectively. , (M-
1) A pulse signal having an H level for one cycle from the rising edge of the wave and the falling edge of the Mth wave.

First pulse start timing reference timing 51
1a and first pulse start position reference clock 511b
Are respectively connected to the D input and the clock input of the D flip-flop 503a, and the Q output of the D flip-flop 503a becomes the first pulse start position signal 511c.

First pulse end reference timing 51
2a and first pulse end position reference clock 512b
Are respectively connected to the D input and the clock input of the D flip-flop 503b, and the Q inverted output of the D flip-flop 503b becomes the first pulse end position signal 512c.

Last pulse start end reference timing 514a
And the last pulse start position reference clock 514b are connected to the D input and clock input of the D flip-flop 503c, respectively, and the Q output of the D flip-flop 503c becomes the last pulse start position signal 514c.

The last pulse end / cooling pulse start end reference timing 515a and the last pulse end position / cooling pulse start end reference clock 515b are connected to the D input and clock input of the D flip-flop 503d, respectively, and the Q inverted output of the D flip-flop 503d is The last pulse end position signal 515c is obtained, and the Q output is the cooling pulse start position signal 515d.

Cooling pulse end reference timing 51
6a and cooling pulse end position reference clock 516b
Are respectively connected to the D input and the clock input of the D flip-flop 503e, and the Q inverted output of the D flip-flop 503e becomes the cooling pulse end position signal 516c.

The first pulse start position signal 511c and the first pulse end position signal 512c are connected to a clock input and a reset input of a D flip-flop 505a, respectively. The D flip-flop 505a
The input is fixed at the H level. As a result, the first pulse signal 517, which is the Q output of the D flip-flop 505a, goes high at the rising edge of the first pulse start position signal 511c when the first pulse end position signal 512c is high, as shown in FIG. Rising, first pulse end position signal 512
It falls to the L level at the falling edge of c.

The multi-pulse reference timing 513a, the multi-pulse start reference clock 513b, and the multi-pulse end reference clock 513c are input to the logic element 504. When the MPW is a positive number, the logic element 504 takes the logical product of the signal obtained by ORing the multi-pulse start reference clock 513b and the multi-pulse end reference clock 513c and the multi-pulse reference timing 513a, and outputs the multi-pulse signal 518. Output as Also, the logic element 50
4 is a multi-pulse start-end reference clock 513b and a multi-pulse end reference clock 5 when the MPW is a negative number.
The multi-pulse signal 518 is obtained by multiplying the logical product of the signal of the logical product 13c and the multi-pulse reference timing 513a.
Output as

The last pulse start position signal 514c and the last pulse end position signal 515c are connected to the clock input and reset input of the D flip-flop 505b, respectively. The D input of the D flip-flop 505b is
Fixed to H level. As a result, the last pulse signal 519 which is the Q output of the D flip-flop 505b
Is the last pulse end position signal 5 as shown in FIG.
Last pulse start position signal 5 when 15c is at H level
It rises to the H level at the rising edge of 14c, and falls to the L level at the falling edge of the last pulse end position signal 515c.

The cooling pulse start position signal 515d and the cooling pulse end position signal 516c are connected to a clock input and a reset input of a D flip-flop 505c, respectively. Also, the D flip-flop 505c
The input is fixed at the H level. As a result, the cooling pulse signal 520, which is the Q output of the D flip-flop 505c, goes high at the rising edge of the cooling pulse start position signal 515d when the cooling pulse end position signal 516c is high, as shown in FIG. Rising, cooling pulse end position signal 51
It falls to the L level at the falling edge of 6c.

The first pulse signal 517, the multi-pulse signal 518, the last pulse signal 519, and the cooling pulse signal 520 generated as described above are input to the pulse synthesizer 506. The pulse synthesizing unit 506 outputs three recording pulses 206a and 20 from the above four types of signals.
6b and 206c are combined and output. FIG. 13 shows a waveform example of the combined recording pulses 206a, 206b, and 206c.

The clock delay section 502 uses a multi-stage connection of inverter elements or buffer elements and a voltage-controlled delay element, similarly to the pulse delay sections used in the recording pulse generation section 111 shown in FIG. Can be configured.

<Specific Configuration of Clock Delay Unit> FIG. 6 is a block diagram showing an example of the internal configuration of the clock delay unit 502 configured using an inverter element. In FIG. 6, a plurality of inverter elements 601 are connected in series, and a clock 510 as an external input is connected to the first-stage inverter element 601. The number of stages of the inverter element 601 is the number of stages at which a delay amount that satisfies the variable range of each edge position of the recording pulses 206a, 206b, 206c is at least obtained. For example, the recording pulses 206a, 206
The variable range of each edge position of b and 206c is ± 10 nanoseconds, and the delay amount of two stages of the inverter element 601 is 0.
Assuming 5 nanoseconds, 20 ÷ 0.5 = 40,
The inverter element 601 requires at least 80 stages.

The selection section 602 is connected to part or all of the output of each inverter element 601, and selects the selection signal 5
19, one of the outputs of the inverter elements 601 is selected and output. The selection unit 602 needs clocks with different delay amounts, and when incorporated in the recording pulse generation unit 111 shown in FIG. 5, seven types of clocks with different delay amounts (first pulse start position reference clock 511b, first clock A pulse end position reference clock 512b, a multi-pulse start reference clock 513b,
Since the multi-pulse end reference clock 513c, the last pulse start position reference clock 514b, the last pulse end / cooling pulse start position reference clock 515b, and the cooling pulse end position reference clock 516b) are required, seven selection units 602 are provided. .

The selection signal 519 is composed of a plurality of types of setting signals.
The selection signal 519a corresponding to the FP, the selection signal 519b corresponding to the first pulse end position setting EFP, the selection end position of the multi-pulse, the selection signal 519c for determining the reference position of each edge variable range of the recording pulse, and the multi-pulse width setting MPW. The corresponding selection signal 519d, the selection signal 519e corresponding to the last pulse start position setting SLP, and the selection signal 51 corresponding to the last pulse end position setting ELP
9f, a selection signal 519g corresponding to the cooling pulse end position setting ECP.

As described above, the clock delay unit 502
The configuration can be easily realized by combining an inverter element 601 for sequentially delaying an input clock and a selection unit 602 for selecting an output of each inverter element. Further, the minimum adjustment step of the recording pulse, which is the resolution of the recording compensation amount, corresponds to a delay time that passes through approximately two inverter elements.

FIG. 16 shows a clock delay section 502 using a buffer element 1601 instead of the inverter element 601.
It is a block diagram showing the example which constituted. According to the configuration shown in FIG. 16 as well, as in the configuration shown in FIG. It is possible to obtain

FIG. 17 is a block diagram showing an example in which the clock delay section 502 is configured using a voltage-controlled delay element 1701 instead of an inverter element or a buffer element. The voltage control type delay element 1701 has the same configuration as that shown in FIG. 22, and therefore the detailed description is omitted. When it is desired to obtain a plurality of types of delay clocks, a voltage-controlled delay element 170 as shown in FIG.
This can be realized by incorporating a plurality of 1s and controlling the amount of delay with separate external control voltages.

In contrast to the buffer element shown in FIG. 16, the configuration using the inverter element shown in FIG. 6 is characterized in that an inverted output, that is, an output having a phase shift of 180 degrees can be easily obtained. The size of the selection unit can be reduced by using. It is desirable to select and use an optimal element in consideration of required performance such as resolution and delay accuracy and the cost of the apparatus.

As described above, the recording pulse generating section 111 having the internal configuration as shown in FIG. 5 incorporates the clock delay section 502 for delaying the clock 510, thereby facilitating the recording-compensated pulse. Can be generated. Further, by adopting the configuration in which the clock is delayed, the circuit scale can be reduced as compared with the configuration in which the pulse is delayed as in the example of FIG. This is because when delaying a pulse, it is necessary to have a plurality of delay units corresponding to the number of edge positions to be controlled independently of a recording pulse, whereas when delaying a clock, only one clock delay unit is required to provide a plurality of delay units. This is because the timing for independently controlling the edge position can be generated.

For example, when there are six edge positions to be controlled independently like the recording pulse shown in FIG. 3, the circuit scale required for the pulse delay unit used in the configuration example of FIG.
The number of delay elements is at least six times as large as the circuit scale required for the clock delay unit used in the configuration example. This is because the variable range of each edge position is the pulse reference clock 30.
1 is less than one cycle, and the pulse reference clock 30
If the position control needs to be performed in a range exceeding one cycle of 1, the difference in circuit scale becomes even larger.

Here, it is assumed that the variable range of each edge position of the recording pulses 206a, 206b, 206c as shown in FIG. 3A is defined as shown in the following table.

[0116]

[Table 1]

In Table 1, Tw is a time length of one channel bit, and in this example, Tw is a period length of one cycle of the pulse reference clock 301. The variable range of the first pulse rising position SFP and the first pulse falling position EFP is modulated data (NRZI format) 2
08, the last pulse rising position SLP, the last pulse falling position ELP, and the cooling pulse rising position ECP are defined as relative positions to the falling edge of the modulation data 208. In this specification, modulation data 208
It is assumed that there is no skew between the pulse reference clock 301 and the rising edge of the pulse reference clock 301 and both edges of the modulation data 208 have the same phase.

As shown in Table 1, when the variable range of each pulse edge greatly exceeds 1 Tw, if the pulse shown in FIG. 4 is individually delayed and then synthesized later, The delay length of each delay unit greatly exceeds 1 Tw, and the circuit scale becomes enormous. On the other hand, while the pulse reference clock 301 is delayed to generate a plurality of delayed clocks, the pulse reference clock 30
FIG. 1 shows a method of generating a recording pulse capable of performing a wide range of pulse edge control exceeding one period of FIG.
8 will be described.

<Pulse Edge Control by Delayed Clock>
FIG. 18 is a schematic diagram for explaining a method of generating a timing signal for determining the first pulse rising position SFP as an example of the pulse edge position control. The only way to obtain a delay timing using a clock signal in which pulses of a constant cycle are continuous is to use the rising edge or the falling edge of the clock signal. The range is less than one cycle of the clock signal. In order to perform position representation over a wider range, a window signal that can be punched out at the rising edge or falling edge of the clock is provided in addition to the clock signal, and the clock signal is moved within a variable range within one cycle of the clock.
What is necessary is just to move the timing of the window signal by the unit of a half cycle of the clock signal. Here, such a window signal is referred to as a “reference axis window signal”, and the number of required timing types in units of a half cycle of the clock signal is referred to as a “number of reference axes”.

In FIG. 18A, the pulse reference clock 3
By generating the first pulse start clock 1801 and the first pulse start reference axis window signal 1802 by delaying the first pulse 01 within one cycle, the first pulse start reference axis window signal 1802 is latched by the first pulse start clock 1801. , The first pulse start timing signal 1803 is obtained. The first pulse start end reference axis window signal 1802 is an H pulse for one cycle of the first pulse start end clock 1801, and its rising edge is −1 Tw, −0.5 Tw, and 0 T with respect to the rising edge of the modulation data 208.
The control is performed at four timings of w and +0.5 Tw. That is, there are four reference axes in this case.

The reason why the timing control of the first pulse start end reference axis window signal 1802 is performed in units of 0.5 Tw is that a latch timing margin in a flip-flop or the like is secured when the actual electric circuit latches by the first pulse start end clock 1801. To do that. When it is assumed that the first pulse start end reference axis window signal 1802 is latched at the rising edge of the first pulse start end clock 1801, the setup time and the hold time need to have a timing margin.

For example, as shown in FIG. 18B, 0.25 Tw after the rising edge of the first pulse start reference axis window signal 1802, and 0.25 Tw before the falling edge of the first pulse start reference axis window signal 1802. In this case, the control may be performed within a range where the rising edge of the first pulse start clock 1801 comes.

In other words, the variable range of the first pulse start clock 1801 is ± 0.25 Tw with respect to each reference axis, that is, the rising edge or falling edge of the pulse reference clock 301. By doing so, both the setup time and the hold time of the flip-flop can be secured to 0.25 Tw or more. In addition,
The value of 0.25 Tw or more is merely an example, and a sufficient margin of the latch timing can be ensured, and a gap (a region where the rising edge of the first pulse start clock 1801 does not come) at the boundary with the variable range with respect to the adjacent reference axis. )
The variable range of the rising edge of the clock may be determined within a range in which there is no clock. For example, with respect to each reference axis, the above condition can be satisfied even when the range is 0.1 Tw in the minus direction and 0.4 Tw in the plus direction.

With the above-described determination of the variable range, the variable range of the first pulse start clock 1801 is changed as shown in FIG.
As shown in (b), as a result, the range of the first pulse rising position SFP defined in Table 1 can be satisfied. In the example shown in FIG. 18, it has been described that the first pulse rising position SFP can be variably controlled. However, other edge positions to be changed, that is, the first pulse falling position EFP, the last pulse rising position SLP, and the last pulse rising position SLP. The falling position ELP and the cooling pulse rising position ECP can be variably controlled by the same method. Table 1 shows the number of reference axes required to support the variable range of each pulse edge position.

The cycle of the pulse reference clock 301 is Tw, that is, one channel bit length.
What is necessary is just n periods (n is a natural number). The example shown in FIG. 18 is a case where n = 1, but if n is an integer of 2 or more, the variable range of the clock edge required for each edge control can be shortened. Therefore, when the clock delay control is performed using the delay unit configured by connecting the unit delay elements shown in FIG. 6 or FIG. 16 in multiple stages, the circuit scale can be reduced. n
Is greater than or equal to 2, the pulse reference clock 301 can be easily generated by multiplying the clock using a PLL or the like. It is needless to say that setting the frequency of the clock to be a multiple of Tw improves the affinity with other functional blocks that operate in synchronization with the channel clock, such as a modulation circuit, and facilitates the circuit configuration.

However, setting n to a large value means increasing the frequency of the pulse reference clock 301, which requires a high-speed operation of the circuit, thereby increasing the power consumption of the circuit. Also, setting n to an excessively large value is not realistic in terms of the stability of circuit operation. It is necessary to select the most efficient value of n in consideration of the circuit scale and the clock frequency.

As described above, by using both the clock delay control and the timing control of the reference axis window signal for latching with the delayed clock, a wide range of position control over the clock cycle can be performed. Formalization is possible as shown below.

The one channel bit period of the recording data is Tw
When a clock signal having a Tw / n cycle (n is a natural number) is delay-controlled within a range of at least Tw / 4n, a pulse-like signal having at least a Tw / n time width is provided, and
The start position is continuous in Tw / 2n time units (d +
1) By generating a reference axis window signal controlled at various types of timing (d is a natural number) and using a clock signal subjected to delay control and a window signal subjected to timing control, d
Pulse delay control is possible in a time range of × Tw / 2n.

<Recording Pulse Generation Unit for Pulse Edge Control Using Delayed Clock> FIG. 19 shows the internal configuration of a recording pulse generation unit 111 capable of performing pulse position control in a range exceeding one cycle of the pulse reference clock 301. Is shown. Among the components shown in FIG. 19, those denoted by the same reference numerals as those in FIG. 5 are blocks having the same functions.
The description is omitted.

The pulse timing generator 1901 receives the modulation data 208 supplied from another block, and receives a first pulse start reference axis window signal 1911a, a first pulse end reference axis window signal 1912a, a multi-pulse reference axis window signal 1913a, and a last pulse. Start end reference axis window signal 1914a, last pulse end / cooling pulse start end reference axis window signal 1
915a: Generate and output a cooling pulse end reference axis window signal 1916a.

Here, the pulse timing generator 1901
Will be described with reference to FIG. 23. In FIG. 23, first, the pulse generation unit 2301
8 and the multi-pulse start-end reference clock 513b as inputs, and outputs five types of timing signals. The five types of timing signals include a first first pulse start timing signal 2306a, a first first pulse end timing signal 2307a, a first last pulse start timing signal 2308a, a first last pulse end timing signal 2309a, and a first Is the cooling pulse end timing signal 2310a. Assuming that the variable range of each edge position of the generated recording pulse is defined as shown in Table 1, each timing signal can be described as follows.

That is, the first first pulse start end timing signal 2306 a is 1 Tw rising from a position 1 Tw before the rising edge of the modulation data 208.
An H pulse having a width (H is a high level of a digital signal). The first first pulse end timing signal 2307a is a 1 Tw width H pulse rising from the same position as the rising edge of the modulation data 208.
In addition, the first last pulse start timing signal 2308
a is 3 with respect to the falling edge of the modulation data 208.
This is an H pulse of 1 Tw width rising from the position before Tw. Also, the first last pulse end timing signal 23
09a is a 1 Tw width H pulse rising from a position 3 Tw before the falling edge of the modulation data 208. The first cooling pulse end timing signal 2310a is a 1 Tw width H pulse rising from a position 2 Tw before the falling edge of the modulation data 208.

The first first pulse start timing signal 2306 a is composed of three D flip-flops 2303.
a, 2303b, and 2303c, further 0.5 Tw
, And the second, third, and fourth first pulse start timing signals 2306b, 2306c,
306d. Further, the SFP reference axis selection unit 2304a
Converts four types of inputs, that is, first to fourth first pulse start timing signals 2306a to 2306d, into SFP
The signal is selected according to the reference axis selection signal 2311a, and is output as the first pulse start end reference axis window signal 1911a.

The first fast pulse end timing signal 2307a is composed of three D flip-flops 2303d,
The signals are further delayed by 0.5 Tw by 2303e and 2303f, and the second, third, and fourth first pulse end timing signals 2307b, 2307c, and 230, respectively.
7d. Further, the EFP reference axis selection unit 2304b
The type input, that is, the second to fourth first pulse end timing signals 2307b to 2307d are selected in accordance with the EFP reference axis selection signal 2311b and output as the first pulse end reference axis window signal 1912a.

First last pulse start timing signal 2
Reference numeral 308a denotes two D flip-flops 2303g, 23
03h, the signal is further delayed by 0.5 Tw, and the second and third last pulse start timing signals 230, respectively.
8b and 2308c. In addition, SLP reference axis selector 2
Reference numeral 304c designates three types of inputs, that is, the first to third last pulse start timing signals 2308a to 2308c as S
The signal is selected according to the LP reference axis selection signal 2311c, and is output as the last pulse start end reference axis window signal 1913a.

First last pulse end timing signal 2
Reference numeral 309a denotes four D flip-flops 2303i and 23
03j, 2303k, and 2303, further 0.5
The second, third, fourth, and fifth last pulse end timing signals 2309b and 2309 are respectively delayed by Tw.
c, 2309d, and 2309e. Furthermore, the ELP reference axis selection unit 2304d has four types of inputs,
Last pulse end timing signals 2309b to 23
09e in accordance with the ELP reference axis selection signal 2311d and the last pulse end reference axis window signal 1914a.
Output as

The first cooling pulse end timing signal 2310a has seven D flip-flops 2303m,
2303n, 2303o, 2303p, 2303q, 2
The second, third, fourth, fifth, sixth, seventh, and eighth cooling pulse end timing signals 231 are further delayed by 0.5 Tw by 303r and 2303s, respectively.
0b, 2310c, 2310d, 2310e, 2310
f, 2310 g, and 2310 h. Further, the ECP reference axis selection unit 2304e has seven types of inputs, that is, second to eighth inputs.
The cooling pulse end reference axis window signal 1 is selected according to the ECP reference axis selection signal 2311e.
915a.

Here, in the case of this example, the timings of the third first pulse start timing signal 2306c and the first first pulse end timing signal 2307a are exactly the same. Therefore, the output 23 of the pulse generation unit 2301
07a and the D flip-flop 2303d are deleted.
By connecting the Q output 2306d of the flip-flop 2303c to the D input of the D flip-flop 2303e,
Third and fourth fast pulse start timing signals 23
The same function can be satisfied by substituting the first and second first pulse end timing signals 2307a and 2307b with 06c and 2306d, respectively, and the number of circuits can be reduced.

In the case of this example, the timing of the first last pulse start timing signal 2308a and the timing of the first last pulse end timing signal 2309a are exactly the same, and the fifth last pulse end timing signal 2309e is used.
And third cooling pulse end timing signal 2310
The timing of c is exactly the same. Therefore, the outputs 2309a and 2310a of the pulse generation unit 2301, the D flip-flops 2303i, 2303j, 2303m and 2
303n is deleted, and the D flip-flop 2303
h output 2308c to D flip-flop 2303k
Of the D flip-flop 2303l
The output 2309e may be connected to the D input of the D flip-flop 2303o.

As a result, the first, second, and third last pulse start timing signals 2308a, 2308b, and 23
008c and the fifth last pulse end timing signal 2
309e, the first, second, and third last pulse end timing signals 2309a, 2309b, and 2309, respectively.
c and the third cooling pulse end timing signal 23
By substituting 10a, the same function can be satisfied, and the number of circuits can be reduced.

Further, other than the circuit configuration described above, any circuit configuration may be used as long as the same function can be satisfied. It is sufficient that the reference axis window signal can be generated at a timing corresponding to the number of reference axes for each pulse edge position control.

As described above, the recording pulse generator 111 capable of controlling the pulse position in a range exceeding one cycle of the pulse reference clock 301 has been described as shown in FIGS. 19 and 23. By adopting such a configuration, the possible scale required for the delay unit can be significantly reduced as compared with a configuration in which an individual pulse delay unit is provided for each pulse portion as shown in FIG.

For example, when there are six edge positions to be adaptively controlled as in this embodiment, even if the start and end delay elements are shared in the configuration shown in FIG. However, in the configuration shown in FIG. 19, only one clock delay unit is required.

In order to support the variable range of Table 1, the delay length of each pulse delay unit in FIG. 4 requires a net delay amount with respect to the variable range of each edge position in Table 1. The clock delay unit 502 in FIG. 19 only needs to have a delay amount of 1 Tw.

<Compensation for Variation of Delay Amount in Delay Unit> The internal configuration example and the internal operation of the recording pulse generation unit 111 that generates the recording pulses 206a, 206b, and 206c from the modulated data 208, which is a feature of the present invention, will be described in detail. I have mentioned. Next, even when the amount of delay in the delay unit, which is one of the internal components of the recording pulse generation unit 111, fluctuates due to external factors such as a temperature change and a power supply voltage change, the recording pulses 206a, 206b, and 206c
The following describes a method and a specific configuration example in which each edge position is maintained at an appropriate position so that the recording signal quality can be kept high under any circumstances. This is another feature of the present invention, and the object can be achieved by the configuration and method described below.

First, the effects of temperature changes and power supply voltage changes when a clock delay unit or a pulse delay unit is first configured using delay elements will be described in detail, and then a specific configuration and method for compensating the effects will be described. I will mention it.

<Variation in Delay Amount Due to Temperature Change and Power Supply Voltage Change> FIG. 7 shows, as an example of a delay unit, the selection signal value of the clock delay unit 502 whose internal configuration has been described with reference to FIG. It is a schematic diagram for demonstrating a relationship. The selection signal value described here is the selection signal 51
9, which determines the number of stages through which the inverter element 601 passes. As a result, the delay amount of the delay clock is controlled. Here, the clock delay unit 5
02, the number of stages of the inverter element 601 is 128
Suppose that the delay clock to be selected is in phase with the input clock 510, that is, only the output of the even-numbered stage inverter element 601 is selected. The delay amount near the middle is obtained by the selection signal value coded to 0 in decimal, and the delay amount decreases as the absolute value increases in the minus direction, and increases as the absolute value increases in the plus direction. When the selection signal values are allocated as described above, the relationship is as shown in FIG.

The selection signal value ± N has a relative delay of about ± 0.5 with respect to the delay clock corresponding to the selection signal value 0.
The selection signal value is defined as Tw. Here, Tw is one cycle of the clock 510, that is, one channel bit cycle. The value of N is always constant unless the amount of delay per stage of the inverter element 601 changes, but in an actual device, the amount of delay per stage of the inverter element 601 due to temperature change and power supply voltage change. Due to fluctuations, the value of N is not constant.

FIG. 8 is a graph showing the relationship between the selection signal value of the clock delay unit 502 on the horizontal axis and the delay time between the input and output of the clock delay unit 502 on the vertical axis. FIG.
(B) is a graph at normal temperature and normal power supply voltage. At this time, the selection signal value whose delay amount relative to the delay clock corresponding to the selection signal value 0 is ± 0.5 Tw is ± No.
And On the other hand, FIG. 8A is a graph under a condition of a low temperature or a high power supply voltage. At this time, a selection is made such that the delay amount relative to the delay clock corresponding to the selection signal value 0 is ± 0.5 Tw. The signal value is ± Ns. Also,
FIG. 8C is a graph under the condition of high temperature or low power supply voltage. At this time, the selection signal value whose delay amount relative to the delay clock corresponding to the selection signal value 0 is ± 0.5 Tw is ± Nf.

In general, the delay time between the input and output of the inverter element becomes relatively shorter as the environmental temperature where the element is placed is lower, and becomes longer as the environmental temperature is higher. Also,
Generally, the delay time between input and output of an inverter element becomes relatively longer as the power supply voltage applied to the element is lower, and becomes relatively shorter as the power supply voltage applied to the element is higher.
Accordingly, as shown in FIGS. 8 (a) to 8 (c), the slope of the graph increases as the graph on the right side increases. Conversely, the magnitude relationship of the selection signal value under each condition is represented by the relationship of Ns>No> Nf. Holds.

As described above, the relative delay amount per selection signal value fluctuates due to a change in temperature and a change in power supply voltage. As a result, the predetermined edge position of the recording pulse is an optimum value for performing high-quality recording. The problem arises that it deviates. In order to solve this problem, a delay amount measuring unit for measuring a delay difference between two signals having two kinds of delay amounts is provided, and recording compensation based on the delay amount measured by the delay amount measuring unit is performed. A configuration for updating the set value is proposed.

<Delay Amount Measurement Unit> FIG. 10 is a block diagram showing the configuration of the delay amount measurement unit 113. First input 1001, second input 1002, clock 1 for delay measurement
003 is input from outside and the delay measuring clock 100
3, a delay difference between a predetermined edge of the first input 1001 and a predetermined edge of the second input 1002 is measured using the delay measurement clock 1003, and the measurement result is output as a delay amount measurement result 1004. It is a configuration to do.

A first input 1001 and a second input 1002
What signal is input as the recording pulse generator 111
Depends on the internal configuration of In the case of the configuration shown in FIG. 4, the first pulse start edge reference signal 411b and the first pulse end edge reference signal 411c, which are the outputs of the first pulse delay section 402, are respectively input to the first input 1001 and the second input 1001.
1002. As a result, the relationship between the delay difference between the two outputs in the first pulse delay unit 402 and the set values of the first pulse rising position setting SFP and the first pulse falling position setting EFP becomes clear from the delay amount measurement result.

In FIG. 4, the output of the delay unit different from the first pulse delay unit 402 is used as the delay amount measurement unit 113.
May be input. In order to accurately measure all the delay amounts of the four types of delay units, all outputs of the delay units should be input to the delay amount measurement unit 113. However, the configuration of the internal delay element of each delay unit is In the same case, it is not necessary to measure all delay amounts, but rather, it is desirable to measure only one typical output of the delay unit in consideration of the time required for measurement and the scale of the measurement unit.

On the other hand, in the case of the configuration of FIG. 5, the first pulse start position reference clock 511b and the first pulse end position reference clock 512b, which are the outputs of the clock delay section 502, are used as the first input 1001 and the second input 1002, respectively. I have. Thereby, the clock delay unit 50
The relationship between the delay difference between the two outputs 511b and 512b in 2 and the set values of the first pulse rising position setting SFP and the first pulse falling position setting EFP becomes clear from the delay amount measurement results.

It should be noted that also in FIG.
The other two outputs may be input to the delay amount measurement unit 113, but it is not necessary to measure all delay differences between the seven types of outputs. This is because the clock delay unit 502 is constituted by a single delay element group, so that it can be said that the delay amount per set value is almost the same regardless of the output.

It is to be noted that the first input 1001 is used as an input of one of the delay units, and the output of the delay unit selected as the input is used as the second input.
May be input 1002. For example, in FIG. 4, the input 411a of the first pulse delay unit 402 is a first input 1001, and one of the outputs 411b of the first pulse delay unit 402 is a second input 1002.
Thus, the delay difference between the input and output of the first pulse delay unit 402 and the first pulse rising position setting SF
The relationship with the set value of P becomes clear from the delay amount measurement result. In FIG. 5, the input 51 of the clock delay unit 502
0 is a first input 1001, and one of the outputs 511 b of the clock delay unit 502 is a second input 1002. Thus, the relationship between the delay difference between the input and output of the clock delay unit 502 and the set value of the first pulse rising position setting SFP becomes clear from the delay amount measurement result.

As the delay measurement clock 1003, the higher the frequency, the smaller the resolution can be measured. However, there is a limit to the frequency. Considering the stability of the circuit operation and the power consumption, it is not preferable to use one having an extremely high frequency. Therefore, the recording pulse generator 111 is used as the delay measuring clock 1003.
, A first input 1001 and a second input 10
It is desirable to configure the delay amount measurement unit 113 so as to be able to detect a set value at which the delay difference between the set value 02 and the set value becomes 1 Tw.

FIG. 11 is a block diagram showing a more detailed configuration of delay amount measuring section 113. The delay amount measurement unit 113 shown in FIG. 11 measures the clock delay amount by the clock delay unit 502 for the recording pulse generation unit 111 including the clock delay unit 502 shown in FIG. .

That is, an output of the clock delay unit 502 is input as a first input, and another output of the clock delay unit 502 is input as a second input. The first window generation unit 1101 receives a first input and generates a first window signal 1110. The second window generation unit 1102 receives the second input and generates a second window signal 1111. The two window signals are OR
An OR operation is performed by the element 1104 to form a measurement window signal 1113. The counting unit 1105 includes a measurement cycle signal 1112 determined by the count cycle determination unit 1103.
During the period of, the H level section of the measurement window signal 1113 is counted using the delay measurement clock. Here, the first output of the clock delay unit, which is the same as the first input, is used as the delay measuring clock. Measurement cycle signal 11
The result counted by the counting unit 1105 in one cycle of 12 is supplied to the D input of the D flip-flop 1106 as a count output 1114. A measurement cycle signal 1112 is connected to the clock input of the D flip-flop 1106, and with this configuration, a count result for each measurement cycle is output as a delay amount measurement result.

FIG. 11 shows an example in which the delay amount measuring unit 113 applied to the recording pulse generating unit 111 having the internal configuration shown in FIG. However, the present invention is not limited to this. As described in the description of FIG. 10, the delay difference between the input and output of the clock delay unit 502, the input and output of each of the pulse delay units 402, 403, 404, and 405 in FIG. As for the part to be
1 can be realized with the same configuration.

The delay amount measuring section 113 shown in FIG.
FIG. 14 is a timing chart for explaining a process of detecting a set value at which the delay difference between the first input 1001 and the second input 1002 is 1 Tw.

FIG. 14A is a timing example when the delay difference between the first input 1001 and the second input 1002 is less than 1 Tw. As shown in the figure, since the H level section of the measurement window signal 1113 is less than 2 Tw at this time, if the cycle of the measurement cycle signal 1112 is 100 cycles of the cycle of the window signals 1110 and 1111, the count result is always It will be 100.

FIG. 14B shows an example of timing when the delay difference between the first input 1001 and the second input 1002 is approximately 1 Tw. At this time, the H level section of the measurement window signal 1113 is 2 Tw, and the cycle of the measurement cycle signal 1112 is equal to the window signals 1110 and 111.
Assuming that one cycle corresponds to 100 cycles, the count result is always 200.

That is, by gradually changing the delay difference between the first input 1001 and the second input 1002 from a set value of less than 1 Tw to a setting of 1 Tw or more,
The delay amount measurement result as the count result is from 100 to 200
Changes to It can be said that the change point is a set value at which the delay difference becomes substantially 1 Tw.

The operation of the apparatus will be described in further detail. When the delay setting of the delay unit built in the recording pulse generation unit 111 is changed by the recording pulse position correction unit 112, the two delay signals are output by the delay amount measurement unit 113. It is possible to search for a set value in which the delay amount between them is 1 Tw.

<Calibration of Setting of Recording Compensation Amount> Next, how to specifically calibrate the setting of the recording compensation amount using the set value searched in this way will be described.

As described in the prior art, as a recording compensation method in the optical disk recording apparatus, at least one of the self-mark length, the immediately preceding space length, or the immediately succeeding space length, or a combination thereof is used. There has been proposed a method of determining a predetermined edge position and defining the determined edge position with respect to a time with respect to a reference position. According to this method, the recording compensation amount for a predetermined pulse edge position is defined by a time table including the number of each mark / space combination. Replace the specified time table with the set value table as described above, and update the set value table so that the specified time table will be in accordance with the specified time table even if there are temperature fluctuations and power supply voltage fluctuations. Table calibration ". The time table is disclosed in detail in, for example, U.S. Patent Application No. 09-352,211 and the contents thereof are incorporated herein by reference.

<Calibration of Recording Compensation Table> FIG. 15 is a flowchart showing a specific process of a method of calibrating the recording compensation table in the optical disc recording apparatus according to the present invention. As shown in the figure, when the start of the calibration of the recording compensation table is instructed, first, the selection signal ± N is set (step 1). That is, the system control unit 110
The selection signal ± N is set via the recording pulse position correction unit 112, and as a result, the first and second signals of the delay amount measurement unit 113 are set.
The number of delay stages for the input is set. Thereafter, the delay measurement result for the selected number of delay stages is read (step 2).

That is, the first input and the second input corresponding to the selected number of delay stages are input to the delay amount measurement unit 113, and the system control unit 110 reads the delay amount measurement result corresponding thereto. Thereafter, based on the read delay amount measurement result, the system control unit 110 determines whether the current delay amount is approximately 1 Tw (step 3). If it is determined that the delay amount is less than 1 Tw, the set value N becomes N +
The value is incremented to 1 (step 4), and the process returns to step 2. If it is determined that the delay amount is approximately 1 Tw, the time table is converted into a set value table using the value of the selection signal N (step 5).

FIG. 9 is a schematic diagram showing an example of conversion of the recording compensation amount from the time table to the set value table. FIG.
In the example, the predetermined edge position of the recording pulse is determined by a combination of the length of the mark (self-mark) to be recorded and the space length immediately before the self-mark.

That is, the self mark length is 3 Tw, 4 Tw, 5
3 types of Tw or more, and the previous space length is 3Tw, 4T
3 × 3 = 9 in combination with w, 5 Tw or more
FIG. 9 shows a time table in which the edge positions are defined by time. Here, 1 Tw = 17 nanoseconds, and FIG.
As described in 1, the setting value when the delay difference between the two inputs obtained by using the delay amount measuring unit 113 becomes ± 0.5 Tw is set to N (for example, the values of Ns, No, and Nf shown in FIG. 8). ), A setting value table corresponding to the time table can be created as shown in FIG. Here, the value of each entry of the setting value table is calculated by adding N / (0.5T) to the value (-1, -2, +2, +3, etc.) of the corresponding entry of the time table.
The value is obtained by multiplying the value of w). Note that the value of each entry obtained in this manner is not always an integer value,
The actual delay setting is given as an integer value. Therefore, it is necessary to perform a rounding process such as rounding to convert the value to an integer value.

The values in the set value table are given by a proportional expression using N as a constant. Therefore, when the value of N increases due to factors such as temperature and power supply voltage, the absolute value of the set value also increases. An increase in the value of N means that the set value is 1
This means that the delay amount per step is smaller than the standard. At this time, if the absolute value of the set value increases, the difference in the number of delay stages between the set value 0 (reference position) and the set value that determines the predetermined edge position also increases. In other words, when the delay amount per step of the set value is smaller than the standard, the number of stages increases, so that the delay amount of the predetermined edge position from the reference position is kept constant.

Conversely, when the value of N decreases, the absolute value of the set value also decreases, and the difference in the number of steps from the reference position (set value 0) also decreases. In other words, when the delay amount per step of the set value is larger than the standard, the number of stages is reduced, and the delay amount of the predetermined edge position from the reference position is kept constant.

Therefore, by converting the set value based on the value of N and correcting the predetermined edge position of the recording pulse using the converted set value by the method shown in FIG. Even if the delay amount of the delay unit fluctuates due to fluctuations in the power supply voltage or the like, the recording compensation amount is kept constant. As a result, the temperature
An excellent effect of preventing the recording characteristics from deteriorating due to external factors such as power supply voltage fluctuation can be obtained.

In the time table shown in FIG. 9, each piece of time information indicating a predetermined edge position of a recording pulse is individually determined by a combination of the self-mark length and the immediately preceding space length, but is not limited thereto. Not something. A combination of the self-mark length and the immediately following space length may be used, or the case may be divided only by the self-mark length. For example, when the recording pulse as shown in the example of FIG. 2 is used, the start edge position SFP of the first pulse is individually determined for each combination of the self mark length and the immediately preceding space length, and the end edge position ELP of the last pulse is determined by the self. If a method of determining each combination of the mark length and the immediately preceding space length is adopted, it is effective from the viewpoint of compensating for thermal interference between marks.

Although the method of calibrating the recording compensation table as shown in FIG. 15 has been described for the recording pulse generator 111 having the clock delay unit shown in FIG. 6, the clock delay shown in FIG. Even when using a part,
The same applies.

For the clock delay section using the voltage-controlled delay element shown in FIG. 17, since the delay selection signal is not a discrete value but a voltage that changes in an analog manner,
The method shown in FIG. 15 cannot be applied as it is. However, the selection signal value + N / − in step 1 of FIG.
N is the delay control voltage Vn / V-n, respectively.
Can be similarly applied by replacing the operation of incrementing the N value by +1 with the operation of changing the delay control voltage Vn to (Vn-Vs) and the delay control voltage V-n to (Vn + Vs). Here, Vs is a delay control voltage corresponding to the minimum change unit of the required delay amount. By increasing or decreasing the current delay control voltage by Vs,
The delay amount increases or decreases by one delay stage number in the example of FIG.

<Correction of Variation of Components of Delay Unit> With the method described above, the recording compensation amount can be kept constant even if the delay amount of the delay unit fluctuates due to fluctuations in temperature, power supply voltage, and the like. It was shown that. By using this method, a great effect can be obtained when the delay amount of the entire delay unit fluctuates. However, there is a problem that it is difficult to obtain a great effect with respect to variations between individual elements constituting the delay unit.

Here, the delay variation between the elements means the inverter element 601 in the case of the configuration of the clock delay section 502 shown in FIG. 6, the buffer element 1601 in the case of the configuration shown in FIG. In the case of the configuration shown, it refers to the variation with respect to the delay amount existing between each element such as the voltage control type delay element 1701.

When the delay unit shown in FIG. 6 or FIG. 16 is incorporated in a digital IC (standard cell / gate array or the like), it can be configured using general-purpose logic cells. Variations in the amount of delay occur due to variations in the wiring load between the logic cells, the driving capabilities of the transistors forming the logic cells, and the like. Also, in the case of the voltage control type delay element shown in FIG. 17, it is actually quite difficult to make the delay between input and output completely linear with respect to the delay control voltage. May also be present. Therefore, in the actual device, the characteristics of the delay unit are not ideal straight lines such as the relationship between the selection signal value and the delay time shown in FIG. 8, but have characteristics having a certain range of variation.

FIG. 24 shows a delay unit (FIG. 6) in an actual device.
In this case, the horizontal axis indicates the selection signal value, and the vertical axis indicates the total delay time between input and output and the delay time between adjacent selection signal values. It is the graph which took the difference. As shown in the figure, the differential delay time is distributed within a range having a certain width, and it can be seen from this distribution that the delay time varies considerably depending on the selection signal value.

As described above, when there is variation in the delay time, the method described with reference to FIG. 15 and the like, that is, the time table is converted into the set value table using the selection signal value N having the total delay amount of 1 Tw. In the method, the edge position of the recording pulse varies as a result. This is because the above method assumes that the characteristic of the delay unit is an ideal linear characteristic and replaces the time with a set value. Therefore, if there is a variation as shown in FIG. 24, the variation deviates from the ideal linear characteristic. This is because the component directly leads to an error in the edge position of the recording pulse.

Therefore, a method for minimizing the error in the edge position of the recording pulse even if there is variation among the individual elements constituting the delay section will be described below.

First, the delay section is divided into a plurality of areas. For example, as shown in FIG. 25A, the selection signal value is divided into a negative region and a positive region centered on 0. That is,
A plurality of inverters constituting the delay unit are divided into a group of inverters having a negative selection signal value to be output (a group of inverters between points A and B) and an inverter having a positive selection signal value to be output. Group consisting of (B
(A group of inverters between point C and point C).

Next, the delay time is separately measured for each of the divided regions (groups). The measurement of the delay time
For example, this can be performed using the delay amount measurement unit shown in FIG. However, since the delay unit is divided into a plurality of regions, the delay time is shortened. Therefore, it is necessary to use a delay measurement clock having a short cycle. In the example of FIG. 25A, the selection signal value is -3.
Point 2 is point A and point 0 is B
The point and the point at which the selection signal value is +32 are designated as point C. The delay time in the negative region is measured from two points AB. The delay time in the positive region is measured from two points of BC.

When the measurement of the delay time for each of the divided areas is completed, a selection signal value corresponding to a predetermined edge position of the recording pulse can be obtained based on the measurement result.

For example, as shown in FIG. 25A, when the clock delay unit is divided into a negative region and a positive region, the delay amount per set value step is positive / negative separately. To determine the value, whether the determined edge position is positive or negative is converted into a selection signal value by a different conversion formula as shown below. S (+) = t ÷ a (+)... When t ≧ 0 S (−) = t ÷ a (−)... When t <0 Here, S (+), S (−) Represents the selection signal value in the positive and negative regions, respectively. t represents the determined edge position as a relative time with respect to the reference axis. a (+) and a (-) represent the slope of the graph in the positive and negative regions, ie, the amount of delay per step. Note that the slope a (-) is A
It is determined by dividing the measurement result of the delay time between B by the number of steps 32. The slope a (+) can also be obtained by dividing the result of measuring the delay time between BC by the number of steps 32. More generally, the slope a (-) is a delay time T _AB between _AB.
The obtained by dividing the number of steps N _AB between AB. Also, the slope a (+) is the delay time T _BC between _BC and B
It is obtained by dividing by the number of steps N _BC between C. FIG. 26 shows an example of a set value table when the variation correction of the components of the delay unit is taken into consideration with respect to the time table shown in FIG. As described above, by including the coefficients a (+) and a (-) in each entry of the setting value table, the variation of the elements can be corrected. The value of each entry obtained in this manner is not always an integer value, but the actual setting of the delay unit is given as an integer value. Therefore,
It is necessary to perform rounding processing such as rounding off to convert to an integer value.

As described above, the clock delay unit is divided into two parts,
By measuring the delay time for each of the divided regions and calculating the slope of the graph based on the measurement result, it is possible to convert the edge position time into a selection signal value by two-point polygonal approximation as shown in FIG. it can. For this reason, the setting error can be further reduced as compared with the case where interpolation is performed by linear approximation from the delay time measurement result of the entire delay unit.

Here, the setting error can be further reduced by further increasing the number of divisions of the delay section. For example, a case where the delay unit is divided into eight will be described with reference to FIG.

In the example shown in FIG. 27, the selection signal value -32 to +32 is divided into eight every four steps, and A, B, C, D, E, F, G, H, I Points. Next, the delay time of each divided area is represented by AB, BC, C
Measurement is performed between two points of D, DE, EF, FG, GH, and HI.

When the delay time for each of the eight divided areas has been measured, the selection signal value corresponding to the predetermined edge position of the recording pulse can be obtained based on the measurement result. At this time, since the approximation can be made by using a polygonal line of eight points, interpolation processing with higher accuracy can be performed as compared with the case of dividing into two.

As described above, the delay section is divided, the delay time for each divided area is measured, and based on the measurement result,
By controlling the edge position of the recording pulse, it is possible to generate the recording pulse timing with high accuracy even when the delay unit varies, as compared with the case where the delay unit is not divided.

Further, if the number of divisions of the delay section is increased, more detailed interpolation processing can be performed, so that the accuracy of the recording pulse can be further improved. However, if the number of divisions is too large, it is not desirable because the time required for measuring the delay time increases and the interpolation processing becomes complicated, which increases the load on the control unit. Further, as the number of divisions increases, the delay time to be measured also decreases, so that a faster delay amount measuring unit is required. From the above points, it is preferable to set the number of divisions to an appropriate value.

Further, in this example, a method is adopted in which a division point is determined in advance for each predetermined number of steps, but this is not always necessary. Conversely, the slope of the graph may be obtained by detecting the number of steps at which the delay amount reaches a predetermined time.

In this case, in order to perform the broken line interpolation approximation, for example, a clock signal having a cycle smaller than half of the total delay time of the delay section is prepared, and an area substantially coincident with the cycle of the clock signal is prepared using this clock signal. Can be detected. By changing the selection signal value to find a selection signal value whose delay amount matches the clock cycle, at least 2
It is possible to detect an area in which one delay amount is a predetermined time. The slope of the graph is obtained as a one-step delay time by dividing the clock cycle by the difference between the selected signal values at both ends.

In order to increase the number of divisions, a clock signal having a cycle sufficiently shorter than the total delay time of the delay section may be used. This makes it possible to further improve the accuracy of the recording pulse even when there is variation in the delay section.

The advantage of this method is that the delay measurement can be performed by a clock signal having a fixed period and not so high as compared with the method of dividing by a fixed number of steps, thereby simplifying the configuration of the delay amount measuring section. What you can do. Specifically, it can be realized by the configuration described in FIG.

Further, in the above-described method, an example has been described in which the inclination of each of the plurality of divided regions is obtained and the polygonal line complementary approximation is performed. However, the approximation method is not limited to this. The main point of the present invention is to measure delay times individually for a plurality of divided regions and calculate a more accurate delay profile from the measurement results. Therefore, the delay profile calculated from the measurement result may be approximated by a curve or may be calculated by using a parameter of a predetermined characteristic function.

<Calibration Start Timing of Recording Compensation Table> Next, the calibration start timing of the recording compensation table will be described. Since the calibration of the recording compensation table is for correcting a predetermined edge position of a recording pulse, it cannot be performed while data is actually being recorded on the optical disk. Therefore, the calibration of the recording compensation table is performed except during the data recording operation.

Since the power supply voltage and temperature, etc., which cause the recording pulse position to fluctuate, especially the temperature inside the device, usually change every moment, the calibration of the recording compensation table is performed from the viewpoint of the accuracy of the recording pulse position. It is desirable to do it regularly. Therefore, the system control unit 110, which controls the recording and reproduction, may start the calibration of the recording compensation table for the format encoder / decoder 107, aiming at the interval between the data recording operations. The format encoder / decoder 107 may perform the processing independently.

FIG. 28 shows an example of the calibration timing of the above-described recording compensation table, that is, an example of the processing flow relating to the recording pulse correction. In the figure, the recording pulse correction process (step 101) indicates the entire process of calibrating the recording compensation table, and includes, for example, the process shown in FIG. The data recording process (step 102) is a normal data recording process,
That is, it shows a process of actually recording data on the optical disk. As shown in the figure, the recording pulse correction process is performed outside the period for performing the data recording process. Therefore, it is possible to perform the recording pulse correction processing without affecting the normal recording operation.

However, in a drive that supports the verify function, it is not always necessary to periodically calibrate the recording compensation table. Here, "verify function"
The function is to reproduce the recorded data once and confirm that the error rate of the data is equal to or less than a predetermined value at the time of recording the data. In other words, even if the edge position of the recording pulse is shifted, if it is confirmed by the verify operation that there is no uncorrectable error in the recorded data, it is not always necessary to calibrate the recording compensation table. Conversely, if the error rate of the data recorded by the verify operation is confirmed to be equal to or higher than a predetermined value, or if the frequency increases, it is determined that there is a possibility that the edge position of the recording pulse is shifted. At this time, the recording compensation table calibration may be started.

<Processing Related to Recording Pulse Correction> FIG. 29 shows an example of the flow of processing related to the above-described recording pulse correction. As shown in the figure, the data recording process (step 11)
After 1), the process proceeds to the verification process (step 112). In the verifying process, data recorded in the data recording process is reproduced, and an error state is detected (for example, a bit error rate is measured). After the verify processing, the verify error state is determined (step 1).
13) If the error state does not satisfy the predetermined criteria (“No Good”), the recording pulse correction processing (step 114) is performed, and if the error state satisfies the predetermined criteria (“Good”). ) Does not perform the recording pulse correction process. The error status is determined by
The determination may be made only based on the error state in the immediately preceding verification processing, or may be determined based on the error states in a plurality of verification processings executed in the past.

A temperature sensor and / or a voltage measuring unit may be separately provided to detect temperature fluctuations or power supply voltage fluctuations and to calibrate the recording compensation table only when a predetermined or more change is detected. good. In this case, if the data recording device is provided with a temperature sensor or a voltage measuring unit in advance, it is possible to more efficiently calibrate the recording compensation table without increasing the cost by using the temperature sensor or the voltage measuring unit.

<Determining Whether to Perform Recording Pulse Correction Processing> The processing for determining whether to perform the above-described recording pulse correction processing will be described with reference to FIGS. 30 and 31.

FIG. 30 shows an example of processing for determining whether or not to perform the recording pulse correction according to the detected temperature state. As shown in the figure, after a temperature detection process (step 121) for reading the current temperature of the device by a temperature sensor or the like,
It is determined whether the temperature has changed by a predetermined value or more (step 1).
22) If it is determined that the value has changed by a predetermined value or more ("YE
In step S "), a recording pulse correction process (step 123) is performed, and when it is determined that there is no temperature change equal to or more than a predetermined value (" N ").
O ”), the recording pulse correction processing is not performed. The temperature change may be determined by comparing the temperature at the time of the last recording pulse correction processing with the current temperature.
A plurality of temperature zones each having a predetermined temperature range may be provided in advance, and a determination may be made by comparing the temperature zone at the time of the last recording pulse correction processing with the current temperature zone.

FIG. 31 shows an example of a process for determining whether or not to perform the recording pulse correction according to the power supply voltage state.
As shown in the figure, a power supply voltage measurement process (step 131) for reading the current power supply voltage of the apparatus by means for measuring the power supply voltage is performed. Here, when there are a plurality of power supply voltages, the power supply voltage applied to the delay unit used for generating the recording pulse is measured. Thereafter, it is determined whether the power supply voltage has changed by a predetermined value or more (step 132).
If it is determined that the change is equal to or more than the predetermined value ("YES"), the recording pulse correction processing (step 133) is performed. If it is determined that there is no change equal to or more than the predetermined value ("NO"), the recording pulse correction processing is performed. Not performed. For power supply voltage changes,
The determination may be made by comparing the voltage value obtained when the recording pulse correction process was performed last and the current voltage value, or a plurality of voltage zones having a predetermined voltage range may be provided in advance, and the recording may be performed last. The determination may be made by comparing the voltage zone at the time of performing the pulse correction process with the current voltage zone.

[0209]

As described above, according to the configuration of the optical disk recording apparatus shown in the embodiment of the present invention, the laser emission waveform at the time of recording can be controlled using the recording pulse generated by the recording pulse generating means. . Further, the predetermined edge position of the recording pulse can be corrected by the recording pulse position correcting means. Further, it is possible to measure the delay amount of the delay means of the recording pulse generating means by the delay amount measuring means. That is, the predetermined edge position of the recording pulse generated by the recording pulse generating means can be corrected by the recording pulse position correcting means based on the result of the delay amount measurement by the delay amount measuring means. Therefore, even if the delay amount of the delay unit fluctuates due to fluctuations in the power supply voltage / temperature, etc., it becomes possible to appropriately maintain the predetermined edge position of the recording pulse,
It is possible to improve the quality of recording data as compared with a conventional optical disk recording device.

Further, according to the optical disk recording method shown in the embodiment of the present invention, the edge position of the recording pulse is corrected during a period when data is not recorded, and the edge position of the recording pulse is corrected during data recording. It can be performed in the state where it was done. Therefore, it is possible to maintain a predetermined edge position of a recording pulse properly without affecting a normal recording operation, and it is possible to improve the quality of recording data as compared with a conventional optical disk recording apparatus. Become.

Further, according to another optical disk recording method shown in the embodiment of the present invention, it can be determined whether or not to correct the edge position of a recording pulse based on the result of the verify operation. Therefore, the operation of correcting the edge position of the recording pulse is performed only when necessary, and the quality of the recording data can be improved without increasing the processing load of the edge position correction of the recording pulse.

Further, according to the optical disk recording method shown in the embodiment of the present invention, a selection signal value for which the delay amount of the delay means of the recording pulse generation means has a predetermined length is obtained, and the obtained selection signal value is converted to a predetermined value. By converting the time table relating to the edge position of the recording pulse into the delay setting value table of the recording pulse generating means, the edge position of the recording pulse can be corrected. Therefore, it is possible to appropriately maintain the predetermined edge position of the recording pulse with a simple configuration and procedure, and to improve the quality of the recording data and the reliability of the apparatus as compared with the conventional optical disc recording apparatus. .

Further, as described in detail in the embodiment of the present invention, according to the optical disk recording method of the present invention, it is possible to generate a delay clock in which a recording clock used for modulating recording data is adaptively delayed. Thus, the predetermined edge position of the recording pulse can be controlled by the timing of the delay clock. By generating a plurality of such delayed clock outputs, it is possible to adaptively control a plurality of edge positions in a recording pulse while using only one clock delay unit. Therefore, the circuit scale required for the delay means can be reduced, and an optical disk recording apparatus capable of controlling the edge of a recording pulse with high accuracy can be realized at low cost.

Furthermore, a pulse signal having a width of at least one recording clock cycle synchronized with the rising edge or the falling edge of the recording clock, and the start position thereof is variably controlled in a time unit of 周期 cycle of the recording clock. By generating a possible reference axis window signal, it becomes possible to control the predetermined edge position of the recording pulse by the timing of the delay clock and the reference axis window signal. By generating such reference axis window signals for the number of types of edges to be adaptively position-controlled of the recording pulse and using them in correspondence with the same number of delay clocks, the number of combinations of the delay clock and the reference axis window signal is obtained. Can be adaptively controlled. Therefore, it is possible to control the edge position of the recording pulse over a wide range while suppressing the circuit scale required for the delay means to a small scale. realizable.

Further, according to the optical disk recording method of the present invention, one optical disk is irradiated with a laser beam whose power is controlled at least in accordance with a recording pulse obtained by synthesizing a first pulse, a multi-pulse train, and a last pulse. Is formed, and at least the start edge position of the first pulse and the end edge position of the last pulse are adaptively controlled, and the start edge position of the first pulse and the end edge position of the last pulse are based on the relative relationship with the rising phase of the multi-pulse train. In this case, the start edge position of the first pulse and the end edge position of the last pulse can be appropriately represented.

Further, according to the optical disk recording apparatus of the present invention, it is possible to perform the recording compensation with higher accuracy by performing the variation correction of the elements constituting the delay means.

As described above, by using the optical disk recording method or the optical disk recording apparatus of the present invention, high-precision and wide-range control of the recording pulse can be easily realized, and from the viewpoint of increasing the recording density of the optical disk. Very useful.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an optical disk device according to the present invention.

FIG. 2 is a block diagram showing an example of an internal configuration of a laser driving unit according to the present invention.

FIG. 3 is a schematic diagram for explaining an example of the shape of a recording pulse, an emission waveform of a semiconductor laser, and a recording mark to be formed according to the present invention.

FIG. 4 is a block diagram illustrating a configuration example of a recording pulse generation unit according to the present invention, the configuration including a pulse delay unit;

FIG. 5 is a block diagram showing another example of the configuration of the recording pulse generation unit according to the present invention, the configuration having a clock delay unit;

FIG. 6 is a block diagram showing a configuration example of a clock delay unit according to the present invention, showing a configuration using an inverter element.

FIG. 7 is a schematic diagram for explaining a relationship between a selection signal value of a clock delay unit and an obtained delayed clock output.

FIG. 8 is a graph showing a relationship between a selection signal value of a clock delay unit and a delay time between input and output.

FIG. 9 is a schematic diagram showing an example of conversion from a time table of a recording compensation amount to a set value table in the present invention.

FIG. 10 is a block diagram illustrating a configuration of a delay amount measuring unit according to the present invention.

FIG. 11 is a block diagram showing a specific configuration example of a delay amount measuring unit.

12 is a signal timing chart for explaining a specific operation example until a recording pulse is generated from modulated data using the recording pulse generation unit having the internal configuration shown in FIG. 4;

13 is a signal timing chart for explaining a specific operation example until a recording pulse is generated from modulated data using the recording pulse generation unit having the internal configuration shown in FIG. 5;

FIG. 14 is a timing chart for explaining a delay amount measurement operation in a delay amount measurement unit having the internal configuration shown in FIG. 11;

FIG. 15 is a flowchart showing a specific processing flow of a method of calibrating a recording compensation table in the optical disc recording apparatus according to the present invention.

FIG. 16 is a block diagram showing another configuration example of the clock delay unit according to the present invention, showing a configuration using a buffer element.

FIG. 17 is a block diagram showing still another configuration example of the clock delay unit according to the present invention, showing a configuration using a voltage-controlled delay element.

FIG. 18 is a schematic diagram for explaining a method of generating a timing signal for determining a first pulse rising position SFP according to the present invention.

FIG. 19 is a block diagram showing another configuration example of the recording pulse generator in the present invention.

FIG. 20 is a block diagram showing a configuration example of a first pulse delay unit according to the present invention, showing a configuration using an inverter element.

FIG. 21 is a block diagram showing another configuration example of the first pulse delay unit according to the present invention, showing a configuration using a buffer element.

FIG. 22 is a block diagram (a) showing still another configuration example of the first pulse delay unit according to the present invention, using a voltage-controlled delay element, and a specific configuration example of the voltage-controlled delay element. FIG.

FIG. 23 is a block diagram showing an example of a configuration of a pulse timing generator according to the present invention.

FIG. 24 is a diagram illustrating delay characteristics of a delay unit (delay circuit).

25A illustrates an example in which a delay element group is divided into two regions in a delay unit including a plurality of delay elements, and FIG. 25A illustrates a two-point broken line when approximating a selection signal value. FIG.

FIG. 26 is a diagram showing an example of conversion of a recording compensation amount from a time table to a set value table in consideration of variation correction.

FIG. 27A illustrates an example in which a delay element group is divided into eight regions in a delay unit including a plurality of stages of delay elements, and an eight-point broken line when approximating a selection signal value is described. FIG.

FIG. 28 is a view for explaining the calibration timing of the recording compensation table.

FIG. 29 is a flowchart showing the flow of processing related to recording pulse correction.

FIG. 30 is a flowchart illustrating a process of determining whether or not recording pulse correction is to be performed according to a temperature state.

FIG. 31 is a flowchart showing a process of determining whether or not to execute a recording pulse correction according to a power supply voltage state.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Optical disk 102 Disk motor 103 Optical head 104 Amplifier 105 Servo control unit 106 Reproduction signal processing unit 107 Format encoder / decoder 108 Laser drive unit 109 Host interface 110 System control unit 111 Recording pulse generation unit 112 Recording pulse position correction unit 113 Delay amount measurement Unit 401 Pulse timing generation unit 402 First pulse delay unit 403 Multi-pulse delay unit 404 Last pulse delay unit 405 Cooling pulse delay unit 501 Pulse timing generation unit 502 Clock delay unit 601 Inverter element 1601 Buffer element 1701 Voltage control type delay element 1901 Pulse timing Generator

Claims (38)

[Claims] 1. An information recording apparatus for recording data on an optical disk by irradiating a laser beam modulated to at least two types of power values modulated according to data to be recorded, comprising: a delay unit; Recording pulse generation means for modulating data to be generated to generate a pulse signal, correcting the pulse signal by delaying a predetermined edge position of the pulse signal by the delay means, and outputting the corrected recording pulse; and Laser driving means for driving a laser while switching a power value by a signal; delay amount measuring means for measuring a delay amount in the delay means; and the edge position of a recording pulse based on a delay amount measurement result by the delay amount measuring means. An information recording apparatus, comprising: a recording pulse position correcting unit that corrects an error. 2. The recording pulse generation device according to claim 1, wherein the laser driving unit includes a plurality of current sources, and a plurality of switches for independently turning on / off the supply of the output current from each current source to the laser. 2. The information recording apparatus according to claim 1, wherein the means outputs a plurality of recording pulses to the laser driving means, and controls on / off of the plurality of switches by the plurality of recording pulses. 3. The recording pulse generation unit modulates data to be recorded and generates a reference pulse signal. The recording pulse generation unit receives the reference pulse signal as an input, and externally changes a delay amount. 2. The information recording apparatus according to claim 1, further comprising a delay amount variable type delay unit that outputs a possible delay pulse. 4. The recording pulse generating means, wherein the delay means comprises: a plurality of inverter elements each having an input / output connected in series; and a selection means for selecting an output of each of the inverter elements. 2. The information recording apparatus according to claim 1, wherein the selection of the selection unit is controlled by a recording pulse position correction unit. 5. The recording pulse generating means according to claim 1, wherein:
A plurality of buffer elements each having an input / output connected in series; and a selection unit for selecting an output of each of the buffer elements, wherein selection of the selection unit is controlled by the recording pulse position correction unit. The information recording apparatus according to claim 1, wherein: 6. A delay means of said recording pulse generating means comprises a voltage control type delay element, and a control voltage of said voltage control type delay element is controlled by said recording pulse position correction means to thereby determine a predetermined edge position of a recording pulse. 2. The information recording apparatus according to claim 1, wherein the information is corrected. 7. The information according to claim 1, wherein the delay amount measuring unit measures a delay amount between input and output of the delay unit of the recording pulse generating unit using a clock signal for delay measurement. Recording device. 8. The delay amount measuring unit measures a delay difference between two outputs having different delay amounts of the delay unit of the recording pulse generating unit using a clock signal for delay measurement. 2. The information recording device according to 1. 9. The recording pulse position correcting means uses the delay amount measurement result by the delay amount measuring means to set a delay such that the delay between input and output of the delay means of the recording pulse generating means is about one channel bit time. 2. The information recording apparatus according to claim 1, wherein a value is obtained, and a predetermined edge position of the recording pulse is corrected based on the delay setting value. 10. The recording pulse position correcting means uses the delay amount measurement result by the delay amount measuring means to calculate a difference in delay amount between two outputs having different delay amounts of the delay means by approximately one channel bit time. Find the delay setting value that gives
2. The information recording apparatus according to claim 1, wherein a predetermined edge position of the recording pulse is corrected based on the delay setting value. 11. The recording pulse position correcting unit corrects an edge position of a recording pulse generated by the recording pulse generating unit to a position different depending on a bit length of a recording mark, a preceding space length, or a succeeding space length. The information recording device according to claim 1, wherein 12. An information recording method for recording data on an optical disk while controlling laser power using a recording pulse modulated according to recording data, wherein the edge position of the recording pulse is determined during a period in which data is not recorded. And a recording step of recording data using the recording pulse whose edge position has been corrected. 13. An information recording method for recording data on an optical disk while controlling laser power using a recording pulse modulated in accordance with recording data, comprising: a recording step of recording data; A verifying step of performing a verifying operation of: a determining step of determining whether or not to correct an edge position of a recording pulse based on an error state of recorded data with reference to the verifying result; A correction step of correcting the edge position of the recording pulse only when it is determined that the edge position of the recording pulse is to be corrected. 14. The method according to claim 1, wherein in the determining step, it is determined whether or not the edge position of the recording pulse is corrected by referring to an error state of the reproduction data in a plurality of verification results executed in the past. The information recording method according to claim 12 or 13. 15. The method according to claim 15, wherein the correcting step measures a delay amount of a delay unit of the recording pulse generating unit, and corrects the predetermined edge position of the recording pulse based on a measurement result of the delay amount. 13. The information recording method according to 12 or 13. 16. The correction step includes: setting a selection signal value for determining a delay amount of a delay unit of a recording pulse generation unit; reading a measurement result of the delay amount with respect to the set selection signal value; Using the measurement result of the delay amount to determine a selection signal value at which the delay amount becomes one cycle time Tw of the clock used by the recording pulse generating means; and determining a selection signal value based on the determined selection signal value. 14. The information recording method according to claim 12, further comprising: converting a time table relating to an edge position of the recording pulse into a setting value table of a selection signal value. 17. The information recording method according to claim 16, wherein the time Tw is a time corresponding to one channel bit of the recording data. 18. The information recording method according to claim 16, wherein the time table includes time information on an edge position of the recording pulse where the position is variable. 19. The information recording method according to claim 16, wherein the time table has individual time information for each mark length of data to be recorded. 20. The time table according to claim 16, wherein the time table has individual time information for each combination of a mark length of data to be recorded and a preceding space length.
Information recording method described in. 21. The time table according to claim 16, wherein the time table has individual time information for each combination of a mark length of data to be recorded and a space length immediately after the mark length.
Information recording method described in. 22. In the pulse correction step, in the recording pulse generating means comprising a plurality of delay means, a delay amount is measured for each delay means group including a predetermined number of delay means, and the measured delay amount is determined for each delay means group. 2. An apparatus according to claim 1, wherein an output of said delay means for determining an edge position of a predetermined recording pulse is controlled based on a delay amount.
14. The information recording method according to claim 2 or claim 13. 23. In the pulse correction step, the recording pulse generating means comprising a plurality of stages of delay means measures a delay amount for each delay means group including a predetermined number of delay means, and performs the measurement for each of the measured delay means groups. A delay profile of the entire delay unit is calculated based on the delay amount, and an output of the delay unit for determining an edge position of a given recording pulse is controlled based on the calculated delay profile. The information recording method according to claim 22, wherein: 24. The information recording method according to claim 23, wherein the calculated delay profile is a function represented by the same number of polygonal lines as the number of the delay means groups. 25. The pulse correcting step, wherein the delay time of the delay means substantially matches one cycle of the clock signal using a clock signal having a cycle equal to or less than half the total delay time of the delay means in the recording pulse generating means. 14. The information recording method according to claim 12, wherein an area to be recorded is detected, an output of the delay unit is controlled based on the detection result, and an edge position of a recording pulse given in advance is determined. . 26. Each mark is formed by irradiating a laser beam whose power is controlled in accordance with a recording pulse composed of a plurality of pulse trains to an optical disc, and a predetermined edge position of the recording pulse is adaptively controlled to thereby form data. An information recording method for performing high-precision recording, wherein a Tw / n period (Tw is one channel bit period of recording data, n is a natural number) used for modulation of recording data is adaptively controlled by a delay amount. An information recording method wherein a delay clock is generated by delaying the recording pulse, and a predetermined edge position of the recording pulse is determined based on the timing of the delay clock. 27. Each mark is formed by irradiating a laser beam whose power is controlled in accordance with a recording pulse composed of a plurality of pulse trains to an optical disk, and a predetermined edge position of the recording pulse is adaptively controlled so that the optical disk is formed. An information recording method for performing high-precision recording of data, wherein a recording clock of Tw / n period (Tw is one channel bit period of recording data, n is a natural number) used for modulation of recording data is used for delay amount. A delay clock that is delayed while being adaptively controlled, and a pulse-like signal having at least a Tw / n time width synchronized with a rising edge or a falling edge of the recording clock, and a start position variable in a time unit of Tw / 2n. A controllable reference axis window signal is generated, and the recording clock is generated based on the delay clock and the timing of the reference axis window signal. Information recording method characterized by determining a predetermined edge position of the scan. 28. When a predetermined edge position of a recording pulse needs to be adaptively controlled in a time range of at least d × Tw / 2n (d and n are natural numbers and Tw is one channel bit period), a reference axis 28. The information recording method according to claim 27, wherein the window signal is controlled to (d + 1) types of timings in Tw / 2n time units. 29. An optical disc is irradiated with a laser beam whose power is controlled in accordance with a recording pulse formed by synthesizing at least one of a first pulse, a multi-pulse train having a waveform having one channel bit period Tw, and a last pulse. Forming one mark, and performing data recording by adaptively controlling at least one of the start edge position of the first pulse and the end edge position of the last pulse. The start edge position of the first pulse and the last pulse Wherein each of the end edge positions of the multi-pulse train is defined based on a relative relationship with a rising phase of the multi-pulse train, wherein: a) a rising phase of the multi-pulse train or a rising phase of the multi-pulse train; Small for phases approximately 180 degrees delayed At least a first pulse reference clock of Tw / n cycle controlled by a relative time within a range of ± Tw / 4n (n is a natural number), and a rising phase of the multi-pulse train or a phase delayed by about 180 degrees from the rising phase. At least one cycle of the first pulse reference clock synchronized with a rising phase reference clock having a cycle Tw controlled at least in a time range of ± Tw / 4n and a rising phase of the multi-pulse train or a phase delayed by about 180 degrees from the rising phase; A first pulse reference axis window signal whose start position is variably controllable in a time unit of Tw / 2n with a pulse-like signal having a width of a minute, and a rising phase of the multi-pulse train or a phase delayed by about 180 degrees from the rising phase. Synchronized with at least the last pulse reference clock 1 A pulse-like signal having a width of a period, a last pulse reference axis window signal whose start position can be variably controlled in a time unit of Tw / 2n; b) the first pulse reference clock and the first pulse reference axis window; An information recording method, wherein a start edge position of the first pulse is determined by a signal timing, and an end edge position of the last pulse is determined by a timing of the last pulse reference clock and the last pulse reference axis window signal. 30. An information recording apparatus for recording data by irradiating an optical disc with laser light whose power value is switched by a recording pulse obtained by modulating data to be recorded, comprising: a Tw / n cycle (where Tw is a recording A recording clock generating means for generating a recording clock of one channel bit period of data, where n is a natural number, and m having different delay amounts by delaying the recording clock.
A clock delay unit for generating a type (m is a natural number) of delayed clocks; and a pulse for generating m types of pulse reference signals having a width of at least one cycle of the recording clock using the recording data and the recording clock. Reference signal generation means; pulse timing signal generation means for generating m kinds of pulse timing signals by associating any one of the m kinds of the delayed clocks with any one of the m kinds of the pulse reference signals; A delay amount control means for controlling a delay amount of the type of the delay clock; and a recording pulse synthesizing means for synthesizing a recording pulse using the m kinds of the pulse timing signals, wherein m predetermined edges in the recording pulse are provided. An information recording apparatus characterized in that the position is variable. 31. An information recording apparatus for recording data by irradiating an optical disc with laser light whose power value is switched by a recording pulse obtained by modulating data to be recorded, comprising: a Tw / n period (where Tw is a recording A recording clock generating means for generating a recording clock of one channel bit period of data, where n is a natural number, and m having different delay amounts by delaying the recording clock.
Clock delay means for generating a type (m is a natural number) of delayed clocks; a pulse signal having a width of at least one cycle of the recording clock using the recording data and the recording clock; Pulse reference signal generating means for generating m kinds of pulse reference signals variable in time units of / 2n; one of the m kinds of delay clocks;
Pulse timing signal generating means for generating m kinds of pulse timing signals in correspondence with any one of the above-mentioned kinds of pulse reference signals; delay amounts of m kinds of the delayed clocks and timings of the m kinds of pulse reference signals And a recording pulse synthesizing means for synthesizing recording pulses using the m types of pulse timing signals, wherein m predetermined edge positions in the recording pulses are made variable. Information recording device. 32. The clock delay means comprises: a plurality of inverter elements each having an input / output connected in series; and a selection means for selecting an output of each of the inverter elements. 32. The information recording apparatus according to claim 30, wherein a delay amount of a delay clock is controlled by controlling output selection of the selection unit. 33. The clock delay means includes a plurality of buffer elements each having an input and an output connected in series, and a selection means for selecting an output of each of the buffer elements. 32. The information recording apparatus according to claim 30, wherein a delay amount of a delay clock is controlled by controlling output selection of the selection unit. 34. The clock delay means comprises a voltage control type delay element, and a control voltage of the voltage control type delay element is controlled by the delay amount control means to control a delay amount of a delay clock. 32. The information recording device according to claim 30, wherein: 35. The pulse timing signal generating means comprises m D flip-flops, m kinds of delayed clocks are respectively connected to clock input terminals of the m D flip-flops, and m kinds of pulse reference signals are provided. Respectively connected to the D input terminals of the D flip-flop,
32. The information recording apparatus according to claim 30, wherein m kinds of pulse timing signals are extracted from Q output terminals of the m D flip-flops. 36. A delay amount measuring means for measuring a delay amount of said clock delay means, wherein said delay amount control means determines m kinds of delay clocks based on a delay amount measurement result by said delay amount measuring means. 32. The information recording apparatus according to claim 30, wherein a delay amount is controlled. 37. An information recording method for recording data on an optical disk while controlling laser power using a recording pulse modulated according to recording data, comprising: detecting a temperature of a device for recording data on the optical disk; Determining the detected temperature change; correcting the edge position of the recording pulse only when it is determined that the temperature change is equal to or more than a predetermined value based on the determination of the temperature change; Recording data by using the information recording method. 38. An information recording method for recording data on an optical disk while controlling laser power using a recording pulse modulated according to recording data, comprising: measuring a power supply voltage of a device for recording data on the optical disk. Determining a change in the measured power supply voltage; correcting the edge position of the recording pulse only when it is determined that the power supply voltage change is equal to or greater than a predetermined value based on the determination of the change in the power supply voltage; Recording data using a position-corrected recording pulse.