JP2007280498A - Laser power control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laser power controller which can control the peaks with sufficient precision regardless of the duty ratio set in the multi-pulse section. <P>SOLUTION: In the test light emitting period right before the data recording area, this laser power controller generates multi-pulses for test with the predetermined duty ratio in the same cycle as the multi-pulse train of the optical recording pulses irrespective of its duty ratio, finds the difference between the detected optical signals converted into electric signals by receiving the test multi-pulses and the reference value corresponding to the target power of the optical recording pulses, and feedback controls to suppress the difference to obtain the current flowing in the semiconductor laser for the optical recording pulses having the target power. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a recording light power control method and a light power control apparatus for a semiconductor laser that emits light to record a mark area corresponding to a data signal on an optical disk.

  When recording information on an optical disk at a high density, in order to form a distortion-free recording mark, the laser beam applied to the recording film is converted into an optical pulse whose intensity is modulated by peak power and bottom power, thereby heating the recording film. A method of forming a mark by repeating cooling is generally performed.

  In order to maintain the reproduction signal quality of a disc that has been overwritten many times, it is necessary to control the peak power of the optical pulse to the correct power. On the other hand, regarding the control of each power value of the optical pulse, the modulation frequency of the optical pulse is 100 MHz or more at a quadruple speed of DVD, for example, while the band of the light receiving element for monitoring each power value is generally about 50 MHz. Therefore, the peak power cannot be detected directly.

  To solve this problem, the conventional optical disk laser control device detects the average power value of the multi-pulse part of the optical pulse, estimates the peak power from this average power value, and the estimated peak power is equal to the target value. There has been a method of controlling (see, for example, Patent Document 1).

  According to the conventional method, in a test light emission section before the data recording area, light emission with a constant bottom power and a multi-pulse whose intensity is modulated with the same duty ratio (d) and bottom power and peak power as in normal data recording. A light pulse including light emission is generated. This light pulse is received by the light receiving element and converted into a current, and converted into a voltage by a current-voltage conversion circuit to obtain a received light waveform. From this received light waveform, the bottom DC value (Bdc) and the average value (M) of the multi-pulse part are obtained. Using the obtained bottom DC value (Bdc), the average value (M) of the multi-pulse part, and the duty ratio (d) of the multi-pulse part by the arithmetic processor, the peak value (P) of the multi-pulse part which is an unknown number Is obtained from the following equation.

M = P * d + Bdc * (1-d)
Than,
P = {M−Bdc × (1−d)} / d (Formula 1)
By such a method, it is possible to control the peak power of the optical pulse to a desired value by estimating the peak power value and controlling the drive current to the semiconductor laser so as to suppress the error from the target value. .

Further, the duty ratio (d) of the optical pulse has a different pulse width value so that optimum recording characteristics can be obtained for each type of optical disk (including manufacturer and recording double speed). In order to cope with this, a recording pulse is generated by inputting and outputting a reference clock to a circuit in which a plurality of delay elements are connected in multiple stages, and by selectively outputting it, the width is changed back and forth with a 50% duty ratio as a reference. There has been a method of changing (see, for example, Patent Document 2).
JP 2002-203320 A JP 2000-276736 A

  However, the conventional configuration has a problem. In the case of high-density recording using a blue laser as a light source or in the case of a multi-layer disc, higher accuracy than peak power is required. On the other hand, in the generation of the recording pulse, there is an error with respect to the setting of the delay element and a deviation due to temperature fluctuation, and there is an error of the pulse width. The influence becomes large, and an error for setting the duty ratio increases in the multi-pulse part. While the duty ratio of the optical pulse is deviated from the set duty ratio d, the arithmetic processor calculates the peak power while maintaining the set duty ratio d, which causes a problem that an error occurs in the detected peak power. For example, when the channel clock is 132 MHz, the multipulse period Tw is 7.58 ns. The pulse width with a duty ratio of 40% is 3.03 ns. When the delay element is used to generate this duty ratio, the inventors have conducted experiments in which a deviation of about 0.3 ns in total occurs due to a deviation from the setting of the delay element or a temperature variation. In this case, the error of the duty ratio with respect to the setting is about 10%. In the detection of peak power, the average value (M) is divided by the duty ratio (d) based on the above-described equation 1, so that the error in the duty ratio becomes the peak power error as it is, for example, the tolerance of the recording power such as a two-layer disc. When the (power margin) is small, the quality of the reproduced signal after recording is deteriorated.

  The present invention solves the above-described problems, and an object of the present invention is to provide a laser power control method capable of accurately controlling peak power by avoiding the influence of a delay element.

  In order to solve the above-described problem, in the present invention, hardware that can set the duty ratio of the multi-pulse generated in the test light emission section before the data recording area separately from that at the time of normal data recording is added. The optical pulse can be generated with a duty ratio that is not affected by this, and the optical pulse is received by the light receiving element, the average value of the multi-pulse part is obtained, and the peak power is estimated. In this way, the control accuracy is improved by improving the detection accuracy of the peak power.

  The invention according to claim 1 is a method for controlling each power value of the first optical pulse including at least a multi-pulse for forming a recording mark in a data recording area of a laser power optical disc, In the test light emission section provided immediately before, a second optical pulse including a multi-pulse having the same period and a different duty ratio as the multi-pulse of the first optical pulse is generated, and the second light is generated. An error is detected between the light detection signal obtained by receiving the pulse and converted into an electric signal and a reference value corresponding to the target power value of the first optical pulse, and the current value flowing through the semiconductor laser is controlled so as to suppress the error. This is a laser power control method.

  According to a third aspect of the present invention, there is provided an apparatus for controlling each power value of a first optical pulse including at least a multi-pulse for forming a recording mark in a data recording area of an optical disc, immediately before the data recording area. Means for generating a second light pulse including a multi-pulse having the same period and a different duty ratio as the multi-pulse of the first light pulse in the provided test light emission section; Means for generating a light detection signal that receives a pulse and converts it into an electrical signal, and obtaining an error between the light detection signal and a reference value corresponding to a target power value of the first light pulse so as to suppress the error. And a means for controlling the value of the current flowing in the semiconductor laser.

  According to the laser power control method of the present invention, regardless of the set duty ratio of the multi-pulse section, the multi-pulse duty ratio generated in the test light emission section before the data recording area is generated without being affected by the delay element. Since this optical pulse is received by the light receiving element so as to obtain the average value of the multi-pulse part and the peak power is estimated, the control accuracy is improved by improving the detection accuracy of the peak power. be able to.

Embodiments of a laser power control method according to the present invention will be described below in detail with reference to the accompanying drawings.
<1. Configuration of optical disc device>
FIG. 1 is a block diagram showing the configuration of an optical disc apparatus according to the present invention. In FIG. 1, a disk motor 102 rotates an optical disk 101 at a predetermined rotational speed. Although not shown, the optical head 103 incorporates a semiconductor laser, an optical system, a photodetector, and the like. Is recorded and reproduced. Reflected light from the recording surface is collected by an optical system in the optical head 103, converted to a current by a photodetector, further converted and amplified by an amplifier 104, and output as a reproduction signal.

  The servo control unit 105 controls the rotation of the disk motor 102, the transfer control for moving the optical head 103 in the radial direction of the optical disk 101, the focus control for focusing the light spot on the recording surface, and tracks the light spot at the center of the track. Tracking control to make it happen. For focus control and tracking control, a focus error signal (electric signal indicating a deviation of a light spot from the recording surface in a direction substantially perpendicular to the recording surface of the optical disc 101) among the reproduction signal output from the amplifier 104 and A tracking error signal (an electric signal indicating a deviation of a light spot from a predetermined track on the recording surface of the optical disc 101) is used.

  The reproduction signal processing unit 106 extracts a signal component corresponding to the data recorded on the optical disc 101 from the reproduction signal that is the output of the amplifier 104, binarizes the extracted signal, and incorporates it from the binarized data and the reference clock. The read clock and the read data synchronized with the read clock are generated by a PLL (abbreviation of Phase Locked Loop).

  The laser control unit 108 generates a laser drive signal so that the semiconductor laser built in the optical head 103 emits light with a reproducing power when reproducing addresses and data and with a recording power when recording.

  The format encoder / decoder 107 reproduces the address information recorded on the optical disc 101 from the read clock and read data output from the reproduction signal processing unit 106, and synchronizes with the sector of the optical disc 101 based on the reproduced address position. It has a role of generating and supplying each timing signal necessary for recording and reproduction at the timing. For example, a timing signal such as a read gate necessary for binarization / PLL processing of an address or data is output to the reproduction signal processing unit 106, or light emission of recording power is permitted to the laser driving unit 108 during recording. By outputting a timing signal such as a write gate, data can be recorded and reproduced at the correct timing.

  Also, the format encoder / decoder 107 adds redundant data such as an error correction code to user data supplied from the outside of the apparatus through the host interface 109, and further records a bit sequence modulated according to a predetermined format. The pulse generator 111 processes the signal into a predetermined recording pulse signal and outputs it to the laser controller 108. At the time of reproduction, the address information and data recorded on the optical disc 101 are demodulated and error-corrected from the read clock and read data output from the reproduction signal processing unit 106, and the corrected data is transmitted to the outside of the apparatus through the host interface 109. Send to.

  The format encoder / decoder 107 includes a recording pulse position correction unit 112 and a delay amount measurement unit 113. The recording pulse position correction unit 112 performs setting related to the position of the recording pulse signal generated by the recording pulse generation unit 111 and makes a specific edge position of the recording pulse signal variable. The delay amount measuring unit 113 has a role of measuring the pulse delay amount by the recording pulse generating unit 111.

The system control unit 110 interprets commands (commands) supplied from the outside of the entire apparatus, that is, the host interface 109, so that data is recorded / reproduced with respect to a predetermined sector of the optical disc 101. In addition, the operation of each unit such as the servo control unit 105, the reproduction signal processing unit 106, the format encoder / decoder 107, the laser driving unit 108, and the host interface 109 is controlled.
<2. Configuration of Laser Power Control Device>
FIG. 2 is a diagram illustrating the configuration of the semiconductor laser control unit.

  The laser drive unit 40 includes pulse current sources 41 to 44, and generates optical pulses by supplying a multilevel pulse current to the semiconductor laser 1. The pulse current source 44 outputs a peak current value (Ip) according to the input current value Ip and the logic of the recording pulse 206c. Similarly, the pulse current source 43 outputs a bias current value (Ie) according to the input current value Ie and the logic of the recording pulse 206b. The pulse current source 42 outputs a cooling current value (Ic) according to the input current value Ic and the logic of the recording pulse 206a. The pulse current source 41 outputs a bottom current value (Ib) according to the input current value Ib and the logic of the recording gate 206d. Here, since the logic of the recording gate 206d is always H level during recording, the bottom current Ib is always output during recording.

  Here, the operation of the laser driving unit 40 will be described in more detail with reference to FIG.

  FIG. 3 is a diagram schematically illustrating an example of generation timing of the recording pulses 206a, 206b, and 206c by the recording pulse generation unit 111, an example of a light emission waveform of the semiconductor laser 1, and a recording mark that is formed on the optical disc in association therewith. is there.

  In FIG. 3, time flows from the left to the right, and the modulation data 208 is an input to the recording pulse generator 111. In the figure, a waveform corresponding to a 6T mark is shown. The pulse reference clock 301 is a clock whose period is a time length of one channel bit, and is used as a reference for recording pulse generation processing in the recording pulse generation unit 111. Each recording pulse 206a, 206b, 206c is generated at the timing shown in FIG. 3 according to the timing of the modulation data 208 and the pulse reference clock 301. The light emission waveform of the semiconductor laser 1 has a shape as shown in the figure according to the timing of each recording pulse 206a, 206b, 206c.

  The light emission waveform for recording one mark (6T mark in this example) is divided into a plurality of pulse parts, and the first pulse part, multi-pulse part, last pulse part, It is called a cooling pulse part. In a recording system that changes the recording film by heat, such as a phase change optical disk, it is known that a method of forming one recording mark by a plurality of pulse portions in time series as in this example is effective. ing. For example, the multi-pulse unit intermittently applies high power and low power to prevent the mark shape from becoming a teardrop shape when a relatively long mark is recorded as described in the prior art. The cooling pulse portion plays a role of blocking the influence of heat when recording the next mark.

  On the other hand, the vertical direction, that is, the amplitude of the light emission waveform in FIG. 3 indicates the light emission power of the laser, and the power value is classified into four types of bottom power, cooling power, bias power, and peak power in ascending order. In the case of phase change recording, the phase of the recording film is crystallized by irradiating the power corresponding to the bias power, and the phase of the recording film is amorphized by irradiating the power corresponding to the peak power. Basically, the portion made amorphous by peak power irradiation is called a recording mark. Also, the bottom power and cooling power temporarily reduce the heat applied to the recording film.

  Next, the relationship between these four types of power and the operation of the laser driving unit 40 described with reference to FIG. 2 will be described. First, the bottom power is realized by setting all the logics of the recording pulses 206a, 206b, and 206c to the Lo level. At this time, only the output current Ib of the current source 41 is supplied to the semiconductor laser 201, and the semiconductor laser 1 emits light with bottom power (Pb).

  The cooling power can be realized by setting the recording pulse 206a to H (High) level and the recording pulses 206b and 206c to L level. At this time, the sum (Ic + Ib) of the output current of the current source 42 and the output current of the current source 41 is supplied to the semiconductor laser 201, and the semiconductor laser 1 emits light with the cooling power (Pc).

  The bias power can be realized by setting the recording pulses 206a and 206b to the H level and the recording pulse 206c to the L level. At this time, the sum (Ie + Ic + Ib) of the output currents of the current sources 43, 42, 41 is supplied to the semiconductor laser 1, and the semiconductor laser 1 emits light with bias power (Pe).

  The peak power can be realized by setting all the recording pulses 206a, 206b, and 206c to the H level. At this time, the sum of all output currents of the four current sources 44, 43, 42, 41 is supplied to the semiconductor laser 1 and emits light with peak power (Pp).

  The first pulse rising position (hereinafter referred to as “SFP”), the first pulse falling position (hereinafter referred to as “EFP”), the multi-pulse width (hereinafter referred to as “MPW”), and the last pulse rising position (hereinafter referred to as “SLP”). The last pulse falling position (hereinafter referred to as “ELP”) and the cooling pulse rising position (hereinafter referred to as “ECP”) are independently changed according to the timing of recording pulses 206a, 206b, and 206c described later. be able to.

  As for the duty ratio of each pulse of the multi-pulse section (hereinafter referred to as “multi-pulse”), the rising timing of the multi-pulse is synchronized with the rising timing of the pulse reference clock 301, and the falling position of the multi-pulse is set to the multi-pulse. It can be made variable by the width setting value MPW. For example, when the multi-pulse width setting value MPW = 0, the multi-pulse duty ratio is 50%, that is, the peak power emission time and the bottom power emission time are 1: 1 in the laser emission waveform of FIG. When the set value is determined, the MPW is set within a predetermined integer range centered on 0, whereby the width can be changed back and forth with respect to the duty ratio of 50%.

In this way, changing the position or duty ratio of the recording pulse is generally called “recording compensation”, and the amount of change in the position or duty ratio of the recording pulse is called “recording compensation amount”. Attempts have already been made to increase the recording density by reducing the influence of thermal interference between the recording marks by this recording compensation.
<3. Control method of each power value of optical pulse>
Next, a method for controlling each power (bottom power, cooling power, bias power, peak power) of the optical pulse to a desired power value will be described using the configuration diagram of the laser control device in FIG. 2 and the waveform in FIG. . Here, an example is shown in which an ALPC (Automatic Laser Power Control) area provided at the head of each sector on the recording track is used as a test light emission section.

  As shown in FIG. 4, in the ALPC region, a test light emission pattern including a constant bottom light emission, a constant cooling light emission, a constant bias power emission, and a multi-pulse light emission is generated. The current values (Ib, Ic, Ie, Ip) of the pulse current sources 41 to 44 in the test light emission pattern are set as follows in the arithmetic processor 25 so that each power of the optical pulse becomes a desired value. The The peak power setting value (Pref), bias power setting value (Eref), cooling setting value (Cref) bottom power setting value (Bref), which are control target values, are recorded in advance in the arithmetic processor (DSP) 25. Assuming that the current conversion coefficient is K and the threshold current of the laser is Ith, the initial values Ib_0, Ic_0, Ie_0, and Ip_0 of Ib, Ic, Ie, and Ip are current values corresponding to the difference between the power values. It is set like this.

Ib = Ib_0 = Ith + K (Bref)
Ic = Ic_0 = K (Cref−Bref)
Ie = Ie_0 = K (Eref-Bref)
Ip = Ip_0 = K (Pref−Eref)
Further, the recording gate 206d, the recording pulse 206a, the recording pulse 206b, and the recording pulse 206c are input by the recording pulse generating means with waveforms as shown in FIGS. 3 (g), (h), (i), and (j), respectively. It is realized by. Here, even when the duty ratio of the multi-pulse part in the actual recording area is as thin as 25%, the recording pulse 206a, the recording pulse 206b, A recording pulse 206c is input.

  The test light emission pattern of the light pulse generated by the method as described above is received by the photodetector 2 that monitors the light emission level, converted into a photocurrent, and converted into a voltage waveform by the current-voltage converter 3.

  Next, the voltage-converted received light waveform is input to the sample hold circuit (SH1, SH2, SH3). The sample hold circuit 11 (SH1) samples and holds the bottom DC value (Pb) of the test light emission section at the timing of the sampling pulse S1 determined according to the light emission waveform as shown in FIG. The sample hold circuit 12 (SH2) samples and holds the cooling DC value (Pc) in the test light emission period at the timing of the sampling pulse S2. The sample hold circuit 13 (SH3) samples and holds the bias value (Pe) of the test light emission period at the timing of the sampling pulse S3.

  In addition, the voltage-converted received light waveform is input to a low-pass filter (LPF) 15. The low-pass filter 15 is set to a cut-off frequency characteristic that can be smoothed in order to detect the average value of the multi-pulse part pulsed between the peak power and the bottom power.

  Next, the output of the low-pass filter (LPF) 15 is input to the sample hold circuit 14 (SH4). The sample hold circuit SH4 samples and holds the multi-pulse average value (Pa) in the test light emission section at the timing of the sampling pulse S4 determined according to the light emission waveform.

Next, the outputs of the sample hold circuits SH1, SH2, SH3, and SH4 are input to the AD converters AD1, AD2, AD3, and AD4, and converted into digital data. The converted digital data is sent to an arithmetic processor (DSP) 25 for bottom DC value data (Pb), cooling DC value data (Pc), bias value DC value data (Pe), and multipulse average value data (Pa). Next, the operation of the arithmetic processor (DSP) 25 will be described. In the test light emission period, the detected four power values are compared with the reference value corresponding to the target power value of the optical pulse, and the peak current value Ip, the bias current value Ie, the cooling current value Ic, The comparison calculation is performed so that the bottom current value Ib becomes the target power value.

  In order to obtain the peak value, it is necessary to convert from the average value (Pa) of the acquired multipulses. When the peak value (Pp) is an unknown number, the unknown number Pp is obtained by calculating the following equation.

From Pa = Pp × d + Pb × (1-d),
Pp = {Pa−Pb · (1−d)} / d ···· (Expression 2)
Then, the obtained peak value (Pp), bias value (Pe), cooling value (Pc), and bottom value (Pb) are compared with each power target value (Pref), (Eref), (Cref), (Bref), The difference values ΔP, ΔE, ΔC, ΔB are calculated.

ΔB = B-Bref
ΔC = Pc-Cref
ΔE = Pe-Eref
ΔP = Pp-Pref
Using the difference values ΔP, ΔE, ΔC, ΔB obtained by the above calculation, the current conversion coefficient K, and the initial values (Ip_0, Ie_0, Ic_0, Ib_0) of each pulse current source, the following calculation is performed. Then, the difference values ΔP, ΔE, ΔC, ΔB can be controlled to converge to a predetermined value, for example, zero.

Ib = K × ΔB + Ib — 0
Ic = K × ΔC + Ic — 0
Ie = K × ΔE + Ie — 0
Ip = K × ΔP + Ip — 0
The calculation data of the bottom current value (Ib), the bias current value (Ie), the cooling current value (Ic), and the peak current value (Ip) output from the arithmetic processor (DSP) 25 are respectively DA converters (DA1, DA2, DA3, DA4) and converted to an analog current value. Then, it is inputted to the pulse current sources 41, 42, 43 and 44, and the semiconductor laser 1 is pulse-driven according to the recording gate 206d, the recording pulse 206a, and the recording pulses 206b and 206c.

  Conventionally, with respect to the duty ratio of the pulse, the value of the pulse width MPW is different so that optimum recording characteristics can be obtained for each type of optical disk (including manufacturer and recording double speed). To cope with this, the reference clock is input to a circuit in which a plurality of delay elements are connected in multiple stages in multi-pulse generation, and is selectively output to change the width before and after the 50% duty ratio as a reference. (Details will be described later). Due to such a configuration, the influence of the accuracy and temperature fluctuation on the setting of the delay element increases as the pulse width deviates from 50%, and the duty ratio of the multi-pulse part deviates from the set duty ratio d. The impact will increase. While the duty ratio of the optical pulse is deviated from the set duty ratio d, the arithmetic processor calculates the peak value while maintaining the set duty ratio d, which causes a problem that an error occurs in the peak value. For example, when the channel clock is 132 MHz, the multipulse period Tw is 7.58 ns. The pulse width with a duty ratio of 40% is 3.03 ns. When the delay element is used to generate this duty ratio, the inventors have conducted experiments in which a deviation of about 0.3 ns in total occurs due to a deviation from the setting of the delay element or a temperature variation. In this case, the deviation of the pulse width with respect to the setting is about 10%. In the detection of peak power, the average value (Pa) is divided by the duty ratio (d) based on the above equation 2, so that the deviation in pulse width becomes the deviation in peak power as it is, which leads to deterioration of recording characteristics on the disc. .

  A feature of the present invention is that the laser power is controlled by a test light emission pattern in which the duty ratio is 50% in the multi-pulse light emission part in the test light emission period, regardless of the duty ratio of the multi-pulse part in the actual user data recording area. It is in.

In the laser control method of the present invention, a test light emission pattern with a duty ratio of 50% is generated in the multipulse light emitting section in the test light emission section, regardless of the duty ratio of the multipulse section in the actual user data recording area. Thus, an optical pulse having a duty ratio equal to the reference clock and 50%, which is not affected by the delay element of the recording pulse generator, is generated. Therefore, since the duty ratio of the optical pulse is equal to the set duty ratio d of the arithmetic processor, no error occurs in the calculation of the peak value, and the control accuracy of the peak power can be improved.
<4. Configuration of recording pulse generator>
FIG. 5 is a block diagram showing an example of the internal configuration of the recording pulse generator 111. FIG. 7 is a signal timing for explaining a specific operation example from generation of recording pulses 206a, 206b, and 206c from modulation data 208 using the recording pulse generator 111 having the internal configuration shown in FIG. FIG. FIG. 7 shows an example of a waveform when a 6T mark is recorded in a case where PWM recording is performed using a modulation rule in which the run length is limited in the range of 2 to 10.

  In FIG. 5, the pulse timing generator 501 receives the modulation data 208 supplied from another block, and receives a first pulse start reference timing 511a, a first pulse end reference timing 512a, a multi-pulse reference timing 513a, and a last pulse start reference timing 514a. The last pulse end / cooling pulse start reference timing 515a and the cooling pulse end reference timing 516a are generated and output. In addition, a test mode signal 600a that is H level only in the test light emission period is generated and output.

  The clock delay unit 502 receives a clock 510 (one cycle is one channel bit) synchronized with the modulation data 208, and the SFP, EFP, first MPW, second MPW set by the recording pulse position correction unit 112, Based on SLP, ELP, and ECP, eight types of delay clocks, that is, a first pulse start position reference clock 511b, a first pulse end position reference clock 512b, a multipulse start reference clock 513b, a first multipulse end reference clock 513c, 2 multi-pulse end reference clock 600c, last pulse start position reference clock 514b, last pulse end position / cooling pulse start position reference clock 515b, and cooling pulse end position reference clock 516b.

  Here, the multi-pulse start reference clock 513b is a clock signal that defines the rising edge position of the multi-pulse part and at the same time serves as a reference for all pulse edges. Each setting of SFP, EFP, MPW, SLP, ELP, and ECP The value is defined based on the time relationship with the multi-pulse start reference clock 513b.

  Also, as shown in FIG. 7, the first pulse start end reference timing 511a is a pulse signal having an H level for one cycle from the rising edge of the modulation data 208 from the rising edge of the first multi-pulse start end reference clock 513b. It is.

  As shown in FIG. 7, the first pulse end reference timing 512a is a pulse signal having an H level for one cycle from the rising edge of the modulation data 208 to the rising edge of the second pulse multi-pulse starting reference clock 513b.

  As shown in FIG. 7, the multipulse reference timing 513a is a rising edge of the fifth multipulse start reference clock 513b from a rising edge of the third multipulse start reference clock 513b from the rising edge of the modulation data 208. This is a gate signal that is at the H level during the period up to. However, the above is a case corresponding to the 6T mark. More generally, the multi-pulse reference timing 513a for the MT mark (M is an integer from 3 to 11) is the third wave from the rising edge of the modulation data 208. From the rising edge of the second multi-pulse start reference clock 513b, it becomes H level for a period of (M-4) channel bit period. However, in the case of M = 3, 4, that is, in the case of 3T mark or 4T mark, the multi-pulse reference timing 512a remains at the L level.

  Further, the last pulse start reference timing 514a, the last pulse end / cooling pulse start reference timing 515a, and the cooling pulse end reference timing 516a are, as shown in FIG. 7, from the rising edge of the modulation data 208, the multi-pulse start reference clock 513b. These are pulse signals having the H level for one cycle from the fourth wave falling edge, the fifth wave rising edge, and the sixth wave falling edge. However, the above is a case corresponding to the 6T mark. More generally, the last pulse start reference timing 514a, the last pulse end / cooling pulse start reference timing 515a for the MT mark (M is an integer from 3 to 11). The cooling pulse end reference timing 516a is the rising edge of the (M-2) th wave and the rising edge of the (M-1) th wave of the multi-pulse starting reference clock 513b from the rising edge of the modulation data 208, respectively. , A pulse signal having an H level corresponding to one period from the falling edge of the Mth wave.

  The first pulse start end reference timing 511a and the first pulse start end position reference clock 511b are respectively connected to the D input and clock input of the D flip-flop 503a, and the Q output of the D flip-flop 503a becomes the first pulse start end position signal 511c.

  The first pulse end reference timing 512a and the first pulse end position reference clock 512b are connected to the D input and clock input of the D flip-flop 503b, respectively, and the Q inverted output of the D flip-flop 503b becomes the first pulse end position signal 512c.

The last pulse start end reference timing 514a and the last pulse start end position reference clock 514b are connected to the D input and clock input of the D flip-flop 503c, respectively, and the Q output of the D flip-flop 503c becomes the last pulse start end position signal 514c. The cooling pulse start end reference timing 515a and the last pulse end position / cooling pulse start end reference clock 515b are connected to the D input and clock input of the D flip-flop 503d, respectively, and the Q inverted output of the D flip-flop 503d becomes the last pulse end position signal 515c. , Q output is a cooling pulse start position signal 515d.

  The cooling pulse end reference timing 516a and the cooling pulse end position reference clock 516b are connected to the D input and clock input of the D flip-flop 503e, respectively, and the Q inverted output of the D flip-flop 503e becomes the cooling pulse end position signal 516c.

  First pulse start position signal 511c and first pulse end position signal 512c are connected to the clock input and reset input of D flip-flop 505a, respectively. The D input of the D flip-flop 505a is fixed at the H level. As a result, the first pulse signal 517, which is the Q output of the D flip-flop 505a, becomes H level at the rising edge of the first pulse start position signal 511c when the first pulse end position signal 512c is at H level, as shown in FIG. It rises and falls to the L level at the falling edge of the first pulse end position signal 512c.

  The multipulse reference timing 513a, the multipulse start reference clock 513b, and the first multipulse end reference clock 513c are input to the logic element 504a. When the first MPW is a positive number, the logic element 504a calculates a logical product of a signal obtained by ORing the multipulse start reference clock 513b and the first multipulse end reference clock 513c and the multipulse reference timing 513a. And output as the first multi-pulse signal 518a. When the first MPW is a negative number, the logic element 504a performs a logical product of a signal obtained by ANDing the multipulse start reference clock 513b and the first multipulse end reference clock 513c and the multipulse reference timing 513a. And output as a first multi-pulse signal 518a.

  Further, the multi-pulse reference timing 513a, the multi-pulse start reference clock 513b, and the second multi-pulse end reference clock 600c are input to the logic element 504b. As shown in FIG. 8, when the second MPW is a positive number, the logic element 504b has a multi-pulse reference and a signal obtained by ORing a multi-pulse start reference clock 513b and a second multi-pulse end reference clock 600c. A logical product with the timing 513a is calculated and output as a second multi-pulse signal 518b. When the second MPW is a negative number, the logic element 504b performs a logical product of a signal obtained by ANDing the multipulse start reference clock 600c and the second multipulse end reference clock 513c and the multipulse reference timing 513a. And output as a second multi-pulse signal 518b.

  The first multi-pulse signal 518a, the second multi-pulse signal 518b, and the test mode signal 600a are input to the selection unit 504c. The test mode signal 600a is a signal that is at the H level in the test light emission section described with reference to FIG. The selection unit 504c selects the first multi-pulse signal 518a when the test mode signal 600a is at the L level, and selects the second multi-pulse signal 518b when the test mode signal 600a is at the H level. Output as signal 518.

  The last pulse start position signal 514c and the last pulse end position signal 515c are connected to the clock input and reset input of the D flip-flop 505b, respectively. The D input of the D flip-flop 505b is fixed at the H level. As a result, the last pulse signal 519, which is the Q output of the D flip-flop 505b, becomes H level at the rising edge of the last pulse start position signal 514c when the last pulse end position signal 515c is at H level, as shown in FIG. It rises and falls to the L level at the falling edge of the last pulse end position signal 515c.

  The cooling pulse start position signal 515d and the cooling pulse end position signal 516c are connected to the clock input and reset input of the D flip-flop 505c, respectively. The D input of the D flip-flop 505c is fixed at the H level. As a result, the cooling pulse signal 520, which is the Q output of the D flip-flop 505c, becomes H level at the rising edge of the cooling pulse start position signal 515d when the cooling pulse end position signal 516c is at H level, as shown in FIG. It rises and falls to the L level at the falling edge of the cooling pulse end position signal 516c.

  The first pulse signal 517, the multi-pulse signal 518, the last pulse signal 519, and the cooling pulse signal 520 generated as described above are input to the pulse synthesis unit 506. A pulse synthesizing unit 506 synthesizes and outputs three recording pulses 206a, 206b, and 206c from the above four types of signals. FIG. 7 shows a waveform example of the synthesized recording pulses 206a, 206b, and 206c.

The clock delay unit 502 can be configured by using a multistage connection of inverter elements or buffer elements, and a voltage control type delay element, similarly to each pulse delay unit used in the recording pulse generation unit 111 shown in FIG.
<5. Configuration of clock delay unit>
FIG. 6 is a block diagram illustrating an internal configuration example of the clock delay unit 502 configured using inverter elements. In FIG. 6, a plurality of inverter elements 601 are connected in series, and a clock 510 as an external input is connected to the first-stage inverter element 601. The number of stages of the inverter element 601 is the number of stages at which at least a delay amount that satisfies the variable range of each edge position of the recording pulses 206a, 206b, and 206c is obtained. For example, assuming that the variable range of each edge position of the recording pulses 206a, 206b, and 206c is ± 10 nanoseconds, and the delay amount of two stages of the inverter element 601 is 0.5 nanoseconds, 20 ÷ 0.5. = 40, and at least 80 inverter elements 601 are required.

  The selection unit 602 is connected to some or all of the outputs of the inverter elements 601, and selects and outputs any one of the outputs of the inverter elements 601 according to the selection signal 519. The selection unit 602 requires clock types having different delay amounts, and when incorporated in the recording pulse generation unit 111 shown in FIG. 5, eight types of clocks having different delay amounts (first pulse start end position reference clock 511b, first clock) Pulse end position reference clock 512b, multipulse start end reference clock 513b, first multipulse end reference clock 513c, second multipulse end reference clock 600c, last pulse start position reference clock 514b, last pulse end / cooling pulse start end position Since the reference clock 515b and the cooling pulse end position reference clock 516b) are necessary, eight selection units 602 are provided.

  The selection signal 519 is composed of a plurality of types of setting signals, including a selection signal 519a corresponding to the first pulse start position setting SFP, a selection signal 519b corresponding to the first pulse end position setting EFP, a multi-pulse start position, and further recording. A selection signal 519c for determining a reference position of each edge variable range of the pulse, a selection signal 519d corresponding to the first multi-pulse width setting MPW, a selection signal 519h corresponding to the second multi-pulse width setting MPW, and a last pulse start end position A selection signal 519e corresponding to the setting SLP, a selection signal 519f corresponding to the last pulse end position setting ELP, and a selection signal 519g corresponding to the cooling pulse end position setting ECP.

  As described above, the clock delay unit 502 can be easily configured by combining the inverter element 601 for sequentially delaying the input clock and the selection unit 602 for selecting the output of each inverter element. The minimum adjustment step of the recording pulse, which is the resolution of the recording compensation amount, corresponds to a delay time that passes approximately two inverter elements.

  The recording pulse generator of the present invention is characterized by the addition of hardware (the logic element 504b and the selector 504c in FIG. 5) that can individually generate the duty ratio of the multi-pulse part in the user data recording area and the test light emission period. It is in. A first duty ratio used for recording on the optical disc is set in the user data recording area, and a second duty ratio is set in the test light emission section. In actual operation, by setting the second MPW to 0, a signal that does not pass through the delay element is selected as the second multi-pulse termination reference clock 600c. As a result, the second multi-pulse signal output from the logic element 504b is a signal having a duty ratio of the reference clock that is not affected by the delay element. Therefore, the duty ratio of the test light emission section is an accurate 50% duty ratio with no temperature fluctuation. As a result, since the duty ratio of the light pulse in the test light emission section is equal to the set duty ratio d of the arithmetic processor (the set duty ratio d in Equation 2), no error occurs in the calculation of the peak value, and the peak power control accuracy is improved. be able to.

  The laser power control apparatus according to the present invention is useful as a DVD recording / reproducing apparatus or the like because the peak value can be accurately controlled regardless of the set duty ratio of the multi-pulse section.

Main configuration diagram of optical disc apparatus according to the present invention Main configuration diagram of laser power control unit in the present invention The schematic diagram for demonstrating an example to the shape of the recording pulse concerning this invention, the light emission waveform of a semiconductor laser, and the recording mark formed Signal waveform diagram of main part of laser control unit in the present invention Main configuration diagram of recording pulse generator in the present invention Main configuration diagram of clock delay unit in the present invention Signal waveform diagram in the user data recording area of the main part of the recording pulse generator in the present invention Signal waveform diagram of test light emission section of main part of recording pulse generator in the present invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Laser 2 Light receiving element 3 Current-voltage conversion circuit 11 Sample hold circuit SH0
12 Sample hold circuit SH1
13 Sample hold circuit SH2
14 Sample hold circuit SH3
15 Low-pass filter 21 AD conversion circuit AD1
22 AD conversion circuit AD2
23 AD conversion circuit AD3
24 AD conversion circuit AD4
25 Arithmetic processor (digital signal processor)
111 Recording Pulse Generation Unit 31 DA Conversion Circuit DA1
32 DA converter circuit DA2
33 DA converter circuit DA3
34 DA conversion circuit DA4
40 Laser Drive Circuit 41 Bottom Current Source 42 Cooling Current Source 43 Bias Current Source 44 Peak Current Source

Claims (3)

A method for controlling each power value of a first optical pulse including at least a multi-pulse for forming a recording mark in a data recording area of an optical disc,
In the test light emission section provided immediately before the data recording area, a second optical pulse including a multi-pulse having the same period and a different duty ratio as the multi-pulse of the first optical pulse is generated,
An error is detected between the light detection signal obtained by receiving the second optical pulse and converted into an electrical signal, and a reference value corresponding to the target power value of the first optical pulse, and the semiconductor laser is controlled so as to suppress the error. A laser power control method characterized by controlling a value of a flowing current. 2. The laser power control method according to claim 1, wherein a duty ratio of a multi-pulse of the second optical pulse is approximately 50%. An apparatus for controlling each power value of a first optical pulse including at least a multi-pulse for forming a recording mark in a data recording area of an optical disc,
Means for generating a second optical pulse including a multi-pulse having the same period and a different duty ratio as the multi-pulse of the first optical pulse in a test light emission section provided immediately before the data recording area When,
Means for receiving the second light pulse and generating a light detection signal converted into an electrical signal;
Means for determining an error between the photodetection signal and a reference value corresponding to a target power value of the first optical pulse, and controlling a value of a current flowing through the semiconductor laser so as to suppress the error;
A laser power control device comprising:

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