JP2000276515A - Device and method for verifying timing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a timing verifying device and a timing verifying method capable of performing a static timing verification when a clock is generated internally and further performing the static timing verification in a short time even when many parts that do not synchronize with an external clock in static timing verification in developing an LSI. SOLUTION: This device consists of an inputting part 11, a data processing part 1 which retrieves a clock generation circuit on the basis of information composed of a net list inputted from the part 11 by program control, a test pattern, the designation information of a clock signal and a library defining the logic and delay of a logical circuit, a clock cycle specifying 31 specifying a clock cycle generated by a clock generation circuit by simulation, a displaying part 32 which shows a message when a clock cycle can not be specified and a timing verifying part 41 which verifies the timing of a flip-flop in a circuit by static timing verification.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing verification technique for a logic circuit in developing an LSI, and more particularly to a timing verification apparatus and a timing verification method for performing static timing verification on an asynchronous logic circuit.

[0002]

2. Description of the Related Art Conventionally, in LSI design, there is a static timing analysis method as a method for verifying the operation timing of a circuit to be verified.
No. 552 discloses this.

That is, a static timing analysis is performed on a synchronous circuit, and then, starting from a synchronous latch or an external data pin that cannot be verified by the static timing verification, a plurality of stages of asynchronous circuits connected to these are started. For the latch, sequentially derive the condition regarding the timing of the asynchronous clock for each element to operate normally under the worst condition,
Further, based on an element receiving data from an external data pin or a synchronous latch, a constraint condition relating to external input data or data timing for normal operation under worst conditions is derived and verified.

[0004]

However, the prior art has the following problems. The problem that the internally generated clock cycle cannot be obtained only from the information of the external clock and the timing information of the external data pin, and static timing verification cannot be performed when the clock is generated internally. There was a point.

Further, it is necessary to derive external input data or data timing which operates under the worst conditions for all the elements which are not synchronized with the external clock. There was a problem that it took.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a static timing verification for developing an LSI, even when a clock is internally generated. , Static timing verification,
Even when there are many parts that are not synchronized with the external clock,
It is an object of the present invention to provide a timing verification device and a timing verification method capable of performing static timing verification in a short time.

[0007]

Means for Solving the Problems In order to solve the above problems, the present invention has the following constitution. The gist of the invention described in claim 1 is that a clock input is performed based on a netlist to be verified, a test pattern, designation information of an external input clock signal input from an external input terminal, and a library defining logic and delay of a logic circuit. A timing verification apparatus having a terminal and performing static timing verification of a logic circuit to be verified in which a setup time, a hold time, a release time, and a removal time in the netlist are defined, wherein: An asynchronous logic circuit searching means for searching the verified logic circuit which is not synchronized with the external input clock signal inputted from the external input terminal from the list as an asynchronous logic circuit; and Verification clock for driving the asynchronous logic circuit at an input terminal of the asynchronous logic circuit Resides No. timing verification apparatus characterized by Enter; and a timing verification means for performing a static timing analysis of the asynchronous logic circuit. The gist of the invention according to claim 2 is that a clock generation circuit that traces the netlist from a clock input terminal of the asynchronous logic circuit searched by the asynchronous logic circuit search means and specifies the preceding logic circuit as a clock generation circuit. Circuit specifying means; and clock cycle specifying means for simulating an internally generated clock signal output from an output terminal of the clock generation circuit by the test pattern to specify a clock cycle of the internally generated clock signal. 2. The timing verification device according to claim 1, wherein the clock signal of the clock cycle specified by the clock cycle specifying unit is input from an output terminal of the clock generation circuit and used as the verification clock signal.
Further, the gist of the invention according to claim 3 is that a logic circuit searching means for searching for the verified logic circuit from the netlist to be verified, and a logic circuit searching means for synchronizing with the external input clock signal from the netlist to be verified. Synchronous logic circuit searching means for searching for the logic circuit to be verified, wherein the asynchronous logic circuit searching means compares the search result of the logic circuit searching means with the search result of the synchronous logic circuit searching means. 3. The timing verification device according to claim 1, wherein the asynchronous logic circuit is searched. The gist of the invention according to claim 4 is that the clock generation circuit specifying means traces the netlist from an input terminal of the clock generation circuit and connects the external input terminal to which a signal for driving the clock generation circuit is input. 4. The timing verification device according to claim 1, wherein the clock pattern specifying unit inputs the test pattern from the external input terminal to which a signal for driving the clock generation circuit is input. . The gist of the invention according to claim 5 is that the clock cycle specifying means determines the clock cycle if the clock cycle of the internally generated clock signal output from the output terminal of the clock generation circuit cannot be specified by simulation. 5. The timing verification device according to claim 1, wherein a message signal is output to notify that the signal cannot be specified. The gist of the invention according to claim 6 is that, when the clock cycle of the internally generated clock signal output from the output terminal of the clock generation circuit changes by simulation, the internally generated clock cycle is determined. The timing verification device according to claim 1, wherein the clock cycle having the shortest clock cycle of a clock signal is specified. The gist of the invention according to claim 7 resides in the timing verification device according to any one of claims 1 to 6, wherein the verified logic circuit is a flip-flop. The gist of the invention described in claim 8 is that a clock based on a netlist to be verified, a test pattern, designation information of an external input clock signal input from an external input terminal, and a library defining logic and delay of a logic circuit. A timing verification method for performing static timing verification of a verified logic circuit having an input terminal and having a setup time, a hold time, a release time, and a removal time defined in the netlist, the method comprising: The logic circuit to be verified that is not synchronized with the external input clock signal input from the external input terminal is searched as an asynchronous logic circuit, and the input terminal of the asynchronous logic circuit searched by the asynchronous logic circuit search unit is A verification clock signal for driving the asynchronous logic circuit is inputted, and the asynchronous logic circuit is inputted. It exists to perform a static timing analysis of the timing verification method comprising.
The gist of the invention according to claim 9 is that the netlist is traced from the searched clock input terminal of the asynchronous logic circuit, the preceding logic circuit is specified as a clock generation circuit, and the clock pattern is specified by the test pattern. A clock cycle of the internally generated clock signal is specified by simulating an internally generated clock signal output from an output terminal of the generation circuit, and a clock signal of the specified clock cycle is input from an output terminal of the clock generation circuit. The timing verification method according to claim 8, wherein the timing verification signal is used as the verification clock signal.
The gist of the invention according to claim 10 is that the logic circuit to be verified is searched for from the netlist to be verified and the logic circuit to be synchronized with the external input clock from the netlist to be verified. 10. The timing verification method according to claim 8, wherein a search is made as a synchronous logic circuit, and the asynchronous logic circuit is searched by comparing the searched logic circuit to be searched with the searched synchronous logic circuit. Exists. The gist of the invention according to claim 11 is to trace the netlist from an input terminal of the clock generation circuit, identify the external input terminal to which a signal for driving the clock generation circuit is input, and specify the clock generation circuit. The timing verification method according to any one of claims 8 to 10, wherein the test pattern is input from the external input terminal to which a signal to be driven is input. According to another aspect of the invention, when the clock cycle of the internally generated clock signal output from the output terminal of the clock generation circuit cannot be specified by the simulation, it is notified that the clock cycle cannot be specified. The timing verification method according to any one of claims 8 to 11, wherein a message signal is output. The gist of the invention according to claim 13 is that when the clock cycle of the internally generated clock signal output from the output terminal of the clock generation circuit changes due to the simulation, the clock cycle of the internal clock signal is changed. The minimum clock period is specified.
In the timing verification method described in any of the above. The gist of the invention described in claim 14 is that the verified logic circuit is a flip-flop.
The present invention resides in the timing verification method according to any one of the first to thirteenth aspects. The gist of the invention described in claim 15 resides in a storage medium storing a program capable of executing the timing verification method according to any one of claims 7 to 14.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing the configuration of a first embodiment of a timing verification device according to the present invention.

The first embodiment has an input unit 11 for inputting a netlist of a circuit to be verified, a test pattern, clock signal designation information, and a library defining logic and delay of a logic circuit, and an input unit for program control. A data processing unit 1 for searching for a clock generation circuit based on a netlist, a test pattern, clock signal designation information input from 11 and a library defining logic and delay of a logic circuit, and clock generation by simulation A clock cycle specifying unit 31 for specifying a clock cycle generated in the circuit, a display unit 32 for displaying a message when the clock cycle cannot be specified, and a flip-flop (hereinafter referred to as F
/ F) and a static timing verification unit 41 for verifying the timing.

The data processing section 1 includes an all-F / F search section 21 for searching for all F / Fs in a netlist, a synchronous F / F search section 22 for searching for a synchronous F / F in a netlist,
Asynchronous F / F for searching asynchronous F / F in netlist
It comprises a search unit 23 and a clock generation circuit search unit 24 for searching for a clock generation circuit in the netlist.

The all-F / F search unit 21 retrieves the F / F defined as having a clock terminal in the library from the input netlist with a unique name assigned to each F / F. Search for.

The synchronous F / F search unit 22 specifies an external input terminal for inputting a clock from the input netlist, and traces from the external input terminal for inputting the specified clock, thereby obtaining an external input terminal for inputting a clock. F connected to the input terminal
/ F is searched as a synchronous F / F with a unique name assigned to each F / F.

The asynchronous F / F search unit 23 checks whether or not the results searched by the all F / F search unit 21 and the synchronous F / F search unit 22 match. And an unmatched F / F is set as an asynchronous F / F, and the search result is supplied to the clock generation circuit search unit 24.

[0015] The clock generation circuit search unit 24 outputs an asynchronous F /
The net list is traced from the clock input terminal of the asynchronous F / F searched by the F search unit 23, a logic circuit at the preceding stage is searched, a searched logic circuit is specified as a clock generation circuit, and an output terminal of the searched logic circuit is specified. Is specified as a clock generation terminal. The external input terminal for driving the clock generation circuit is specified by tracing the netlist from the searched logic circuit, that is, the input terminal of the clock generation circuit to the external input terminal.

The clock cycle specifying unit 31 inputs the test pattern specified by the input unit 11 only to the external input terminal specified by the clock generating circuit searching unit 24, and outputs the clock generating terminal specified by the clock generating circuit searching unit 24. While observing the signal, the simulation is performed using the input test pattern to specify the clock cycle. Specifically, the signal output from the output pin of the clock generation terminal specified by the clock generation circuit search unit 24, that is, the clock cycle is specified, and the time when the signal changes from 0 to 1;
Next, the difference from the time when it changes from 0 to 1 is continuously observed,
When the time difference is stabilized, the clock cycle is specified. If no change in this signal was observed due to the input test pattern, or if the difference between the time when the signal changed from 0 to 1 and the time when the signal next changed from 0 to 1 was not stable, the signal was input. Since there is a possibility that the test pattern has an error, a signal indicating that the clock cycle cannot be specified is output, a message indicating that the clock cycle could not be specified is displayed on the display unit 32, and another test pattern is input again. Ask.

The static timing verifying section 41 has a synchronous F / F
In response to the synchronous F / F searched by the search unit 22, the input unit 11
The static timing analysis is performed based on the clock cycle designation information input from the asynchronous F / F search unit 23.
The clock signal of the clock cycle specified by the clock generation circuit search unit 24 is supplied to the clock generation terminal specified by 4 to perform the static timing analysis.

Next, the operation of the first embodiment of the present invention will be described in detail with reference to FIG.

FIG. 2 is a flowchart for explaining the operation of the first embodiment of the timing verification device according to the present invention.

First, a netlist of a circuit to be verified, a test pattern, a clock designation, and a library defining logic and delay of a logic circuit are input to the input unit 11 (step A10).

Next, the netlist of the circuit to be verified, the test pattern, the clock specification, and the library defining the logic and delay of the logic circuit, which are input to the input unit 11, are supplied to the data processing unit 1 and all F / The F search unit 21 searches the input netlist for an F / F defined as having a clock terminal in the library with a unique name assigned to each F / F, and searches for a synchronous F / F. F search unit 22
Then, the external input terminal for inputting the clock is specified from the input netlist, and the F / F connected to the external input terminal for inputting the clock is synchronized by tracing from the external input terminal for inputting the specified clock. A search is performed using a unique name assigned to each F / F as / F. Next, the search result of the all F / F search unit 21 and the search result of the synchronous F / F search unit 22 are supplied to the asynchronous F / F search unit 23. Synchronous F / F with 21
Check whether the search result matches with the search unit 22,
Search for unmatched F / Fs and search for unmatched F / Fs
As an asynchronous F / F, and supplies the search result to the clock generation circuit search unit 24 (step A20).

The search result of the all F / F search unit 21 and the synchronous F / F
When the search results of the F search unit 22 match, the static timing analysis unit 41 performs a static timing analysis using the clock designation given first as a timing constraint (step A70).

Next, the clock generation circuit search unit 24 traces the netlist from the clock input terminal of the asynchronous F / F searched by the asynchronous F / F search unit 23, searches for the logic circuit at the preceding stage, and searches the searched logic circuit. The circuit is specified as a clock generation circuit, and the output terminal of the searched logic circuit is specified as a clock generation terminal. The external input terminal for driving the clock generation circuit is specified by tracing the netlist from the searched logic circuit, that is, the input terminal of the clock generation circuit to the external input terminal (step A30).

Next, the result of the clock generation circuit search section 24 and the test pattern input from the input section 11 are supplied to the clock cycle specification section 31, and the external clock specified by the clock generation circuit search section 24 by the clock cycle specification section 31. The test pattern input from the input unit 11 is input only to the input terminal, and the simulation is performed using the input test pattern while observing the signal of the clock generation terminal specified by the clock generation circuit search unit 24. The difference between the time when the signal of the clock generation terminal changes from 0 to 1 and the time when the signal next changes from 0 to 1 is continuously observed, the cycle of the generated clock is specified, and the clock generation circuit search unit 24 It is determined whether or not the clock cycle of the clock output from the clock generation terminal specified in (1) can be specified (step A4).
0).

If the clock cycle can be specified, a clock signal of the specified clock cycle is specified (step 50). Then, the specified clock signal is supplied to the static timing verification unit 41, and the asynchronous F / F searched by the asynchronous F / F search unit 23 by the static timing verification unit 41 is specified by the clock generation circuit search unit 24. A clock signal having the clock cycle specified by the clock generation circuit search unit 24 is supplied to the specified clock generation terminal to perform a static timing analysis. Further, for the synchronous F / F searched by the synchronous F / F search unit 22, static timing analysis is performed based on the designation information of the clock signal input from the input unit 11 (step A70).

When the clock cycle cannot be specified, that is, when the change from 0 to 1 is not continuously observed at the clock generation terminal, or when the signal changes from 0 to 1 and the time when the signal next changes from 0 to 1 If the difference is not stable, there is a high possibility that the input test pattern has an error, so that a clock cycle unspecified signal is output and a message indicating that the clock cycle could not be identified is displayed on the display unit 32. Then, a request is made to input another test pattern again (step A60).

Next, the operation of this embodiment will be described in more detail with reference to the specific examples shown in FIGS.

FIG. 3 is a netlist diagram showing an example of a netlist of a circuit to be subjected to timing verification according to the present invention, and FIG. 4 illustrates a clock cycle specified by the clock cycle specifying unit shown in FIG. FIG. 6 is a waveform diagram of a clock signal for performing the operation.

As shown in FIG. 3, the netlist to be verified has seven F / Fs, and reg0, reg1, reg2, reg3, reg4, reg5, A unique name is given to each F / F called reg6.

First, a clock list having a cycle of 10 ns and a library defining the logic and delay of a logic circuit are input to the input device 11 as shown in FIG.

Next, in the entire F / F search unit 21, an F / F defined as having a clock terminal in the library from the input netlist is a unique F / F assigned to each F / F. Search by name, reg0, reg1,
Obtain reg2, reg3, reg4, reg5, reg6.

Next, the synchronous F / F search unit 22 specifies a clock designation terminal Clock which is an external input terminal for inputting a clock from the input netlist, and traces the clock designation terminal Clock from the specified clock designation terminal Clock. Clock designation terminal C
Search for F / F linked to lock by unique name given to each F / F, and search results reg0, reg1, re
g2, reg3. Next, in the asynchronous F / F search unit 23, all F
The / F search unit 21 and the synchronized F / F search unit 22 check whether the search results match, search for unmatched F / Fs, and obtain reg4, reg5, and reg6. Next, the clock generation circuit search unit 24 first specifies the output terminal of the preceding logic circuit connected to the clock input terminals of reg4, reg5, and reg6. In this case, since reg4, reg5, and reg6 are all connected to the output of nor1, the output terminal of nor1 is specified as the clock generation terminal. Next, follow the netlist from the input terminal of nor1 to the external input terminal, search for the external input terminal driving the clock generation circuit, and enter the external input terminal name En.
Specify able, Reset, and Clock.

Next, the clock cycle specifying section 31 is connected to the input section 11.
Is given to only the external input terminals Enable, Reset, and Clock specified by the clock generation circuit search unit 24, and the simulation is performed while observing a signal change of the output terminal of nor1 specified as the clock generation terminal. Do. From the signal output from the output pin of nor1 specified as the clock generation terminal, the difference between the time when the signal changes from 0 to 1 and the time when the signal next changes from 0 to 1 is continuously observed. When the time difference is stabilized, the time ans changing from 0 to 1 and the time bns changing from 0 to 1 are specified as shown in FIG. 4, and the clock cycle is specified as (ba) ns from these time differences. I do.

Next, the clock signal of the clock cycle (ba) ns specified by the clock cycle specifying unit 31 is supplied to the static timing verification unit 41, and the static timing verification unit 41 searches the asynchronous F / F search unit 23. Asynchronous F / F
A static timing analysis is performed by supplying a clock signal having a clock cycle (ba) ns to the output terminal of nor1. Synchronous F / F
For the synchronous F / F searched by the search unit 22, static timing analysis is performed based on the clock signal designation information input from the input unit 11.

As described above, according to the first embodiment, the clock signal output from the clock signal generating terminal can be specified by searching the clock generating terminal from the connection information of the netlist and performing the simulation. Also, even when a clock is generated in a circuit, there is an effect that static timing verification of the F / F driven by the internally generated clock can be performed.

Further, since the internal clock generating sub-circuit is specified and only that portion is simulated, there is an effect that the static timing can be verified in a short time even when there are many portions not synchronized with the external clock.

(Second Embodiment) FIG. 5 is a block diagram showing a configuration of a timing verification device according to a second embodiment of the present invention.

In the second embodiment, in addition to the configuration of the first embodiment shown in FIG. 1, a clock cycle change verifying unit 33 for verifying a change in clock cycle is provided.

The clock cycle change verification section 33 changes the time at which the signal output from the output pin of the clock generation terminal continuously observed by the clock cycle identification section 31 changes from 0 to 1, and then changes from 0 to 1. It is verified whether or not the difference from the time does not change. If the difference between the change times changes, the difference between the change times, that is, the clock cycle of the smaller clock cycle (stricter fast clock cycle as a constraint) is specified, and the Is supplied to the dynamic timing verification unit 41. Further, the clock cycle is also verified with respect to the designation information of the clock signal input from the input unit 11, and when the clock cycle changes, the clock cycle of the smaller clock cycle (stricter clock cycle as a constraint) is specified. This is supplied to the static timing verification unit 41.

FIG. 6 shows the operation of the second embodiment of the present invention.
This will be described in detail with reference to FIGS.

FIG. 6 is a flowchart for explaining the operation of the second embodiment of the timing verification device according to the present invention. FIG. 7 is a diagram for explaining the change of the clock cycle verified by the clock cycle change verification section shown in FIG. FIG. 6 is a waveform diagram of a clock signal for performing the operation. The description of the same steps as those in the flowchart shown in FIG. 2 will be omitted.

The clock cycle change verifying unit 33 determines the time when the signal output from the output pin of the clock generation terminal observed by the clock cycle specifying unit 31 changes from 0 to 1 and the time when the signal next changes from 0 to 1. And whether the clock cycle of the clock signal designation information input from the input unit 11 does not change is verified (step A51).

Next, when the difference between the change times changes, a clock signal having a smaller change time difference, that is, a clock signal with a smaller clock cycle (a faster clock cycle as a constraint) is specified and supplied to the static timing verification unit 41. That is, as shown in FIG. 7, the times a, b, c, and d at which the signal output from the output pin of the clock generation terminal changes from 0 to 1 are observed,
The difference (d) of the smallest change time among the differences (ba), (cb), and (dc) between the time when the signal changes from 0 to 1 and the time when the signal next changes from 0 to 1 -C) is specified and supplied to the static timing verification unit 41 (step A52).

As described above, according to the second embodiment, there is an effect that the static timing verification can be performed in consideration of the case where the clock cycle of the clock signal changes during the operation of the circuit.

In the present embodiment, the logic circuit to be subjected to the timing verification is specified as the F / F. However, the present invention provides a setup time (Setup time), a hold time (Ho
ld time), release time (Relase time), and removal time (Removal time) are defined and can be applied to a logic circuit having a clock input terminal.

It should be noted that the present invention is not limited to the above embodiments, and it is clear that each embodiment can be appropriately modified within the scope of the technical idea of the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, but can be set to numbers, positions, shapes, and the like suitable for carrying out the present invention. In the drawings, the same components are denoted by the same reference numerals.

[0047]

According to the timing verification apparatus and the timing verification method of the present invention, a clock signal output from the clock signal generation terminal can be specified by searching the clock generation terminal from the connection information of the netlist and performing simulation. Also, even when a clock is generated in a circuit, there is an effect that static timing verification of the F / F driven by the internally generated clock can be performed. Furthermore, since the internal clock generation sub-circuit is specified and only that portion is simulated, there is an effect that the static timing can be verified in a short time even when there are many portions not synchronized with the external clock.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a first embodiment of a timing verification device according to the present invention.

FIG. 2 is a flowchart illustrating an operation of the first embodiment of the timing verification device according to the present invention.

FIG. 3 is a netlist diagram showing an example of a netlist of a circuit to be subjected to timing verification according to the present invention;

FIG. 4 is a waveform diagram of a clock signal for explaining a clock cycle specified by a clock cycle specifying unit shown in FIG. 1;

FIG. 5 is a block diagram showing a configuration of a first embodiment of a timing verification device according to the present invention.

FIG. 6 is a flowchart illustrating an operation of the first embodiment of the timing verification device according to the present invention.

FIG. 7 is a waveform diagram of a clock signal for describing a change in a clock cycle verified by a clock cycle change verification unit illustrated in FIG. 5;

[Explanation of symbols]

 Reference Signs List 1 data processing unit 11 input unit 21 full F / F search unit 22 synchronous F / F search unit 23 asynchronous F / F search unit 24 clock generation circuit search unit 31 clock cycle identification unit 32 display unit 33 clock cycle change verification unit 41 static Timing Verifier

Claims (15)

[Claims] A clock input terminal based on a netlist to be verified, a test pattern, designation information of an external input clock signal inputted from an external input terminal, and a library defining logic and delay of a logic circuit; A timing verification device for performing static timing verification of a verified logic circuit in which a setup time, a hold time, a release time, and a removal time are defined in a netlist, wherein An asynchronous logic circuit searching means for searching, as an asynchronous logic circuit, the logic circuit to be verified which is not synchronized with the external input clock signal inputted from an external input terminal; and an input of the asynchronous logic circuit searched by the asynchronous logic circuit searching means. A verification clock signal for driving the asynchronous logic circuit is input to the terminal Timing verification apparatus characterized by comprising a timing verification means for performing a static timing analysis of the serial asynchronous logic circuits. 2. A clock generation circuit specifying means for tracing the netlist from a clock input terminal of the asynchronous logic circuit searched by the asynchronous logic circuit search means and specifying the preceding logic circuit as a clock generation circuit; Clock cycle identification means for simulating an internally generated clock signal output from an output terminal of the clock generation circuit in accordance with a test pattern to identify a clock cycle of the internally generated clock signal; 2. The timing verification device according to claim 1, wherein the clock signal having the clock cycle is input from an output terminal of the clock generation circuit and used as the verification clock signal. 3. A logic circuit retrieving means for retrieving the verified logic circuit from the netlist to be verified, and the verified logic circuit synchronized with the external input clock signal from the netlist to be verified. And a synchronous logic circuit searching means for searching for the asynchronous logic circuit. The asynchronous logic circuit searching means causes the asynchronous logic circuit to be searched based on a comparison between a search result of the logic circuit searching means and a search result of the synchronous logic circuit searching means. The timing verification device according to claim 1, wherein: 4. The clock generation circuit specifying means traces the netlist from an input terminal of the clock generation circuit, specifies the external input terminal to which a signal for driving the clock generation circuit is input, and specifies the clock cycle. 2. The identification unit according to claim 1, wherein the test pattern is input from the external input terminal to which a signal for driving the clock generation circuit is input.
Or the timing verification device according to 3. 5. The clock cycle specifying means, when the clock cycle of the internally generated clock signal output from the output terminal of the clock generation circuit cannot be specified by simulation, notifies that the clock cycle cannot be specified. 5. The timing verification device according to claim 1, wherein the timing verification device outputs a message signal. 6. The clock cycle specifying means, wherein when the clock cycle of the internally generated clock signal output from the output terminal of the clock generation circuit changes by simulation, the clock cycle of the internally generated clock signal is changed. 6. The timing verification device according to claim 1, wherein the clock cycle having the smallest value is specified. 7. The timing verification device according to claim 1, wherein the verification target logic circuit is a flip-flop. And a clock input terminal based on a netlist to be verified, a test pattern, designation information of an external input clock signal input from an external input terminal, and a library defining logic and delay of a logic circuit. A timing verification method for performing static timing verification of a verified logic circuit in which a setup time, a hold time, a release time, and a removal time are defined in a netlist, wherein the external input terminal is selected from the netlist. The asynchronous logic circuit is searched for the logic circuit to be verified which is not synchronized with the external input clock signal input from the asynchronous logic circuit, and the asynchronous logic circuit is driven to the input terminal of the asynchronous logic circuit searched by the asynchronous logic circuit searching means. A verification clock signal is input, and the static timing of the asynchronous logic circuit is The timing verification method and carrying out the testimony. 9. The logic circuit of a preceding stage is specified as a clock generation circuit by tracing the netlist from a clock input terminal of the searched asynchronous logic circuit, and from the output terminal of the clock generation circuit according to the test pattern. Simulating the internally generated clock signal to be output to specify a clock cycle of the internally generated clock signal; inputting the clock signal of the specified clock cycle from an output terminal of the clock generation circuit; 9. The timing verification method according to claim 8, wherein the timing verification method is used. 10. The logic circuit to be verified is searched from the netlist to be verified, and the logic circuit to be synchronized with the external input clock is searched as a synchronization logic circuit from the netlist to be verified. 10. The timing verification method according to claim 8, wherein the asynchronous logic circuit is searched based on a comparison between the searched logic circuit to be searched and the searched synchronous logic circuit. 11. An external input terminal to which a signal for driving the clock generation circuit is input by tracing the netlist from an input terminal of the clock generation circuit, and a signal for driving the clock generation circuit is input. 11. The timing verification method according to claim 8, wherein the test pattern is input from the external input terminal. 12. When the clock cycle of the internally generated clock signal output from the output terminal of the clock generation circuit cannot be specified by the simulation, outputting a message signal indicating that the clock cycle cannot be specified. The timing verification method according to any one of claims 8 to 11, wherein: 13. When the clock cycle of the internally generated clock signal output from the output terminal of the clock generation circuit changes due to the simulation, the clock cycle having the smallest clock cycle of the internal clock signal is determined. 13. The timing verification method according to claim 7, wherein the timing verification is performed. 14. The timing verification method according to claim 7, wherein the verified logic circuit is a flip-flop. 15. A storage medium storing a program capable of executing the timing verification method according to claim 7. Description: