JP2000276506A - Cad system for electronic circuit board design and recording medium storing program used for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CAD system for electronic circuit board design which can accurately grasp or check the conductive situation of a wiring part such as connection of plating wiring and a side face metallization layer with simple processing and also has a function capable of smoothly and simply changing its set content in accordance with an inspection target and the difference of a substrate type, etc. SOLUTION: This CAD system subdivides a connection decision target area into plural element areas including current-carrying connection areas T, L, B and R and generates sets of wiring net diagrams connected to them for every area of T, L, B and R being connection decision targets. Then, it performs a set operation following a prescribed operation expression among the sets and generates wiring net connection information on the basis of the operated results. Thus, the conductive situation of a wiring part such as the connection of plating wiring and a side face metallization layer can accurately be grasped or checked with simple processing. Also, even in the case discrimination conditions are different in accordance with a discrimination target and a target type, a desired discrimination condition can accurately set by using an operation expression and accordingly, various needs can be dealt with smoothly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a CAD system for designing an electronic circuit board and a recording medium storing a program used therein.

[0002]

2. Description of the Related Art In recent years, as the degree of integration of semiconductor chips such as ICs and microprocessors has rapidly increased, the number of terminals of input / output units of the chips has also increased significantly. In response to this, the number of wiring parts on the electronic circuit board for connecting such chips has also increased rapidly, and a multilayer type wiring part that has built up multi-layer wiring parts through insulating layers of polymer materials and ceramics etc. Package substrates are increasing. In such an electronic circuit board, there are conductive portions serving as connection terminals, such as pads (or lands) for connecting to a chip and pads for connecting itself to another wiring board such as a motherboard. It is usually formed by exposing a large number on the surface. For example, in the electronic circuit board B shown in FIG. 1, a wiring portion 201 is formed in an insulating layer 200 made of resin or ceramic, and an end of the wiring portion 201 is bonded for connection with a terminal on a chip side. While the pad 203 is formed, an intermediate portion of the wiring section 201 is connected via a via 207 to a pin pad 202 (for connecting the connection pin 206) formed on the rear surface of the substrate.

Recently, in order to efficiently design such an electronic circuit board, a design system using a computer drawing process, so-called CAD (Computer Aided Desig) has been proposed.
ning) system is used. This is done by opening a drawing screen on the display device and drawing a figure such as a wiring part or a pad or a via for making a connection between different wiring layers on the drawing screen using an input device such as a mouse. Is what you get.

[0004] By the way, pads or lands on the above-mentioned substrate are usually plated to ensure connection. To perform such plating,
Generally, a plating line portion 204 is formed on the wiring portion 201,
Metallization layer 20 for energizing plating formed on the side of substrate
5 to the wiring section 2 from the metallization layer 205.
A method of energizing through 01 is adopted. Therefore,
It is important from a design point of view that a wiring portion connected to each pad or the like is designed so that a plating line is connected to a metallized layer without fail. For example, if a plated wire is missing from a certain wiring portion, a defect such as plating omission or plating unevenness may occur in a pad or the like connected to the wiring portion.

[0005] When the number of wiring portions formed in one substrate increases and the wiring portions are complicatedly interlaced over a plurality of layers, even when drawing a design drawing using a CAD system, one wiring portion is formed. It is very difficult to accurately grasp the state of formation of the plating line for each wiring portion, and the above-described failure due to oversight of a missing plating line is inevitable. Then, for example, Japanese Patent Application Laid-Open No. 63-188267.
Various inspection methods have been proposed on CAD, such as Japanese Patent Application Laid-Open Publication No. H10-107, which can grasp the conduction state of a wiring portion.

[0006]

Here, in an actual electronic circuit board, the shape, position and number of energized metallized layers often differ depending on the type. This means that the setting content (for example, the number, the position, and the shape) of the connection determination target area is different depending on the type on the drawing screen.
Also, the plating energization method may be different depending on the product type, and this leads to a difference in the conditions for determining the connection status of the plated wires. However, with the conventional inspection method, there is a case where the inspection setting contents cannot be changed or the setting contents change work is very troublesome. There were many.

SUMMARY OF THE INVENTION An object of the present invention is to make it possible to accurately grasp or check the continuity state of a wiring portion by a simple process, such as joining of a plated wire and a side metallization layer, and to perform inspection purposes and differences in board types. An object of the present invention is to provide a CAD system for designing an electronic circuit board having a function of changing the setting contents flexibly and easily in accordance with the above, and a recording medium storing a program to be used for the system.

[0008]

According to the present invention, a plurality of wiring layers are laminated via an insulating layer, and a portion to be plated where a wiring portion formed in the wiring layer is conductive is formed on a substrate. The present invention relates to a CAD system for designing an electronic circuit board having an energization metallization layer formed on a side surface while being formed on the surface while being connected to the wiring portion. A wiring pattern figure input means for inputting a wiring pattern figure on the drawing screen, a reference area corresponding to the outer shape of the main surface of the substrate, and a reference area including a conduction connection area corresponding to the conduction metallization layer. Area setting means for setting a connection determination target area formed outside on the drawing screen, and an element area for setting a plurality of element areas including one or a plurality of energized connection areas for the connection determination target area A constant section, corresponding to each element region, a variable representing a set of wiring patterns graphic to be connected to the element region (hereinafter, referred to as pattern set variables) and pattern set variable setting means for setting a, and the pattern set variable,
Arithmetic expression storage means for storing an arithmetic expression described using one or two or more types of operators combined therewith, prepared in correspondence with each operator, and defined in advance for each operator Operation program module storage unit for storing an operation program module for executing the set operation contents, an operation expression reading unit for reading an operation expression from the operation expression storage unit, and a pattern set included in the read operation expression A pattern set generation for detecting a variable and extracting, from among the wiring pattern figures, those connected to an element area corresponding to the pattern set variable to generate a set of wiring pattern figures corresponding to the pattern set variable. Means and a set defined by each operator for a set of wiring pattern graphics indicated by each pattern set variable in accordance with the description content of the arithmetic expression. An operation executing means for executing an operation using a corresponding operation program module; a wiring pattern connection information generating means for generating information on a connection state between the wiring pattern figure and the energized connection area based on the operation result; And wiring pattern connection information output means for outputting the obtained wiring pattern connection information.

In the CAD system, a connection determination target area is subdivided into a plurality of element areas including a current-carrying connection area, and a set of wiring net figures connected to each of the element areas for connection determination is generated. . Then, a set operation according to a predetermined operation expression is performed between these sets, and wiring net connection information is generated based on the operation result. As a result, even when the discrimination conditions are different depending on the purpose of discrimination and the board type, it is possible to accurately set desired discrimination conditions by using an arithmetic expression, and thus flexibly respond to various needs. it can.

[0010] The recording medium of the present invention is characterized by storing a program for causing a computer to function as each means constituting the CAD system of the present invention. Thus, the CAD system of the present invention can be easily realized by installing the program stored in the recording medium into a computer.

The operators include a union operator for obtaining a union of a set of two wiring pattern figures, an operator for a difference operation for obtaining a difference set, an operator for a product operation for obtaining a common set, and It may include at least one of a negative operation operator for obtaining a negative set of a certain set of wiring pattern figures for a mother set including all registered wiring pattern figures. This makes it possible to cover most of the discriminating conditions required for the design of the connection state of the plated wires except for the special substrate. This will be described in detail in the section of the embodiment of the invention. For example, as an arithmetic expression, pattern set variables corresponding to all the set energized connection areas are connected in series by a sum operation, and the result is subjected to a negative operation. Is stored, it is possible to obtain information on the existence of a wiring pattern graphic that is not connected to any of the energized connection regions (that is, a wiring pattern graphic with missing plated lines).

In the above configuration, it is possible to provide arithmetic expression input means for inputting an arithmetic expression. In this case, the arithmetic expression storage means may be provided with an arithmetic expression registration unit for registering and storing the input arithmetic expression. This is convenient because it is possible to freely create and register an arithmetic expression in order to set a determination condition according to the purpose. In this case, a plurality of arithmetic expressions can be stored in the arithmetic expression storage unit. An arithmetic expression selecting means for selecting a desired one from the stored arithmetic expressions is provided, and the arithmetic execution means may be configured to execute only an arithmetic operation related to the selected arithmetic expression. . This is more convenient because a plurality of arithmetic expressions describing the contents of various determination conditions are prepared and can be freely selected and used according to the purpose.

The CAD system of the present invention includes:
Drawing layer setting means for setting a plurality of drawing layers corresponding to a wiring layer to be formed in a substrate on a drawing screen;
Object input means for inputting an object, which is a drawing unit of a wiring pattern figure, to a drawing layer; and via input means for inputting a figure of a via connecting wiring portions between different wiring layers to a drawing layer corresponding to the wiring layers. Register a plurality of objects connected in a connected state on the same drawing layer or objects connected to each other via a via figure between different drawing layers as an integrated wiring net figure. And a wiring net figure registering means. In this case, the wiring pattern connection information generating means, based on the positional relationship between the registered wiring net figure and the connection determination target area,
Information on the connection state between the wiring net figure and the current-carrying connection area is generated.

In the above arrangement, the wiring pattern graphic is input in units of objects, and the objects are integrated by connecting the objects on the same layer or connecting the objects between the layers via the vias, and collectively integrate the objects. Registered as a wiring net figure of
It is determined whether or not the wiring net figure is connected to a connection determination target area that is set including a current-carrying connection area representing a metallization layer for current-carrying. That is, since objects connected to each other, that is, a wiring net figure, mean a wiring net connected without disconnection, it is only necessary to determine a connection relationship between this and a current-carrying connection area representing, for example, a current-carrying metallization layer. Checks such as missing plating lines can be easily and reliably performed.

[0015]

Embodiments of the present invention will be described below with reference to the embodiments shown in the drawings. FIG. 2 is a CAD system 1 (hereinafter simply referred to as CAD) for designing an electronic circuit board according to the present invention.
FIG. 1 is a block diagram illustrating an overall configuration of an embodiment (also referred to as a system). The CAD system 1 includes a computer main body 12 including an I / O port 2 and a CPU 3, a ROM 4, a RAM 5, and the like connected to the I / O port 2. Input means such as a keyboard 6 or a mouse 7 as peripheral devices, and a CD
A computer system to which a recording medium reading means such as a ROM drive 8 or a floppy disk drive 9, a hard disk drive (hereinafter referred to as an HDD) 10, a monitor 13 connected via a monitor control unit 11, a printer 14 and the like are connected , The whole is built.

The CPU 3 is mainly composed of area setting means, wiring pattern connection information generating means, element area setting means, arithmetic expression reading means, pattern set generating means, arithmetic execution means, arithmetic expression input means, and the like. . Also, a drawing screen display unit, a wiring pattern graphic input unit, a wiring pattern connection information output unit, an element area setting data storage unit, an operation expression storage unit, an operation program module storage unit, an operation expression input unit, an operation expression registration unit, an operation expression It also functions as a control entity such as a selection unit. Keyboard 6 or mouse 7
It is a main component of the wiring pattern graphic input means, the arithmetic expression input means, and the arithmetic expression selection means. HDD 10 and RAM
5 is an element area setting data storage means, an arithmetic expression storage means,
It is an essential part of the operation program module storage unit and the operation expression registration unit. The monitor 13 functions as a drawing screen display unit, a wiring pattern connection information output unit, and the like. The printer 14 functions as a wiring pattern connection information output unit and the like, in addition to a drawing output unit that prints out a design drawing of an electronic circuit board on which drawing has been completed.

The HDD 10 has an operating system program (hereinafter referred to as OS) 61 and an application program (hereinafter referred to as application) 6.
2 is stored. Application 62 uses CAD
This is a basic program for realizing the functions of the system 1 and operates on the OS 61. This is, for example, C
It is stored in the D-ROM 20 or the like in a computer-readable state, and is installed using, for example, a dedicated installer program. The HDD 10 stores a data file 63 of the created drawing. On the other hand, the work memory 5 of the OS 61 is stored in the RAM 5.
1 and an application work memory 52 are respectively formed.

As shown in FIG. 3, the application program 62 includes a control program 71, a drawing tool program 72, a check language system program 73, arithmetic expression data 74, element area setting data 75, a display / output program 76, and the like. I have. Among them, the control program 71 is a program for performing basic processing for causing a computer to function as the CAD system 1. Other programs complement the functions of the control program 71, and their roles will be described later. The ROM 4 stores various basic programs for hardware control of the computer system. When the application program 62 is started, the control program 71 is stored in the control program resident memory 52a formed in the application work memory 52, the drawing tool program 72 is stored in the drawing tool resident memory 52b, and the check language system program 73 is stored in the same manner. Check language system resident memory 5
At 2c, the display / output program 76 is also loaded into the display / output program resident memory 52d. These resident memories function as work areas for the corresponding programs. The operation expression data 74 is stored in the operation expression memory 5.
2e.

The application work memory 5
2, a drawing data memory 52f for storing drawing data, which is image data of a drawing being drawn, is formed. Element region setting data 75 for drawing an element region described later includes the element region setting data. The data is loaded into the data memory 52g. Furthermore, a wiring net data registration memory 52i is formed in the RAM 5. FIG. 5 shows the details, which will be described later in detail.

As shown in FIG. 4, the check language system program 73 includes a sum operation module 73a, a difference operation module 73b, a product operation module 73c, a negation operation module 73d, and a diagonally connected net detection module 73e.

Hereinafter, the operation of the CAD system 1 will be described in detail. The application program 62 of FIG.
Is activated, the control program 71 displays a drawing screen 40 on the monitor 13 (FIG. 2) as shown in FIG. The application program 62 according to the present embodiment is constructed as draw-based graphic software in the same manner as a known CAD system, and is a wiring pattern which is a graphic of a wiring portion or a portion to be plated on the drawing screen 40 by operating the mouse 7. The drawing operation is performed while inputting the figures in units of objects. In this embodiment, when the drawing screen 40 for a new drawing is started up, the drawing screen 40 includes the outline of the main surface of the board to be designed and drawn based on the display data separately stored in the HDD 10 or the like. A corresponding quadrilateral reference area 51 and a figure of a portion to be plated formed on the substrate surface, for example, a figure 53 of a specific pin pad and a figure 55 of a bonding pad are displayed as default object figures. . In this case, a default object data storage unit that stores default object data in association with a product number is provided in, for example, the HDD 10 and the product number is input by using the keyboard 6 (or clicking a soft button on the screen with the mouse 7). It is convenient if the default object data to be read is read out and displayed on the drawing screen.

Here, the substrate to be designed is a package substrate or the like in which a plurality of wiring layers are stacked via an insulating layer. By the operation of the control program 71, a plurality of drawing layers corresponding to the wiring layers to be formed are displayed on the drawing screen 4.
Set to 0. These drawing layers (hereinafter, also simply referred to as layers) cannot be visually discriminated because they are overlapped in FIG. Although the graphics written in each layer are superimposed on the drawing screen 40, other graphics may be displayed by displaying only the graphics on a specific layer, or by changing the color, brightness, shading, and filling pattern. It is possible to make the display state different from the graphic on the layer.

FIG. 6 is a flowchart showing the flow of the drawing process. First, in S1, a layer in which an object is to be written is selected. This layer selection can be performed by, for example, clicking a soft button (not shown) for layer selection displayed on the screen with the mouse 7 (FIG. 2). The objects that can be input as graphics are the above-described objects and via graphics for connecting objects between different layers, and in S2 and S8, which of them is selected is determined by command input. This command input can also be performed by mouse clicking of a soft button (not shown) for selecting an object input or a via input.

When the object input is selected, the process proceeds from S2 to S3, and the object is drawn. When drawing an object, a drawing tool program 72 (FIG. 3) is prepared for each type of object to be drawn, such as wiring drawing and pad drawing, similarly to known CAD system software. The drawing tool can also be selected by a mouse click on a drawing tool selection button (not shown) formed as a soft button on the screen. Then, when a desired drawing tool is selected, as shown in FIG. 10B, the pointer P indicating the drawing position is moved by mouse operation, and the mouse is clicked or dragged (by moving the mouse while holding down the mouse button). ) Draw objects while combining operations such as). The figure shows a state in which the graphic of the wiring section connecting the graphic 53 of each pin pad and the graphic of the bonding pad 55 has been drawn as an object.

As shown in FIG. 12B, every time one object is drawn, the object description data, which is its graphic data, includes object specifying data (eg, an object code) and layer specifying data (eg, a layer number). The drawing data memory 5 of FIG.
It is stored in 2g. The object description data is, for example, as shown in FIG.
Vector data, function formula data or coordinates of specific reference points and dimensions such as radius and length for defining the shape, size and drawing position of OB12, OB13, etc. on a coordinate plane set on the screen 40 Expressed as a set of prescribed data.
For example, the object OB11 has a reference point A11 (x0, y
A11 (x1, y1), A11 (x2, y2), A11 while circling in a predetermined direction (for example, clockwise) starting from 0).
When the outline of the object is drawn by connecting vectors in the order of (x3, y3) and A11 (x0, y0),
It is represented as a data set of the coordinates of the end point position of each vector. The same applies to the object OB12. A circular object OB13 representing a pad or the like is represented as a data set of the center coordinates C13 and the radius r13. Although not shown, for example, a figure of a wiring portion having a constant width can be represented as a data set of the coordinates of the starting position and the ending position and the line width. In FIG. 12, all three objects OB11, OB12, and OB13 are drawn on the same layer (No. 1).

On the other hand, if the via input is selected in FIG. 6, the flow advances to S9 to execute via input processing. FIG.
As shown in (a), a via V is formed in a wiring portion W of a different wiring layer.
In this embodiment, the input of the graphic of the via V is performed by, for example, positioning the pointer on the screen at a position where the user wants to input the via, and ending the same as the via starting point layer. This can be done by designating a layer. The data of this via figure is shown in FIG.
As shown in FIG. 3 (b), the drawing data memory 52f stores the via position data and the layer specifying information of the layer serving as the via start point and the end point in association with the via specifying data (for example, via code). You.

Returning to FIG. 6, when the object is drawn, the process proceeds to S4, and as shown in FIG. 14A, the input object OB12 partially overlaps (that is, is connected to) the input object OB12 in the same layer. It is determined whether or not the input object OB11 exists. If No, the process further advances to S5, and as shown in FIG. 15, it is determined whether or not another object OB31 is connected by a connection between different layers via the via VA11. If this is also No, the object OB12 is used as a wiring net figure.
For example, only the object specifying information is added to the wiring net data registration memory 52i of FIG. 3 with the net specifying information (for example, the net number), written as net data, and registered.

In S4 or S5 of FIG.
In the case of es, the process proceeds to step S7, in which the object to be connected to the object is incorporated into the registered wiring net figure to which the object belongs, that is, the object specification data of the newly drawn object is stored in the wiring net data registration memory 52i. Processing to be added to the net data to be performed. In the case of connection using a via, the via specifying data is also added to the net specifying information. In this way, as shown in FIG. 5, each net specifying information net1, net2,... And the specific data OB11, OB of the object belonging to the wiring net are stored in the wiring net data registration memory 52i.
12, ‥‥ or via specific data VA11, VA12, ‥
ネ ッ ト and the net data associated with each other are stored.

On the other hand, as shown in FIG. 14B, when objects overlapping between different layers occur, the object specifying data is not added to the net data at the overlapping destination. However, in S10 of FIG. 6, when wiring net figures connected to each other by the newly input via figure occur, the process proceeds to S11, and the net data of these wiring net figures are integrated (merged).
Then, a process of re-registering it as net data of one wiring net figure is performed. In this case, as the net specifying information, one corresponding to one of the wiring net figures before integration may be left, and the other may be deleted to be treated as a missing number. Net specifying information may be added.

When the drawing operation is terminated after repeating the drawing input of the input of the object or the via as described above,
Proceeding from S12 to S13, the graphic data stored in the drawing data memory 52g, that is, the drawing data is
A file name is given together with the net data in the wiring net data registration memory 52i, and the file name is written and stored in the drawing data file 63 of the HDD 10 (FIG. 2). In the example shown in FIG. 11, thirteen wiring net figures N1 to N13 are formed in the created drawing.

The created drawing can be printed out from the printer 14 based on the drawing data.

FIG. 7 is a flowchart showing the flow of the setting and checking processing of the element area. First, S101
Then, the element area is set on the drawing screen. The setting of the element region may be performed in the middle of drawing or after all drawing is completed. In FIG. 11, four rectangles representing energization metallization layers on the side surfaces of the substrate are shown, corresponding to each side of the reference region 51 representing the outline of the main surface of the substrate, in a manner in which the substrate to be designed is expanded and displayed. The current-carrying connection regions T, L, B, and R are set as element regions, and figures representing those regions are displayed on the screen. The setting of the element area may be performed using standard element area setting data prepared in advance (for example, data incorporated in the application program 62 as shown in FIG. 3), or the operator may perform drawing. You may make it perform drawing on a screen using a tool. In either case, the element area setting data described in the same format as the graphic data of the object can be used. As shown in FIG. 3, the element area setting data is a part of the drawing data, and is stored in the element area setting data memory 52g formed in the drawing data memory 52f as an element area name (element area specifying data). Is stored in a form associated with.

In FIG. 7, the process proceeds to S102, where the type of check to be performed is selected. This is, for example, FIG.
A check type selection window 41 as shown in FIG. In the window 41, an executable check name, an arithmetic expression for giving the content of the check, and a check selection button 42 for selecting whether or not to execute the check are formed. In response to this, the application 6 of the HDD 10
In the storage area No. 2, as shown in FIG.
4 is stored and loaded into the arithmetic expression memory 52e of the work memory 52 of the RAM. FIG.
As shown in FIG. 6 (a), in the arithmetic expression data 74, each arithmetic expression is stored in a form associated with a check name (arithmetic expression specifying data), and is accompanied by an execution flag. Check selection button 42 in window 41
Is turned on / off by mouse click, and accordingly, the corresponding execution flag is turned on / off (for example, “1” is on and “0” is off). I have. Then, only the arithmetic expression for which the execution flag is ON is executed (FIG. 7: S103).

For example, as shown in FIG. 11, a check execution button 43 is formed in the drawing screen 40, for example, so that the check operation can be immediately shifted from the drawing work.
It is convenient to check this by clicking the mouse. Thus, the process proceeds from S104 to S105 in FIG. If the user wants to change the contents of the check, the process returns from S104 to S102 via S108, and selects the check type again.

FIG. 8 is a flowchart showing details of the check process. Hereinafter, the principle of the check method using the arithmetic expression will be briefly described. FIG. 17 is a somewhat simplified drawing of an example of a drawing drawn on the drawing screen, and four element regions (electrically connected regions) T, L, B, and R are provided in contact with each side of the reference region 51. Are formed. It is also assumed that seven wiring net figures a to g are registered. Whether or not these wiring net figures are connected to a certain element region is determined in exactly the same way as in the case of performing connection determination between objects in the drawing process (FIG. 6) by regarding each element region as an object. be able to. When a certain element area is specified, a set of connection nets to the element area is obtained by searching all the wiring net figures connected to the element area based on the above-described determination processing. The search is performed using the check search / determination memory 52h of FIG. If the connection destination element region name (element region identification information) is associated with the set of wiring net figures obtained in this way, it can be considered that the element region name represents one set variable.
Hereinafter, this is called a net set variable.

In the case of FIG. 17, each of the element regions T, L, B,
The following four set variables can be defined corresponding to R: T = {b, a}, L = {a, f}, B = {e, d}, R = {d, c} (1) Also, a wiring net not connected to any of the set element regions The figure is g, and a set composed of all registered wiring net figures, that is, a mother set G can be considered.
This can be expressed as follows (however, G does not represent a specific element area). G = {a, b, c, d, e, f, g} (2) As can be seen from this, the wiring net figure g is a wiring net that does not conduct to any conductive metallization layer, This represents a wiring net with missing lines, and can be regarded as a wiring net figure not connected to any of the element regions T, L, B, and R in the drawing. When a set of such nets with a missing plating line is Z, this can be expressed as follows by using a general set algebraic symbol (where "'" is a complement set ( Negation operator). Z = (T∪L∪B∪R) ′ ‥‥ (3) Further, a difference operation for obtaining a difference set between the set A and the set B is defined, for example, as follows (however, the same result is obtained) If so, the operation content is not limited to this.) AB≡ (A∪B) ∩B '‥‥ (4)

Based on the above, the meaning and description method of the arithmetic expression used in this embodiment will be described. First, this arithmetic expression is an arithmetic expression of a set algebra applied between the above-mentioned net set variables (the set elements use wiring net figure specifying information in processing). In this embodiment, operations in general set algebra are described by the following reverse Polish notation, that is, a notation in which an operator is placed after an operation number. A∪B⇔AB | (∪⇔ |) ‥‥ (5) A∩B⇔AB & (∩⇔ &) ‥‥ (6) AB⇔AB ＾ (-⇔ ＾) ‥‥ (7) A'⇔ A! ('⇔!) ‥‥ (8)

In addition, in the set algebra, the union rule holds for the sum operation and the product operation. In this notation, it can be expressed as follows. (A∪B) ∪C = A∪ (B∪C) ⇔AB│C│ = ABC││ ‥‥ (9) (A∩B) ∩C = A∩ (B∩C) ⇔AB & C & = ABC && ‥‥ (10) If this is used, for example, it is understood that the same result can be obtained by expressing the expression (3) by any of the following. Z = TL | B | R |! ‥‥ (11) Z = TLB | R ||! ‥‥ (12) Z = TLBR ｜｜｜! ‥‥(13)

Next, a program for reading the stored arithmetic expression, analyzing the contents and executing the arithmetic is a check language system program 73 shown in FIG.
The program 73 includes program modules 73a to 73d for performing a sum operation, a product operation, a difference operation, and a negation operation of the set when the set of the wiring net figure specifying information is given. Further, a module 73e for detecting a diagonally connected net described later is also provided. It also controls the input of arithmetic expressions. The input of the arithmetic expression can be performed using, for example, the keyboard 6 (FIG. 2) or the like, and is stored as the arithmetic expression data 74 (FIG. 3).

As the arithmetic expression execution processing by the check language system program 73, for example, the following method can be adopted. First, the check search / judgment memory 52
In h (FIG. 3), a memory area having a structure as shown in FIG. 19 is set. This is because a plurality of input memories IM1, IM
2, IM3,..., An operation result memory RM1 for storing the operation result, and an operator memory OM for storing the operator. Hereinafter, the flow of processing will be described with reference to the flowchart of FIG.

First, in step S201, an arithmetic expression designated to be executed is read. Although the arithmetic expression is described by a net set variable and an operator, hereinafter, when these are collectively referred to as a syntax element. First, since the arithmetic expression uses the above-mentioned reverse Polish notation, the syntax element at the head is always a net set variable (that is, an element area name). In S202, this is read first, and the process proceeds to a process of searching for a net connected to the element area specified by the element area name (net search processing) (S203).

FIG. 9 shows the details of the net search process. First, an element area corresponding to the element area name read in S301 is specified, and it is checked whether there is an object connected to the element area (S305). If there is an object to be connected, all the net specifying information of the wiring net figure to which the object belongs is extracted (S3).
06), input memories IM1, IM2, IM3 in FIG.
Is stored in the first one (in this case, IM1). That is, what is stored in the input memory IM1 is a set of net specifying information belonging to the net set variable indicated by the element region name.

On the other hand, in the arithmetic expression, an auxiliary operator (hereinafter, referred to as a diagonal connection operator) for detecting a diagonally connected net can be attached to the net set variable. This diagonal connection operator is represented by “で は” in the notation of this embodiment, and is placed before the target operator. For example, a set of wiring net figures obliquely connected to the element region A is represented by “〜A”. If the diagonal connection operator is detected in step S304, the flow advances to step S307 to check whether there is an object such as a wiring diagonally connected in the corresponding element area. Extract the net specifying information of the wiring net figure to which it belongs. For example, as shown in FIG.
In the case of an object of a wiring portion specified by specifying the following, a reference vector B0B1 set in parallel with an edge (in this case, a side portion) corresponding to an element region of the reference region 51 is set, and a vector K1K2 is set. And a scalar product of the reference vector B0 and B1. If the result is zero (or within a certain numerical range centered on zero), it is determined that the connection is normal, otherwise the connection is diagonal.

Returning to FIG. 8, the process proceeds to S204, and if the next syntax element is a net set variable, the process proceeds to S206.
The variable is read and the same net search processing is performed (S
206, S207). The set of the generated net specifying information is stored in the input memory IM1, IM2, IM3} in the form of leading justification in the subsequent form if there is a memory in which the set (or operator) is stored first. . On the other hand, if the read syntax element is neither a net set variable nor an operator (for example, if it is an undefined code), the process proceeds to S211 to notify an error.

If the read syntax element is an operator, it is stored in the operator memory OM (FIG. 19), and the flow advances to S212. If the operator is a binary operator such as a sum (|), a difference (＾), or a product (&), the operator is stored in the last two of the input memories IM1, IM2, IM3}. A set operation of the contents indicated by the stored operator is performed on the set of the specified net specifying information, and the set of results is stored in the operation result memory RM1 (S212).
On the other hand, when the operator is a unary operator such as negation (!), The stored operation is performed on the set of net specifying information stored in the last one of the input memories IM1, IM2, IM3}. The set operation of the contents indicated by the child is performed, and the set of results is stored in the operation result memory RM1 (S212). In any case, when the operation is completed, the set of operation-specified net specifying information is cleared from the input memory, and instead, the set of operation results is written with justification (S213).

If the next syntax element remains in S208, the process returns to S204 and the same processing is repeated until the processing for all the syntax elements is completed. When the processing for all syntax elements is completed (S20
9) If an uncalculated set (variable) remains in the input memory, it means that the calculation was not performed correctly, and the process proceeds to S211 to notify an error. On the other hand, if there is no unprocessed set (variable), a set indicating the final calculation result should be stored in the calculation result memory RM1, and this is output as a check result (S210).

In the arithmetic expression described in the reverse Polish notation, the operation order is determined only by the position of the operator without using parentheses as in ordinary algebraic notation, so that the intermediate operation result is not saved on the way. Syntax elements can be sequentially processed in order from the top. As a result, the structure of the operation memory is simplified, and the processing speed is improved. FIG. 21 shows that A = {a, b, c}, B = {b, c, d}, C
AB & C & and ABC when = {c, d, e}
It is an operation example of &&. In the case of AB & C &, first, as shown in (a), A and B are stored in IM1 and IM2, the first & is stored in OM, AB & calculation is performed, and the calculation result {b, c} (= R) Is stored in RM1. Next, (b)
As shown in the figure, IM1 and IM2 are cleared, and the calculation result R
= {B, c} is stored in IM1. Then, C is stored in IM2, the second & is stored in OM, and the calculation of RC & is performed. The result is {c}.

On the other hand, in the case of ABC &&, A, B and C are stored in IM1, IM2 and IM3 as shown in FIG.
Store the first & in the OM. In this case, the & operation on the last two variables, that is, the BC & operation, is performed first, and the operation result {c, d} (= R) is stored in RM1. next,
As shown in (b), the operated IM2 and IM3 are cleared, and the operation result R = {c, d} is stored in IM2 with the left justified because the unoperated A remains in IM1. . Then, the second & is stored in the OM, and the calculation of AR & is performed. The result is the same {c} as before. That is, AB
& C & = ABC &&, which indicates that the operation according to the associative law is possible.

FIG. 22 is a view for explaining the above-mentioned (13) (Z = TL) in the drawing of FIG.
BR ｜｜｜! The following shows the contents of the arithmetic processing when the arithmetic expression represented by () is executed. According to this, the calculations are performed in the following order. U1 = BR | = {c, d, e} (14) U2 = LU1 | = {a, c, d, e, f} (15) U3 = TU2 | = {a, b, c, d, e, f｝ ‥‥ (16) Z = U3! = {G} (17) (note that the mother code is G = {a, b, c, d, e, f, g}). It can be seen that the correct result is obtained.

Next, one pair of energizing metallization layers is insulated from the other pair, and the energizing metallization layers belonging to the same pair are electrically connected by a wiring net extending between them. That is, whether or not the diagonal connection state is realized can be easily checked by combining some of the above arithmetic expressions. For example, in FIG. 17, a pair of energized connection regions T, L (first connection region pair) and B,
R (the second connection area pair) is connected by a wiring net figure (a (the first diagonal connection net figure) in the former, and d (the second diagonal connection net figure) in the latter). Consider the case where L, B and R, T are not connected (ie, there is no complementary diagonal connection net).

The first check can be performed by the operation of Q1 = BL | TR | & ‥‥ (17). FIG. 23 shows an example of the calculation. According to this, the calculations are performed in the following order. V1 = BL | = {a, d, e, f} (18) V2 = RT | = {a, b, c, d} (19) Q = V1V2 & = {a, d} ( 20) That is, it turns out that the correct result was obtained. In order to check, it is necessary to individually indicate that L, B and R, T do not have complementary diagonal connection nets. Therefore, it is sufficient to check that the results of the other two arithmetic expressions: Q2 = BL & ‥‥ (21) Q3 = TR & ‥‥ (22) are all empty sets.

It is determined whether or not a state in which the metallization layers for energization of all adjacent sides are electrically connected to each other by wiring nets extending over them, that is, a four-side connection state, is realized. In the case of 17, the next 4
Two arithmetic expressions: P1 = TL & ‥‥ (23) P2 = LB & ‥‥ (24) P3 = BR & ‥‥ (25) P4 = RT & ‥‥ (26) Good. For example, in FIG. 17, when the new wiring net figures h and i are considered, the results of the above four equations are respectively
It is normal if {a}, {i}, {d}, {h}, and if any one becomes an empty set, it becomes abnormal. Note that this arithmetic expression can also be used for checking the diagonal connection state. That is, when FIG. 17 is returned to a state in which the wiring net figures h and i do not exist again, if the results of the above equation 4 are {a}, ｛｝, {d} and そ れ ぞ れ, respectively, it is normal. It is.

To check that there is no diagonal connection net, the result of the following equation: W =＝ T〜L〜B〜R│││ (27) becomes an empty set You just need to make sure. In FIG. 17, if there is a wiring net figure (for example, k) diagonally connected to any of the element regions T to R,
All of them are extracted by the above operation.

Hereinafter, the operation result as described above, that is,
A method of outputting a check result will be described. This display /
The output control is performed by the display control program 76 shown in FIG. For example, in FIG. 24A, on the drawing screen,
The wiring net figure N6 extracted as a missing plating line is
This is an example in which the color is displayed by making it different from the others. In this case, the wiring net name can be displayed in a separate check result display window 45 provided. On the other hand, in the example shown in FIG. 24B, a wiring net name display area 46 is formed near the extracted wiring net figure N6, and the wiring net name is displayed here. In any case, the operator can see the result and immediately start the drawing correction work for eliminating the plating line missing state. Also, as shown in FIG.
A check result display screen 47 may be displayed separately from the drawing screen, and a wiring net name as a check result may be displayed here.

On the other hand, in checking the diagonal connection state,
If a diagonally connected net figure that should exist is not detected, an element area (areas B and R in FIG. 26) in which the existence of the diagonally connected net figure is required is notified by, for example, changing the color. Can be.

The element region can be set in various forms other than the energized connection region as shown in FIG. In FIG. 27, when the substrate is finished as a product, the reference region 51 of the substrate is set to correspond to the outline after the cutting, on the assumption that the edge on which the metallization layer for energization is formed is cut. A boundary line 51a corresponding to the outer shape line before cutting is set outside the region, and a region located between the reference region 51 and the boundary line 51a is set as an element region J. Further, a limit line 51b is further set outside the boundary line 51a.
The region excluding the energization connection regions T, L, B, and R among the regions sandwiched between the line 1b and the boundary 51a is set as the element region H. FIG. 27 also shows examples of execution results of some arithmetic expressions when the wiring net figures a to e are formed.

[Brief description of the drawings]

FIG. 1 is a partial perspective view showing an example of an electronic circuit board.

FIG. 2 is a block diagram showing an electrical configuration of a CAD system for designing an electronic circuit board according to the present invention.

FIG. 3 is a map showing contents of the application program and the application work memory.

FIG. 4 is a map showing the contents of a check language system program.

FIG. 5 is a map showing the contents of a wiring net data registration memory.

FIG. 6 is a flowchart illustrating a flow of a drawing process.

FIG. 7 is a flowchart showing the flow of an element area setting / checking process.

FIG. 8 is a flowchart showing details of the check processing.

FIG. 9 is a flowchart illustrating a flow of a net search process.

FIG. 10 is an explanatory diagram of an operation process on a drawing screen in the electronic circuit board designing CAD system of the present invention.

FIG. 11 is an explanatory view following FIG. 10;

FIG. 12 is a conceptual diagram of an object and its graphic data.

FIG. 13 is a conceptual diagram of a via graphic and its graphic data.

FIG. 14 is an explanatory diagram of an overlapping connection state of objects.

FIG. 15 is an explanatory diagram of a via connection state of an object.

FIG. 16 is an explanatory diagram of operation expression data and a check type selection window.

FIG. 17 is a view for explaining the concept of a set variable having a wiring net figure as an element.

FIG. 18 is an explanatory diagram showing an example of an operator and an arithmetic expression using the operator.

FIG. 19 is an explanatory diagram showing the contents of a check search / judgment memory.

FIG. 20 is an explanatory diagram showing a determination calculation method of a diagonally connected net.

FIG. 21 is an explanatory diagram showing that the associative law of the product operation is satisfied.

FIG. 22 is an explanatory diagram showing a calculation example of a plating line omission check.

FIG. 23 is an explanatory diagram showing a calculation example of a diagonal connection check.

FIG. 24 is an explanatory diagram showing some output examples of check results.

FIG. 25 is an explanatory diagram showing another output example.

FIG. 26 is an explanatory diagram showing still another output example.

FIG. 27 is an explanatory diagram showing another example of setting an element area.

[Explanation of symbols]

Reference Signs List 1 CAD system for electronic circuit board design 3 CPU (area setting means, wiring pattern connection information generating means, element area setting means, arithmetic expression reading means, pattern set generating means, arithmetic execution means, arithmetic expression input means) 5 RAM (net Specific information storage means, net image data storage means, element area setting data storage means, arithmetic expression storage means, arithmetic program module storage section, arithmetic expression registration section) 6 keyboard 7 mouse (wiring pattern graphic input means, arithmetic expression input means, Arithmetic expression selection means) 8 CD-ROM drive 10 Hard disk drive (element area setting data storage means, arithmetic expression storage means, arithmetic program module storage section, arithmetic expression registration section) 12 Computer body 13 Monitor (drawing screen display means, wiring pattern) Connection information output means) 14 Printer (wiring pattern) Connection information output means) 20 CD-ROM (recording medium)

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tomoshige Ono 14-18, Takatsuji-cho, Mizuho-ku, Nagoya-shi, Aichi Prefecture Inside Japan Special Ceramics Co., Ltd. 25-1 chome Fuku term in Zuken Co., Ltd. (reference) 2G014 AA02 AA13 AB59 AC09 AC15 5B046 AA08 BA04 JA01

Claims (6)

[Claims] A plurality of wiring layers are stacked via an insulating layer, and a portion to be plated through which a wiring portion formed in the wiring layer conducts is formed on the surface of the substrate while being exposed.
A CAD system for designing an electronic circuit board in which a metallization layer for conduction connected to the wiring portion is formed on a side surface, wherein a wiring pattern graphic which is a graphic of a wiring portion or a portion to be plated is input on a drawing screen. A wiring pattern figure input means, a reference area corresponding to the outer shape of the main surface of the substrate, and a connection determination target area formed outside the reference area so as to include an energization connection area corresponding to the energization metallization layer Area setting means for setting a plurality of element areas including one or a plurality of energized connection areas for the connection determination target area; and each of the element areas A pattern set variable setting means for setting a variable (hereinafter, referred to as a pattern set variable) representing a set of wiring pattern graphics connected to the element region, Arithmetic expression storage means for storing an arithmetic expression described using a combined variable and one or more types of operators combined with the combined variables; An operation program module storage unit that stores an operation program module for executing a set operation content defined in advance, an operation expression reading unit that reads the operation expression from the operation expression storage unit, A pattern set variable included in an arithmetic expression is detected, and among the wiring pattern figures, those connected to an element region corresponding to the pattern set variable are extracted, and a wiring pattern figure corresponding to the pattern set variable is extracted. A pattern set generating means for generating a set of pattern patterns, and a wiring pattern graphic indicated by each pattern set variable according to the description content of the arithmetic expression. Operation execution means for executing a set operation defined by each operator using a corresponding operation program module, and a connection state between the wiring pattern graphic and the energized connection area based on the operation result. A wiring pattern connection information generating means for generating information regarding the wiring pattern connection information output means for outputting the generated wiring pattern connection information. 2. The operator according to claim 1, further comprising: an operator for a sum operation for obtaining a union of a set of two wiring pattern figures; an operator for a difference operation for obtaining a difference set; and an operation for a product operation for obtaining a common set. 2. The electronic circuit board according to claim 1, further comprising at least one of a child and an operator of a negation operation for obtaining a negative set of a set of certain wiring pattern figures with respect to a mother set including all registered wiring pattern figures. CAD for design
system. 3. An arithmetic expression input means for inputting the arithmetic expression is provided, and the arithmetic expression storage means registers the input arithmetic expression.
The CAD system for designing an electronic circuit board according to claim 1, further comprising an arithmetic expression registration unit that stores the arithmetic expression. 4. An arithmetic expression selection means for selecting a desired one from the stored arithmetic expressions, wherein a plurality of the arithmetic expressions can be stored in the arithmetic expression storage unit. 4. The CAD system for designing an electronic circuit board according to claim 1, wherein the execution means executes only an operation related to the selected operation expression. 5. The wiring pattern connection information generating means, as the arithmetic expression in the arithmetic expression storage unit, connects pattern set variables corresponding to all the energized connection areas set in series by a sum operation, and adds the result to the result. The information on the content of performing the negation operation is stored, and based on the operation result based on the operation expression of the operation execution means, information on the existence of the wiring pattern graphic not connected to any of the energized connection areas is stored in the wiring. The CAD system for designing an electronic circuit board according to claim 1, wherein the CAD system is generated as pattern connection information. 6. A program for causing a computer to function as each means constituting the CAD system for designing an electronic circuit board according to claim 1, wherein the program is stored in a computer-readable state. recoding media.