JP2000269908A - Method and circuit for monitoring bus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a method and a circuit for monitoring a bus for a bit rearrangement processing circuit. SOLUTION: A high-speed interface circuit 10 converts received serial data 100 into parallel data 102 and generates a parity bit 104 of the parallel data 102. A receiver side STM frame synchronizing circuit 12 detects a frame synchronization pattern to check a pattern of a bit phase, generates bit rearrangement information 110 denoting the pattern, applies bit rearrangement processing with respect to the parallel data 102 on the basis of the pattern to generate parallel data 106 that are synchronized in terms of bytes. A receiver side STM descramble circuit 14 descrambles the parallel data 106 into the signal parallel data prior to bit rearrangement on the basis of the bit rearrangement information 110, checks parity by using parity bit 108 received from the high-speed interface circuit 10 via the receiver side STM frame synchronization circuit 12 and outputs a parity error alarm 114.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a path monitoring method and a path monitoring circuit for monitoring a pass path of a main signal in a device.

[0002]

2. Description of the Related Art In a data transmission device or the like, usually, a wiring pattern or the like in a device through which a main signal passes is monitored (path monitoring), and a failure is promptly dealt with. Conventionally, as one of such path monitoring methods, FTS (Filling Ti
me Slot) monitoring is known. In the FTS monitoring, a specific pattern is always inserted into an empty time slot of a main signal at a start point of a monitoring section, and the pattern is checked at an end point. In addition, parity check (Parity Check) and CRC (Cy
clic Redundancy Check) can be used for path monitoring.

[0003]

However, in the above-described monitoring method, when a circuit for executing a bit rearrangement process of parallel data is included in the apparatus, the specific pattern of the FTS is determined by the bit rearrangement process. And the result of the parity check operation changes, so that path monitoring cannot be performed, and there is a problem that a non-monitoring area exists in the device.

For example, SDH (Synchronous Digital Hi
In a circuit for terminating a transmission line of the erarchy type, the transmission side converts 8-bit parallel data to be transmitted into serial data by a parallel / serial conversion circuit and sends out the serial data to the transmission line, and the reception side receives serial data received from the transmission line. The data is converted into 8-bit parallel data by a serial / parallel conversion circuit and output. In this case, since the bit phase of the 8-bit parallel data output from the serial / parallel conversion circuit on the receiving side is completely arbitrary, if the byte synchronization is not achieved, the byte synchronization is performed by performing a bit rearrangement process. The data was converted to 8-bit parallel data.

Here, the bit phase indicates how many bits of the parallel data of interest deviate from the parallel data bit in a state where byte synchronization is established. FIG. 7 is an example of the bit phase of 8-bit parallel data. In FIG. 7, D0 [7: 0] (D0 [7] to D0 [0]) and D1 [7: 0] (D1
[7] to D1 [0]) are two preceding and succeeding 8-bit parallel data input to the parallel / serial conversion circuit on the transmission side. The parallel data D0 [7: 0] and D1 [7: 0] are converted into serial data by a parallel / serial conversion circuit, sent to the other party via a transmission line, and then received by the reception side serial / parallel conversion circuit. It is assumed that the data is converted into 8-bit parallel data (hereinafter referred to as reception-side parallel data).

When the bit phase of the parallel data on the receiving side is in a state where byte synchronization is established, the bit phase shown in FIG.
Corresponds to the pattern 7 shown in FIG. However, when the byte synchronization is not established, the bits of the parallel data on the receiving side are shifted backward by several bits, and the bit phase corresponds to one of the patterns 6 to 0 shown in FIG.
Here, pattern 6 to pattern 0 are such that each bit of the parallel data is shifted 1 bit, 2 bits, 3 bits, 4 bits, 5 bits, 6 bits, and 7 bits backward with respect to pattern 7. Is shown.

On the receiving side, a frame synchronization circuit is detected from the received parallel data by a frame synchronization circuit, and it is checked which of the pattern 7 to pattern 0 the bit phase of the frame synchronization pattern corresponds to. When the bit phase of the frame synchronization pattern corresponds to any one of patterns 6 to 0, the bits are arranged based on the corresponding pattern so that the parallel data on the receiving side becomes the parallel data in a byte-synchronized state. The replacement process is performed.

However, when the bit rearrangement process is performed on the parallel data on the receiving side as described above, the FTS pattern and the like inserted for path monitoring also change.
Path monitoring by FTS or the like becomes impossible, and there is a problem that a non-monitoring area exists in the device.

An object of the present invention is to solve such a problem of the prior art and to provide a path monitoring method and a path monitoring circuit capable of monitoring a path of a bit rearrangement processing circuit.

[0010]

According to the present invention, there is provided a path monitoring method for monitoring a signal path of an apparatus including bit rearranging means for rearranging bits of parallel data, the method comprising the steps of: A data error detection information generating step of generating data error detection information for detecting a data error of the parallel data before the bits are rearranged by the bit rearrangement unit, and the parallel data whose bits are rearranged by the bit rearrangement unit A bit phase detecting step of detecting the bit phase of the data, and, based on the bit phase detected in the bit phase detecting step, restoring the parallel data before bit rearrangement from the parallel data whose bits have been rearranged by the bit rearranging means. Parallel data restoration process, and data of the parallel data restored in the parallel data restoration process. Characterized in that it comprises a data error detection step of detecting based on data error in the data error detection information.

In this case, the bit phase of the frame synchronization pattern included in the parallel data is preferably used as the bit phase in the bit phase detecting step.

It is preferable to use a parity bit as the data error detection information in the data error detection information generation step.

According to the present invention, there is provided a monitoring circuit for monitoring a signal path of a device including a bit rearranging means for rearranging bits of parallel data, the circuit comprising a parallel circuit before the bits are rearranged by the bit rearranging means. Data error detection information generating means for generating data error detection information for detecting a data error of data; bit phase detection means for detecting a bit phase of parallel data whose bits have been rearranged by the bit rearrangement means; Based on the bit phase detected by the bit phase detecting means, a parallel data restoring means for restoring parallel data before bit rearrangement from the parallel data whose bits have been rearranged by the bit rearranging means, The data error of the restored parallel data is detected based on the data error detection information. Characterized in that it comprises a data error detecting means for.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an STM frame synchronization circuit to which a path monitoring method according to the present invention is applied. In this STM frame synchronization circuit, parallel data
The path of the receiving-side STM frame synchronization circuit 12 that rearranges the 102 bits and outputs the parallel data 106 is monitored by a parity check. This STM frame synchronization circuit forms a part of the termination processing circuit in the SDH transmission line.

In FIG. 1, serial data 100 (main signal) received from the outside is transmitted to a high-speed interface circuit (HIF).
) Entered in 10. The high-speed interface circuit 10 sequentially converts the received serial data 100 into 8-bit parallel data 102 according to a clock in the device. For example, S
In the TM-1 (Synchronous Transfer Module level 1) mode, serial data with a bit rate of 155.52 Mb / s is sequentially converted into 8-bit parallel data.

The high-speed interface circuit 10 generates information for detecting a data error in each parallel data 102, for example, a parity bit 104 according to a predetermined procedure. When data having the same content as the parallel data 102 is used as information for detecting a data error, the data error can be easily detected by collation. The output of the high-speed interface circuit 10 is connected to the receiving-side STM frame synchronization circuit (STMR_S
YNC) 12 connected. The parallel data 102 and the parity bit 104 are input to the receiving-side STM frame synchronization circuit 12 through different routes.

The receiving-side STM frame synchronization circuit 12 detects a frame synchronization pattern from the input parallel data 102 and performs processing for establishing or losing synchronization. In this embodiment, it is mainly checked whether the bit phase of the detected frame synchronization pattern corresponds to any one of the patterns 7 to 0 shown in FIG. A bit rearrangement process is performed so that the bit phase of the data 102 corresponds to the pattern 7 to generate byte-synchronized parallel data 106.

However, if the bit phase of the frame synchronization pattern corresponds to pattern 7, the parallel data 10
No bit reordering of 2 is performed. In this embodiment,
Although the frame synchronization pattern is used to detect the bit phase of the parallel data, when information that can detect the bit phase of the parallel data is included in the parallel data, that information may be used.

The receiving-side STM frame synchronization circuit 12
Bit rearrangement information 110 indicating a pattern corresponding to the bit phase of the detected frame synchronization pattern is generated. Further, a predetermined delay is given to the input parity bit 104, and a parity bit 108 having the same timing as the parallel data 106 is generated. The output of the receiving-side STM frame synchronization circuit 12 is the receiving-side STM descramble circuit (STMR_DSCR)
Connected to 14. The parallel data 106, the parity bit 108, and the bit rearrangement information 110 are input to the receiving-side STM descramble circuit 14 by different routes.

FIG. 2 is a block diagram showing an example of the above-mentioned receiving-side STM frame synchronization circuit 12. In FIG. 2, data latch registers (DLT1 [7: 0] to DLT5 [7: 0]) 20 to 28
Are, for example, D-type flip-flops that operate according to a clock in the device, and are connected in series. The output of each register is connected to a frame synchronization pattern detection circuit (FPTNDET) 30. Therefore, the parallel data 10 input from the high-speed interface circuit 10
2 is sequentially shifted by one clock by the data latch registers 20 to 28, and the five parallel data 120 to 128 are input to the frame synchronization pattern detection circuit 30 from the data latch registers 20 to 28 every clock.

In the STM-1 mode, for example, when two-stage backward protection is employed, the SOH (Section Over Head) of the frame is used.
6 bytes A1, A1, A1, A2, A2, inserted in the part
A2 (hereinafter A1 (1), A1 (2), A1 (3), A2 (1),
A2 (2), A2 (3)), 4 bytes of A1 (2), A1
(3) Frame synchronization is achieved by detecting A2 (1) and A2 (2) twice in succession at the same byte position. The frame synchronization detection circuit 30 receives the parallel data 120 to 12
8, the above-mentioned A1 (2), A1 (3), A2 (1), and A2 (2) are detected as frame synchronization patterns, and the bit phase of the frame synchronization pattern is set to any of patterns 7 to 0 in FIG. A check is made as to whether the bit pattern is applicable, and bit phase information 130 representing the pattern is generated. Here, the patterns of A1 and A2 are F6 and 28 (both in hexadecimal).

Specifically, the frame synchronization detection circuit 30
When byte synchronization is achieved, 4 bytes of parallel data 128-122 to 4 bytes of A1 (2), A1 (3)
, A2 (1), and A2 (2), the synchronization pattern can be detected. In this case, the frame sync pattern
The bit phases of A1 (2), A1 (3), A2 (1) and A2 (2) are shown in FIG.
Of pattern 7. However, when the byte synchronization is not established, the parallel data 120 to 128
Are shifted from the position where byte synchronization is established, so that the 5-byte parallel data 128 to 12
A1 (2), A1 (3), A2 (1) and A2 (2) of 4 bytes from 0 are detected.

For example, if the bits of the parallel data 120 to 128 are shifted one bit backward, the parallel data
Detecting four bytes of A1 (2), A1 (3), A2 (1), and A2 (2) of the frame synchronization pattern from the bits from the second bit of 128 to the first bit of the parallel data 120 Detects the frame synchronization pattern. This allows
It can be seen that the bit phase of the detected frame synchronization pattern is shifted one bit backward, and the bit phase is shown in FIG.
Of pattern 6.

The frame synchronization detection circuit 30 generates bit phase information 130 representing the bit phase pattern of the detected frame synchronization pattern. Specifically, when the bit phase corresponds to the pattern 7, 6, 5, 4, 3, 2, 1, 0 shown in FIG. 7, 80, 40, 20, 10, 08, 04, 02, 01 (any Is also generated in hexadecimal). In addition,
The bit phase information 130 is output only when a frame synchronization pattern is detected, and otherwise, 00 is output. The output of the frame synchronization detection circuit 30 is connected to a bit phase information holding register (FPTNDET_LT [7: 0]) 32, and the bit phase information 130 is input to the bit phase information holding register 32.

The bit phase information holding register 32 is, for example, a D-type flip-flop, and takes in the input bit phase information 130 and outputs it as bit phase information 132. The output of the bit phase information holding register 32 is connected to a bit rearrangement information holding register (OCTSEL [7: 0]) 34, and the bit phase information 132 is input to the bit rearrangement information holding register 34.

The bit rearrangement information holding register 34 is, for example, a D-type flip-flop having a hold function. The bit rearrangement information holding register 34 takes in and holds bit phase information 132 inputted when a predetermined condition is satisfied, and holds the held information. Is output as bit rearrangement information 134. Note that the output of the bit rearrangement information holding register 34 is 00 when the frame synchronization pattern is not detected. The output of the bit rearrangement information holding register 34 is connected to a bit rearrangement information output register (OCTSELO [7: 0]) 36 and a bit rearrangement circuit (OCTLINE) 38, and the bit rearrangement information 134 is a bit rearrangement information. It is input to the output register 36 and the bit rearrangement circuit 38.

The data latch registers 22 and 24
Are connected to a bit rearranging circuit 38, and the parallel data 122 and 124 are input to the bit rearranging circuit 38. When the bit rearrangement information 134 is input from the bit rearrangement information holding register 34, the bit rearrangement circuit 38 sequentially fetches the parallel data 122 and 124 and rearranges the bits based on the value indicated by the bit rearrangement information 134. To generate parallel data 136. In particular,
When the bit rearrangement information 134 indicates 80, the bit phase of the frame synchronization pattern corresponds to the pattern 7 in FIG. 7, and thus no bit shift occurs in the parallel data 122 and 124. In this case, the bit rearrangement circuit 38 outputs the input parallel data 124 as parallel data 136 without performing the bit rearrangement process.

However, for example, the bit rearrangement information 13
When 4 indicates 08, the bit phase of the frame synchronization pattern corresponds to pattern 3 in FIG.
Bits 2 and 124 are shifted 4 bits backward compared to the case where the byte synchronization is achieved (pattern 7). In this case, the bit rearrangement circuit 38 outputs the parallel data 124
The lower 4 bits of the parallel data 136 are taken out as the upper 4 bits of the parallel data 136, and the upper 4 bits of the parallel data 122 are taken out as the lower 4 bits of the parallel data 136, thereby generating byte-synchronized parallel data 136. Similarly, when the bit phase of the frame synchronization pattern is another pattern, the parallel data
Generate

The output of the bit rearrangement circuit 38 is connected to a data output register (DO [7: 0]) 40, and the parallel data 136 is input to the data output register 40. The data output register 40 is, for example, a D-type flip-flop. The data output register 40 receives the input parallel data 136 and outputs it as parallel data 106. This parallel data 106 is input to the receiving-side STM descramble circuit 14 in FIG.

The bit rearrangement information output register 36
Is, for example, a D-type flip-flop which takes in the input bit rearrangement information 134 and outputs this information as bit rearrangement information 110. The bit rearrangement information 110 is output when the first parallel data is output from the data output register 40 after the detection of the frame synchronization pattern. Bit sorting information
110 is input to the receiving-side STM descramble circuit 14 in FIG.

The parity bit shift registers 42 to 46
For example, it is a D-type flip-flop, which sequentially shifts the parity bit 104 input from the high-speed interface circuit 10 of FIG. 1 and delays it by three clocks, and outputs it as a parity bit 108 at the same timing as the corresponding parallel data 106. This parity bit 108 is input to the receiving-side STM descrambling circuit 14 in FIG.

Returning to FIG. 1, the receiving-side STM descramble circuit 14 mainly receives the scrambled data (excluding the first line of the SOH including the frame synchronization pattern) sent from the transmitting side. This is a circuit for performing descrambling processing. FIG. 3 is a block diagram showing an example of the parity check unit included in the receiving-side STM descramble circuit 14. This parity check unit 50
Parallel data output from STM frame synchronization circuit 12
106, and restores the parallel data before bit rearrangement processing is performed.
The parity check is performed using the parity bit 108 output from the
Monitor the main signal path at 12.

In FIG. 3, the parallel data 106 input from the receiving-side STM frame synchronization circuit 12 is output as parallel data 112 to the outside as it is, and a data delay register (DI_LT [7: 0]) 52 and a parity check circuit are provided. Entered in 56. The data delay register 52 is, for example, a D-type flip-flop, which delays the input parallel data 106 by one clock, and
Output as 150. The output of the data delay register 52 is connected to a parity check circuit 56, and the parallel data 150 is input to the parity check circuit 56.

The parity bit 108 and bit rearrangement information 110 input from the receiving-side STM frame synchronization circuit 12 are as follows:
These are input to a parity bit delay register 54 and a parity check circuit 56, respectively. Parity bit delay register
Numeral 54 denotes, for example, a D-type flip-flop, which takes in the parity bit 108, delays it by one clock, and outputs it as a parity bit 152. The parity bit delay register 54 is connected to the parity check circuit 56, and the parity bit 152 is input to the parity check circuit 56.

The parity check circuit 56 rearranges the bits of the parallel data 106 and 150 based on the bit rearrangement information 110, and converts the parallel data before the bit rearrangement process is performed by the receiving-side STM frame synchronization circuit 12. Restore. For example, when the bit rearrangement information 110 indicates 08, the bit phase of the parallel data before the bit rearrangement corresponds to the pattern 3 in FIG. Therefore, the lower 4 bits of the parallel data 150 are taken out and stored in the upper 4 bits of the restored parallel data.
The bits are taken out and set as the lower 4 bits of the restored parallel data, and the parallel data before bit rearrangement is restored.
However, when the bit rearrangement information 110 indicates 80, the bit phase of the parallel data before the bit rearrangement is
This corresponds to pattern 7 in FIG. In this case, the parity check circuit 56 uses the parallel data 150 as restored parallel data.

Next, the parity check circuit 56 performs a parity check on the restored parallel data using the parity bit 152. Then, if the check result matches a predetermined value, the parallel data 10
Since the contents of 2 and the restored parallel data are the same, it is determined that there is no failure in the main signal path in the STM frame synchronization circuit 12 on the data receiving side.

However, if the check result does not match the predetermined value, it is determined that a failure has occurred in the main signal path in the receiving side STM frame synchronization circuit 12, and a parity error occurrence signal 154 is generated. When parallel data having the same content as the parallel data 102 is used instead of the parity bit, the presence or absence of a data error can be detected by comparing the parallel data with the restored parallel data.

The output of the parity check circuit 56 is connected to a parity error alarm output register (ALM_PTY0) 58, and the parity error occurrence signal 154 is input to the parity error alarm output register (ALM_PTY0) 58. The parity error alarm output register 58 is, for example, a D-type flip-flop, takes in the input parity error occurrence signal 154, and outputs it as a parity error alarm 114 to the outside.

Next, the operation of the STM frame synchronization circuit shown in FIG. 1 will be described. The high-speed interface circuit 10 sequentially converts the received serial data 100 input from the outside into 8-bit parallel data 102 in accordance with a clock in the apparatus, and outputs this to the receiving-side STM frame synchronization circuit 12.
In addition, the high-speed interface circuit 10 generates a parity bit 104 for each of the generated parallel data 102 according to a predetermined procedure, and outputs the parity bit 104 to the receiving-side STM frame synchronization circuit 12 through a different route from the parallel data 102.

In the receiving side STM frame synchronization circuit 12, the parallel data 10 output from the high-speed interface circuit 10 is output.
2 and performs bit rearrangement processing to generate byte-synchronized parallel data 106,
Output to the STM descramble circuit 14. First, the operation of the receiving-side STM frame synchronization circuit 12 in a state where byte synchronization is established will be described. Fig. 4 shows the frame synchronization pattern (STM-1 mode) when byte synchronization is achieved.
6 is a timing chart showing the detection operation of FIG.

In FIG. 4, CLK is a clock, and each circuit in the apparatus operates according to the clock. Also,
The bit phase of the parallel data 102 is the pattern 7 in FIG.
And byte synchronization is established. Receiver
Parallel data 10 input to STM frame synchronization circuit 12
2 is sequentially delayed by one clock by the data latch registers 20 to 28, and the parallel data 120 to 128 are input from the data latch registers 20 to 28 to the frame synchronization pattern detection circuit 30 every clock. In addition, parallel data
122 and 124 are also input to the bit rearrangement circuit 38.

As shown in FIG. 4, the parallel data 10
2 as A1 (1), A1 (2), A1 (3), A2 (1), A2 (2), A2
When the parallel data 102 including (3) is sequentially input, when the data latch register 28 outputs A1 (2) as the parallel data 128, the data latch registers 26 to
A1 from 22 as parallel data 126 to 122 respectively
(3), A2 (1) and A2 (2) are output and input to the frame synchronization pattern detection circuit 30. The frame synchronization pattern detection circuit 30 detects frame synchronization patterns A1 (2), A1 (3), A2 (1) and A2 (2) from the parallel data 128 to 122.

Next, the frame synchronization pattern detection circuit 30
Then, it is checked which of the pattern 7 to pattern 0 shown in FIG. 7 the bit phase of the detected frame synchronization pattern corresponds to. In this case, for example, since all bits of A1 (2) are included in the parallel data 128 and there is no bit shift, the bit phase of the frame synchronization pattern corresponds to pattern 7. Therefore, the frame synchronization pattern detection circuit
At 30, bit phase information indicating 80 corresponding to pattern 7
130 is generated and output to the bit phase information holding register 32. Note that, for example, in the two-stage backward protection device, when the pattern of A1 (2), A1 (3), A2 (1), and A2 (2) is detected twice consecutively at the same byte position, frame synchronization is performed. It has been established.

The bit phase information holding register 32 outputs the bit phase information 130 to the bit rearrangement information holding register 34 as bit phase information 132. The bit rearrangement information holding register 34 holds 80 indicated by the bit phase information 132, and stores the bit rearrangement information 134 indicating the 80.
Is generated and output to the bit rearrangement information output register 36 and the bit rearrangement circuit 38. The bit rearrangement information holding register 34 holds the value 80 until it is determined that frame synchronization has been lost.

In the bit rearrangement circuit 38, when the bit rearrangement information 134 is given from the bit rearrangement information holding register 34, the parallel data 122 inputted from the data latch registers 22 and 24 are based on the value indicated by the information. ,
The bit rearrangement processing for 124 is started. But,
In this case, since the bit rearrangement information 134 indicates 80, the parallel data 12
4 is output to the data output register 40 as parallel data 136. Thereafter, the bit rearrangement circuit 38 converts the parallel data 124 into parallel data 136 during the period when the bit rearrangement information 134 indicates 80.
Output to 40.

The data output register 40 takes in the parallel data 136 output from the bit rearrangement circuit 38 and outputs it as parallel data 106 to the receiving-side STM descramble circuit 14. In FIG. 4, one clock after the bit rearrangement information 134 becomes 80, the data output circuit 40 outputs A2, J0, 0H7, and OH as the parallel data 106.
8, DA1,... Are sequentially output. The bit rearrangement information output register 36 takes in the bit rearrangement information 134 output from the bit rearrangement information holding register 34 and outputs it as the bit rearrangement information 110. This bit rearrangement information 110 is transmitted to the receiving side when A2 is first output from the data output register 40.
This is output to the STM descramble circuit 14.

Next, the operation of the receiving-side STM frame synchronization circuit 12 in a state where byte synchronization is not established will be described.
FIG. 5 is a timing chart showing an operation of detecting a frame synchronization pattern in a state where byte synchronization is not established. In FIG. 5, the bit phase of the parallel data 102 input from the high-speed interface circuit 10 is shifted backward by 4 bits, and the bit phase corresponds to the pattern 3 in FIG. For example, the lower 4 bits (D0 [3: 0]) of D0 [7: 0] input as parallel data 102 and D1
The upper 4 bits (D1 [7: 4]) of [7: 0] correspond to parallel data when there is no bit shift.

In this case, A1 (1), A1 (2), A1 (3), A2
Each of (1), A2 (2), and A2 (3) is dispersed in two parallel data by 4 bits. Therefore, when the parallel data 128 including the upper 4 bits of A1 (2) is output from the data latch register 28,
From 26, the parallel data 126 including the lower 4 bits of A1 (2) and the upper 4 bits of A1 (3) is transferred to the data latch register 24.
, The parallel data 124 including the lower 4 bits of A1 (3) and the upper 4 bits of A2 (1) is output from the data latch register 22, and the lower 4 bits of A2 (1) and the upper 4 bits of A2 (2) are output from the data latch register 22. The parallel data 122 including the lower 4 bits of A2 (2) is output from the data latch register 20, and is input to the frame synchronization pattern detection circuit 30.

The frame synchronization pattern detection circuit 30 detects frame synchronization patterns A1 (2), A1 (3), A2 (1) and A2 (2) from the parallel data 120 to 128. Then, it is checked which of the pattern 7 to pattern 0 shown in FIG. 7 the bit phase of the detected frame synchronization pattern corresponds to. In this case, since the upper four bits of A1 (2) are included in the parallel data 128, the detected bit phase of the frame synchronization pattern corresponds to pattern 3.

Therefore, the frame synchronization pattern detection circuit 30
Then, the bit phase information 13 indicating 08 corresponding to the pattern 3
0 is generated and output to the bit phase information holding register 32. The bit phase information holding register 32 fetches the bit phase information 130 and stores the bit phase information 13 indicating 08.
2 is generated and output to the bit rearrangement information holding register 34. The bit rearrangement information holding register 34 fetches the bit phase information 132, generates bit rearrangement information 134 indicating 08, and outputs it to the bit rearrangement circuit 38.

In the bit rearrangement circuit 38, since the bit rearrangement information 134 indicates 08, the parallel data 122
, 124 are converted into parallel data in a state where byte synchronization is achieved. For example, as shown in FIG.
When [7: 0], D1 [7: 0], D2 [7: 0],... Are input, D0 [7: 0] is input to the bit rearrangement circuit 38 as parallel data 124. D1 [7: 0] is input as parallel data 122 and D1 [
When [7: 0] is input, D2
[7: 0] is input, and similarly, two adjacent parallel data are sequentially input.

In the bit rearrangement circuit 38, when the bit rearrangement information 134 indicating 08 is input, the parallel data 12
The bit rearrangement process is performed by judging that the bits 124 and 124 are shifted backward by 4 bits. For example, if D0 [7: 0] and D1 [7: 0] are input as parallel data 124 and 122, respectively, the lower 4 bits (D0 [3: 0]) of D0 [7: 0] are converted to the upper 4 bits And the upper 4 bits of D1 [7: 0] (D1 [7: 4])
Data 136 (D0 [3: 0], D1
[7: 4]). The bit phase of the parallel data 136 corresponds to the pattern 7 in a state where byte synchronization is achieved. Bit rearrangement processing is similarly performed for other parallel data.

The parallel data 136 generated by the bit rearrangement circuit 38 is taken into the data output register 40,
The data is output to the receiving-side STM descramble circuit 14 as parallel data 106. The parity bit 104 is delayed by three clocks in accordance with the delay of the corresponding parallel data 106, and output to the receiving-side STM descramble circuit 14 as a parity bit 108.

The receiving-side STM descramble circuit 14 performs a parity check process based on the parallel data 106, the parity bits 108, and the bit rearrangement information 110 input from the receiving-side STM frame synchronization circuit 12. FIG.
Is a timing chart showing the parity check process.

The input parallel data 106 is input to the data delay register 52 and the parity check circuit 56 shown in FIG. The parallel data 106 input to the data delay register 52 is delayed by one clock and input to the parity check circuit 56 as parallel data 150. Therefore, two adjacent parallel data 106 and 150 are input to the parity check circuit 56. The input parity bit 108 is delayed by one clock by the parity bit delay register 54 and input to the parity check circuit 56 as a parity bit 152. As a result, the parity bit 152 is synchronized with the parallel data to be subjected to the parity check.

The parity check circuit 56 performs a parity check and outputs a data error detection signal 154 when a data error is detected. Specifically, the value indicated by the input bit rearrangement information 110 is checked. When the bit rearrangement information 110 indicates 80, the input parallel data 106 has not been subjected to the bit rearrangement process in the receiving-side STM frame synchronization circuit 12, so that the parallel data 106 and the parity bit delay register Parity check is performed using the parity bit 152 from 54,
Check for data errors.

However, when the bit rearrangement information 110 indicates a value other than 80, the parallel data 106 and 150 have been subjected to the bit rearrangement process in the receiving-side STM frame synchronization circuit 12, and the parity check is performed as it is. The value of bit 152 cannot be used. Therefore, the parity check circuit 56 restores the parallel data before the bit rearrangement process is performed using the parallel data 106 and 150.

For example, as shown in FIG. 6, as the parallel data 106 (DY [3: 0], DZ [7: 4]), (DZ [3: 0], D0 [7:
4]), (D0 [3: 0], D1 [7: 4]), ... are input, PZ, P0, P1, .... are input as parity bits 108, and bit rearrangement information is input. Consider the case where 08 is input as 110. (D0 [3: 0], D1 [7: 4]) as parallel data 106
When this (D0 [3: 0], D1 [7: 4]) is input to the parity check circuit 56, (DZ [3: 0], D0 [7: 4]) as parallel data 150 But P as parity bit 152
0 is input to the parity check circuit 56.

In this case, the bit rearrangement information 110 is 08
Therefore, the bit phase of the parallel data before the bit rearrangement processing is performed corresponds to the pattern 3 in FIG. Thus, the parity check circuit 56 extracts the upper 4 bits (D0 [3: 0]) from (D0 [3: 0], D1 [7: 4]) as the parallel data 106, and outputs the parallel data 150
(DZ [3: 0], D0 [7: 4]) as lower 4 bits (D0
[7: 4]), and D0 [7: 4] is replaced with the upper 4 bits, D0
Generate parallel data using [3: 0] as the lower 4 bits. This allows the parallel data D0 before bit rearrangement
[7: 0] is restored.

The bit rearrangement information 110 is a pattern m (m
= 6 to 0), the upper (m + 1) bit of the parallel data 106 is set to the lower (m + 1) bit, and the lower (7-m) bit of the parallel data 150 is set to the upper (m-1). 7-m) Generate parallel data as bits and restore the parallel data before bit rearrangement. Next, in the parity check circuit 56, the restored parallel data D0
A parity check is performed using the parity bit [7: 0] and the parity bit P0 input from the parity bit delay register 54 at that time to check for a data error.

When a data error is detected, it is determined that a failure has occurred in the main signal path in the receiving-side STM frame synchronization circuit 12. The parity check circuit 56 outputs the data error detection signal 154 to the parity error alarm output register 58. The parity error alarm output register 58 captures the data error detection signal 154 and outputs the parity error alarm.
Output 114 to the outside. Externally, the failure of the main signal path in the receiving-side STM frame synchronization circuit 12 can be known from the parity error alarm 114. FIG. 6 shows a data error (ERR) in the parallel data D3 [7: 0] before bit rearrangement.
) Is detected, and after one clock, the parity error alarm 114 is output.
Is output.

In this embodiment, the case where the path monitoring method according to the present invention is applied to the frame synchronization circuit in the STM-1 mode has been described. However, the frame synchronization circuit in the STM-0 and STM-N modes, and the like. It can be applied to a circuit including a simple bit rearrangement circuit.

[0064]

As described above, according to the present invention, the original parallel data before bit rearrangement is restored from the parallel data whose bits have been rearranged by the bit rearrangement circuit. Since the parity check is performed using the parity bits of the parallel data before the bit rearrangement, it is possible to monitor the path of the device including the bit rearrangement circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of an STM frame synchronization circuit to which a path monitoring method according to the present invention is applied.

FIG. 2 is a block diagram illustrating an example of a receiving-side STM frame synchronization circuit in the STM frame synchronization circuit illustrated in FIG. 1;

FIG. 3 is a block diagram illustrating an example of a receiving-side STM descramble circuit in the STM frame synchronization circuit illustrated in FIG. 1;

4 is a timing chart showing an operation of the receiving-side STM frame synchronization circuit shown in FIG. 2 in a state where byte synchronization is established.

5 is a timing chart showing an operation of the receiving-side STM frame synchronization circuit shown in FIG. 2 in a state where byte synchronization is not established.

FIG. 6 is a timing chart showing an operation of a parity check unit included in the receiving-side STM descramble circuit shown in FIG. 3;

FIG. 7 is a diagram illustrating a bit phase of 8-bit parallel data.

[Explanation of symbols]

 10 High-speed interface circuit 12 Reception-side STM frame synchronization circuit 14 Reception-side STM descramble circuit 20, 22, 24, 26, 28 Data latch register 30 Frame synchronization pattern detection circuit 32-bit phase information holding register 34-bit rearrangement information holding register 36 Bit rearrangement information output register 38 Bit rearrangement circuit 40 Data output register 42, 44, 46 Parity bit shift register 52 Data delay register 54 Parity bit delay register 56 Parity check circuit 58 Parity error alarm output register

Claims (5)

[Claims] 1. A path monitoring method for monitoring a signal path of an apparatus including a bit rearranging means for rearranging bits of parallel data, the method comprising the steps of: A data error detection information generation step of generating data error detection information for detecting a data error; a bit phase detection step of detecting a bit phase of the parallel data whose bits have been rearranged by the bit rearrangement means; A parallel data restoration step of restoring parallel data before bit rearrangement from the parallel data whose bits have been rearranged by the bit rearrangement unit based on the bit phase detected in the phase detection step; A data error of the restored parallel data is determined based on the data error detection information. Path monitoring method characterized by comprising a data error detection step of leaving. 2. The path monitoring method according to claim 1, wherein said bit phase in said bit phase detecting step is a bit phase of a frame synchronization pattern included in parallel data. 3. The path monitoring method according to claim 1, wherein the data error detection information in the data error detection information generating step is a parity bit. 4. The method according to claim 1, wherein the data error detection information in the data error detection information generating step is parallel data having the same content as the parallel data before bit rearrangement. Method. 5. A path monitoring circuit for monitoring a signal path of a device including a bit rearranging means for rearranging bits of parallel data, said circuit comprising: a bit line rearranging means for rearranging parallel data before the bits are rearranged by said bit rearranging means. Data error detection information generation means for generating data error detection information for detecting a data error; bit phase detection means for detecting the bit phase of the parallel data whose bits have been rearranged by the bit rearrangement means; Based on the bit phase detected by the phase detection means, a parallel data restoration means for restoring parallel data before bit rearrangement from the parallel data whose bits have been rearranged by the bit rearrangement means, A data error of the restored parallel data is determined based on the data error detection information. Path monitoring circuit which comprises a data error detecting means for output.