JP2000269352A - Semiconductor device comprising field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device wherein increase in current density near a second drain region is suppressed. SOLUTION: On a substrate region 11, a first drain region 12, second drain region 13 with higher impurity concentration than that, channel formation region 14, and source region 15, are provided to constitute an MOSFET. Here, the impurity concentration at the central part of a first drain region 12' is raised to limit expansion of a depletion layer toward the first drain region 12' side, so that narrowing of a current path is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including an insulated gate field effect transistor with a high breakdown voltage.

[0002]

2. Description of the Related Art The present applicant has manufactured a composite or integrated semiconductor device shown in FIG. This semiconductor device has a first semiconductor element 1 composed of an insulated gate field effect transistor, and a second semiconductor element 2 having a smaller power capacity than the first semiconductor element 1. A silicon semiconductor substrate 3 for forming the first and second semiconductor elements 1 and 2;
Drain electrode 4, source electrode 5, gate insulating film 6, gate electrode 7, ground electrode 8, capacitively-coupled field plate structure 9 for first semiconductor element 1, electrode 10 for second semiconductor element 2 Etc.

A semiconductor substrate 3 includes a P-type (first conductivity type) substrate (base layer) region 11 and an N-type (second conductivity type) region.
First drain region 12 and first drain region 12
N ⁺ -type second drain region 1 having a higher impurity concentration than
3, a P-type channel forming region 14 surrounding the first drain region 12 in plan view, an N ^{+ -type} source region 15, and a semiconductor region 16 for the second semiconductor element 2. . The semiconductor region 1 for the second semiconductor element 2
Reference numeral 6 includes a collector region 16a, a base region 16b, and an emitter region 16c. The substrate region 11 is formed so as to include the entire back surface (lower surface) of the plate-shaped semiconductor substrate 3. The first drain region 12 is based on a layer in which an N-type semiconductor is epitaxially grown on the substrate region 11, has a relatively large area in plan view, and contributes to a higher breakdown voltage of the FET. I have. Second of N ^{+ type}
The drain region 13 is a region for making the drain electrode 3 have good ohmic contact, and is arranged at the center of the first drain region 12. The N ⁺ -type second drain region 13 is formed by diffusing an N-type impurity into the first drain region 12 in an island shape, and is formed relatively shallow so as not to reach the substrate region 11. ing. The P-type channel formation region 14 surrounds the first drain region 12 in plan view and is arranged to reach the P-type substrate region 11 from the surface (upper surface) of the semiconductor substrate 3. Therefore, the channel formation region 14 not only contributes to the formation of the channel of the FET, but also contributes to the electrical isolation between the first and second semiconductor elements 1 and 2. Note that the channel forming region 14 or the substrate region 11 and the channel forming region 14 together can be called a body region of the FET. The N ^{+ -type} source region 15 is formed by connecting the first drain region 12 to the channel forming region 14 in plan view.
, And is formed by diffusing an N-type impurity into the channel forming region 14 in an island shape. Semiconductor region 16 for second semiconductor element 2
The N-type collector region 16a of the transistor is disposed on the substrate region 11 so as to be adjacent to the channel forming region 14 in plan view.

The drain electrode 4 is connected to an N ^{+ type} second drain region 13. Source electrode 5 is connected to N ^{+ type} source region 15. The gate insulating film 6 is disposed between the source region 15 and the first drain region 12 so as to cover the channel forming region 14 exposed on the surface of the semiconductor substrate 3. Gate electrode 7 is arranged on gate insulating film 6, and has source region 15 and first drain region 1.
2 is opposed to the channel forming region 14. The ground electrode or back gate electrode 8 is arranged apart from the gate insulating film 6 and is connected to the channel formation region 14. Note that the emitter electrode 5 and the ground electrode 8 may be formed integrally.

[0005] Capacitively coupled field plate assembly 9
Are an insulating film 17 made of a silicon oxide film formed annularly on the surface of the first drain region 12, a plurality of ring metal conductor layers 18 for field plates, and a plurality of dielectric layers 1
9 and a plurality of connection conductor layers 20a, 20b, 20c. As is apparent from FIG. 2, the annular metal conductor layer 18 faces the first drain region 12 with the insulating film 17 interposed therebetween to form a field plate. The dielectric layer 19 is disposed so as to cover each field plate conductor layer 18. The connection conductor layer 20a as the first capacitive coupling means is provided on the innermost peripheral field plate conductor layer 18 by the dielectric layer 1a.
9 and is connected to the drain electrode 4. The connection conductor layer 20b as the second capacitive coupling means is provided on the outermost field plate conductor layer 18 with the dielectric layer 19b.
And is connected to the ground electrode 8. The connection conductor layer 20c as the third capacitive coupling means faces the field plate conductor layer 18 and functions as a capacitor series connection member. Conductor layers 20a, 20
b, 20c, the dielectric material 19 and the five field plate conductor layers 18 constitute ten capacitors directly connected to each other, and a series circuit of the ten capacitors forms a series connection of the drain electrode 4 and the ground electrode 8. Connected between them.
The annular conductor layer 18 acts as a field plate,
This contributes to making the potential change of the first drain region 12 in the horizontal direction in FIG. 1 uniform.

In the FET as the first semiconductor element 1, when the potential of the drain electrode 4 is set higher than the potential of the source electrode 5, and a gate signal is applied between the gate electrode 7 and the source electrode 5, a channel is formed. An N-type channel is formed on the surface of region 14, and a drain current flows through a path including drain electrode 4, second drain region 13, first drain region 12, N-type channel, source region 15, and source electrode 5. . The first drain region 12 is formed to be relatively thick, has a higher impurity concentration than the P-type substrate region 11, and has the field plate structure 9, so that the drain electrode 4 and the source electrode 5 A relatively high voltage can be applied between
An OSFET can be provided.

[0007]

By the way, when the potential of the drain electrode 4 is higher than the potential of the source electrode 5, a voltage is applied to the gate electrode 7, and a current flows between the drain and the source. , A first PN junction 21 between the substrate region 11 and the first drain region 12, and a second PN junction 21 between the first drain region 12 and the channel formation region 14.
N-junction 22 is in a reverse bias state, and a depletion layer is generated in a region between two broken lines 23a and 23b. Since the first drain region 12 has a resistance, the potential in the first drain region 12 gradually increases from the channel forming region 14 toward the second drain region 13. Therefore, the PN junction 2 under the second drain region 13
The voltage applied to 1 is highest and spreads most here. As a result, the drain current path of the first drain region 12 near the second drain region 13 is greatly narrowed by the depletion layer 23b of the first drain region 12, the resistance of the drain current path increases, and the current Density increases. When a relatively large current flows through a high-resistance current path near the second drain region 13, the intensity of the electric field in this region increases, and when the intensity of the electric field exceeds the maximum electric field intensity of the semiconductor, N A large number of electrons accelerated to a high electric field are generated in the first drain region 12 of the shape, and these collide with crystal grains to generate more electrons, and the number of carriers (electrons) increases at an accelerated rate. The generated majority carriers are sucked into the P-type substrate region 11. Since the P-type substrate region 11 is shared by another adjacent semiconductor element 2, the N-type collector region 16 of the second semiconductor region 2
a, an NPN-type parasitic transistor is formed by the P-type substrate region 11, the P-type channel forming region 14, and the N-type first drain region 12, and the N-type first transistor is formed.
Of the majority carriers generated in the drain region 12 of the P-type substrate region 11 acts as a base current of the parasitic transistor, the parasitic transistor is turned on, a large current continues to flow, and the semiconductor device may be thermally damaged. is there. Since this thermal breakdown occurs at a drain-source voltage lower than a calculated (theoretical) voltage (withstand voltage) between the drain and the source, despite the high breakdown voltage structure as shown in FIG. It was not possible to operate with a high withstand voltage. Such a problem is that when the first drain region 12 and the source region 15 are arranged concentrically around the second drain region 13 in a ring shape, the current density becomes high particularly near the second drain region 13. It occurs remarkably.

An object of the present invention is to provide a semiconductor device capable of suppressing an increase in current density near the second drain region.

[0009]

SUMMARY OF THE INVENTION The present invention for solving the above-mentioned problems and achieving the above-mentioned objects will be described with reference to the reference numerals in the drawings showing the embodiments. First semiconductor element 1 and second semiconductor element 2
Wherein the first semiconductor element 1 is a semiconductor device which is an insulated gate field effect transistor, wherein the semiconductor substrate 3 comprises a substrate region 11 of a first conductivity type;
First and second drain regions 12 ′ and 13 of a second conductivity type opposite to the first conductivity type, a channel formation region 14 of the first conductivity type, a source region 15 of the second conductivity type, A semiconductor region 16 for the semiconductor element 2 of the first and second semiconductor elements 1 and 2; and the first drain region 12 ′ is a common substrate of the first and second semiconductor elements 1 and 2. The semiconductor substrate 3 has an impurity concentration higher than that of the substrate region 11 and
Is disposed so as to have a portion exposed to one of the main surfaces and to have a portion adjacent to the substrate region 11,
The impurity concentration of the first drain region 12 ′ is
The drain region 13 is set so as to gradually or continuously decrease from the drain region 13 toward the channel forming region 14, and the second drain region 13 is connected to the first drain region 1.
The semiconductor device has an impurity concentration higher than that of 2 ′ and is arranged to be exposed on one main surface of the semiconductor substrate 3 and is arranged in an island shape in the first drain region 12 ′. The formation region 14 has a portion exposed on one main surface of the semiconductor substrate 3 and is arranged so as to be separated from the second drain region 13 and adjacent to the first drain region 12 ′. The region 15 is arranged in an island shape in the channel forming region 14, the drain electrode 4 is connected to the second drain region 13, the source electrode 5 is connected to the source region 15, and one of the semiconductor bases 3 is formed. A gate insulating film 6 is provided so as to cover the main surface between the source region 15 and the first drain region 12 ′, and a gate electrode 7 is disposed on the gate insulating film 6. Those related to the semiconductor device according to symptoms.

It is desirable that a plurality of field plate conductor layers 18 be provided on the first drain region 12 'with an insulating layer 17 interposed therebetween. Also,
It is preferable that the second drain region 13 is arranged at the center of the first drain region 12 '.
Further, the buried region 50 can be provided as described in claim 4.

[0011]

According to the present invention, the impurity concentration of the first drain region 12 'decreases stepwise or continuously from the second drain region 13 toward the channel forming region 14. In the vicinity of the second drain region 13, the effect of suppressing the depletion layer increases. Thereby, the passage of the drain current in the first drain region 12 'is made uniform, so that the current density near the second drain region 13 increases, the electric field intensity increases, and the power loss increases. . As a result, thermal destruction of the semiconductor device can be prevented. According to the second aspect of the present invention, the withstand voltage can be improved satisfactorily with the effect of the field plate. According to the third aspect of the invention, thermal destruction due to an increase in current density due to the cylindrical structure can be easily prevented. Further, according to the invention of claim 4, the expansion of the depletion layer can be suppressed more favorably.

[0012]

Embodiments and Examples Next, embodiments and examples of the present invention will be described with reference to FIGS. However, in FIGS. 3 to 5, substantially the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

[0013]

FIG. 3 shows the surface of a semiconductor substrate 3 of a semiconductor device according to a first embodiment, and FIG.
FIG. 3 shows a cross-sectional view of a portion corresponding to line -A. FIG. 3 shows an N-type collector region 16 as a semiconductor region 16 for the second semiconductor device 2 having a smaller power capacity than the first semiconductor device 1.
a, a P-type base region 16b and an N-type emitter region 16c are shown. The semiconductor device of the first embodiment shown in FIG. 4 has the same configuration as that of FIG. 1 except for an N-type first drain region 12 '. First drain region 1 in FIG.
2 'has the same pattern as the first drain region 12 of FIG. 1 as a whole, and has a higher impurity concentration than the sub-straight region 11. The first drain region 12 '
4, first, second, third, and fourth portions 2a, 12b, and
12c and 12d. The first portion is a region where the impurity concentration is high, and the second drain region 13
Is arranged at the center of the first drain region 12 '. The second portion 12b is a region having a lower impurity concentration than the first portion 12a, and is arranged so as to annularly surround the first portion 12a. The third part 12c is the second part
This is a region having a lower impurity concentration than the portion 12b, and is arranged so as to annularly surround the second portion 12b. The fourth portion 12d is a region having a lower impurity concentration than the third portion 12c, and is disposed so as to annularly surround the third portion 12c. The fourth region 12d is a non-impurity diffusion region of a layer epitaxially grown on the substrate region 11.

First, second, third and fourth portions 1 having different impurity concentrations from each other in first drain region 12 '.
5A, a first impurity diffusion layer 12a 'is formed in the N-type epitaxial growth layer 30 in the P-type substrate region 11, as shown in FIG. As shown in FIG. 7, a second impurity diffusion layer 12b 'is formed so as to have a portion overlapping the first impurity diffusion layer 12a' and a portion surrounding the same, and furthermore, the first and second impurity diffusion regions 12a '. , 12b ′ so as to have a portion overlapping with and surrounding the third impurity diffusion layer 12b ′.
After forming c ', the first, second and third impurity diffusion layers 12a', 12b 'and 12c' are obtained by deep diffusion as shown in FIG. 5C. Although the diffusion depths of the first, second, and third portions 12a, 12b, and 12c do not always match, FIGS. 4 and 5 show a state where they match.

The diffusion of the N-type impurity was performed three times in duplicate.
The impurity concentration of the first portion 12a is about 2.5 × 10¹⁵cm
^-3And the impurity concentration of the second portion 12b is about 2.0 ×
10 ¹⁵cm^-3And the impurity concentration of the third portion 12c is
About 1.6 × 10¹⁵cm^-3And the fourth part 12d is not
Pure substance concentration is about 1.2 × 10¹⁵cm^-3It is. Therefore,
The impurity concentration of the first drain region 12 'is the second drain region.
Impurity concentration from region 13 to channel formation region 14
Is gradually decreasing.

According to the present invention, a first drain region 12 'is provided.
The distribution of the impurity concentration is made non-uniform in order to make the spread of the depletion layer uniform to the first drain region 12 '.

FET as first semiconductor device 1 in FIG.
A drain-source voltage is applied between the drain electrode 4 and the source electrode 5 so that the potential of the drain electrode 4 is higher than the potential of the source electrode 5.
When a gate-source voltage is applied between the gate electrode 7 and the source electrode 5 so that an N channel is formed, the drain current is increased to the drain electrode 4 and the second drain region 1.
3, flows through the path of the first drain region 12 ′, the N-type channel, the source region 15 and the source electrode 5. At this time, the first PN junction 21 between the substrate region 11 and the first drain region 12 'and the second PN junction 22 between the channel forming region 14 and the first drain region 12' are reversed. In a bias state, broken lines 23a, 23b, 2 in FIG.
As shown by 3c, a depletion layer is generated. In FIG. 4, dashed line 23a,
The depletion layer indicated by 23b 'is the same as the depletion layers indicated by broken lines 23a and 23b in FIG. 1 when the rated voltage is applied between the drain electrode 4 and the source electrode 5, and the first and second PN junctions 2 are formed.
1 and 22. As described above, the depletion layer changes depending on the impurity concentration and the strength of the electric field. In the conventional FET of FIG. 1, the length of the portion where the emitter region 15 and the first drain region 12 face each other is larger than the outer peripheral length of the second drain region 13, so that the density of the drain current is the second. In the vicinity of the drain region 13 of FIG. On the other hand, in the FET of FIG. 4 of the present embodiment, the second drain region 1
The first portion 12 of the first drain region 12 'near
Since the impurity concentration of a is high, the spread of the depletion layer there is limited. Further, the impurity concentration of the first drain region 12 is changed from the second drain region 13 to the channel formation region 14.
Gradually decreases toward the first drain region 12 ', and the spread of the depletion layer toward the first drain region 12' is increased as shown by a broken line 23b '. Being substantially parallel to the PN junction 21, a sufficient drain current path can be obtained, and the FET can be prevented from being thermally damaged. That is, the first drain region 1
In the vicinity of the second drain region 13 of 2 ', the drain current density does not abnormally increase, and majority carriers (electrons)
Is limited by thermal implantation due to implantation into the substrate region 11. Therefore, the maximum voltage between the drain electrode 4 and the source electrode 5 can be increased. Further, since the concentrically arranged field plate members 9 are provided, the potential change in the first drain region 12 can be made uniform, and the withstand voltage characteristics are improved.

[0018]

Second Embodiment A second embodiment is directed to a first drain region 1.
In the method for obtaining the predetermined impurity distribution of 2 ′,
This embodiment is different from the first embodiment, and the other points are the same as those of the first embodiment. In the second embodiment, as shown in FIG. 6, first, second, third and fourth films 41, 42, 43 and 44 are formed on an N-type epitaxial growth layer 30 on a P-type substrate region 11.
Is disposed, and the first and second masks 45 having different thicknesses are arranged.
Then, impurity ions are implanted through the third films 41, 42, and 43 by a well-known ion implantation method to form an N-type impurity implantation region 46.
Of the first, second, third, and fourth portions 12a, 12b, and 12 of the first embodiment.
Regions corresponding to 12c and 12d are obtained. The mask 4
The impurity implantation amount changes depending on the difference in film thickness of No. 5. According to the second embodiment, a semiconductor device having the same effect as that of the first embodiment can be easily formed.

[0019]

Third Embodiment Next, a third embodiment of the present invention will be described with reference to FIGS. However, in FIGS. 7 and 8, portions substantially the same as those in FIGS. 1 to 6 are denoted by the same reference numerals, and description thereof is omitted. The semiconductor device of the third embodiment shown in FIGS. 7 and 8 is the same as that of FIG. 4 except that an N-type buried region 50 is added to the semiconductor device of the first embodiment of FIG. . The buried region 50 is disposed between the first drain region 12 and the substrate region 11 as is apparent from FIG. 7, and is disposed so as to include the entire second drain region 13 at the center in plan view. Have been. More specifically, the buried region 50 is arranged concentrically with respect to the first and second drain regions 12 ′ and 13 and the source region 15 in plan view, and the outer peripheral edge thereof is the second
Between the drain region 13 and the channel formation region 14. The buried region 31 is the substrate region 1
1 and the first drain region 12 ′. Such an arrangement is similar to substrate region 11
N-type impurities are diffused into a predetermined region of the main surface of
This is inevitably caused by epitaxially growing N-type silicon for obtaining the drain region 12 'of FIG.

The buried region 50 is provided to prevent the drain current path in the first drain region 12 'from being narrowed by the depletion layer. Therefore, when a rated voltage is applied between the drain electrode 4 and the source electrode 5, the P-type substrate region 11 and the N-type buried region 50
Between the first drain region 12 'and the buried region 50 as indicated by the broken line 23c on the N-type buried region 50 side caused by the reverse bias of the PN junction 53 between the first drain region 12' and the buried region 50.
The impurity concentration and the thickness (depth) of the N-type buried region 50 are determined so as to be in the vicinity of the boundary with. If the impurity concentration of the buried region 50 is too low, the PN junction 32
Depletion layer fills the buried region 50 and greatly extends to the first drain region 12 ', thereby narrowing the path of the drain current in the first drain region 12'. If the thickness (depth) of the buried region 50 is too small, even if the impurity concentration is relatively high, the buried region 50 is buried by the depletion layer, and the depletion layer greatly spreads to the first drain region 12 '. The drain current path in one drain region 12 'is narrowed. Therefore, in this embodiment, the impurity concentration of the substrate region 11 is about 2.5 ×
10 ¹⁴ cm ⁻³ , the impurity concentration of the first drain region 12 ′ is about 1.0 to 2.5 × 10 ¹⁵ cm ⁻³ , and the buried region 50
Impurity concentration of about 1.2 × 10 ^{15 to} 2.5 × 10 ¹⁵ cm
^-3 is set.

The N-type buried region 50 has first and second impurity concentration regions 51 and 52 as shown in FIG. The first impurity concentration region 51 at the center of the buried region 50 is arranged so as to face the second drain region 13, and has a circular planar shape. The second impurity concentration region 52 is disposed so as to annularly surround the first impurity concentration region 51,
Impurity concentration region 34 has a lower impurity concentration.
Note that the impurity concentration of the first impurity concentration region 51 is about 2.
The impurity concentration is 5 × 10 ¹⁵ cm ⁻³ and the impurity concentration of the second impurity concentration region 51 is about 1.2 × 10 ¹⁵ cm ⁻³ . In this embodiment, the impurity concentration of the buried region 50 is changed in two steps, but may be changed in three or more steps or continuously.

In the third embodiment, since both the N-type buried region 50 and the N-type first drain region 12 'have an impurity concentration distribution that limits the spread of the depletion layer, the PN junction 5 is formed.
As shown by the dashed line 23c of the depletion layer caused by No. 3, it is possible to obtain the same effect as that of the first embodiment.

[0023]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) The embedding region 50 can be configured by a combination of a plurality of regions. (2) In the third embodiment, the buried region 50 has the highest impurity concentration in the central portion facing the second drain region 13 and the impurity concentration decreases as the distance from the buried region 50 increases. It can be an impurity concentration distribution. (3) Although a remarkable effect can be obtained by adopting the cylindrical structure as in each embodiment, a structure in which the left half or the right half of the second drain region 13 is removed may be employed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a conventional semiconductor device.

FIG. 2 is an enlarged sectional view showing a part of the field plate structure of FIG. 1;

FIG. 3 is a plan view showing a part of the surface of the semiconductor substrate of the semiconductor device according to the first embodiment of the present invention.

FIG. 4A of the semiconductor device according to the first embodiment of the present invention;
It is sectional drawing which expands and shows the part corresponding to the -A line.

FIG. 5 is a cross-sectional view for describing a method for forming a first drain region.

FIG. 6 is a cross-sectional view for describing a first drain region forming method according to the second embodiment.

FIG. 7 is a sectional view showing a semiconductor device according to a third embodiment in the same manner as in FIG. 4;

8 is a cross-sectional view showing the buried region of FIG. 7 and its vicinity.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st semiconductor element 2 2nd semiconductor element 3 Semiconductor base 11 Substrate area 12 '1st drain area 13 2nd drain area 14 Channel formation area 15 Source area 50 Embedded area

Claims (4)

[Claims] 1. A semiconductor device comprising: a first semiconductor element (1) and a second semiconductor element (2) formed based on a common semiconductor substrate (3), wherein the first semiconductor element (1) is insulated. A semiconductor device that is a gate type field effect transistor, wherein the semiconductor substrate (3) includes a substrate region (11) of a first conductivity type and a first region of a second conductivity type opposite to the first conductivity type.
And a second drain region (12 ', 13), a channel formation region (14) of the first conductivity type, a source region (15) of the second conductivity type, and the second semiconductor element (2). The substrate region (11) is a common substrate of the first and second semiconductor elements (1, 2), and the first drain region (12 '). ) Has an impurity concentration higher than that of the substrate region (11), has a portion exposed on one main surface of the semiconductor substrate (3), and is adjacent to the substrate region (11). And the impurity concentration of the first drain region (12 ') decreases stepwise or continuously from the second drain region (13) toward the channel forming region (14). Set as The second drain region (13) has an impurity concentration higher than that of the first drain region (12 ') and is arranged so as to be exposed on one main surface of the semiconductor substrate (3). And is arranged in an island shape in the first drain region (12 '), wherein the channel forming region (14) is the semiconductor substrate (3).
The source region (15), having a portion exposed on one main surface of the first region (12) and being spaced apart from the second drain region (13) and adjacent to the first drain region (12 '). Is the channel forming region (1)
4) a drain electrode (4) disposed in an island shape in the second drain region (13);
Are connected to the source region (15), and the source electrode (5) is connected to the source region (15) and the first drain region (12 ') on one main surface of the semiconductor substrate (3). A semiconductor device, wherein a gate insulating film (6) is provided so as to cover the space therebetween, and a gate electrode (7) is disposed on the gate insulating film (6). 2. A ground electrode (8) connected to a portion of the channel formation region (14) remote from a portion where the gate insulating film (6) is arranged, and the ground electrode (8) of the semiconductor substrate (3). An insulating film (17) formed on a surface between a second drain region (13) and the channel forming region (14); and a plurality of field plate conductors disposed on the insulating film (17). A layer (18); first coupling means for capacitively coupling the one of the plurality of field plate conductor layers (18) closest to the drain electrode (4) to the drain electrode (4); Second coupling means for capacitively coupling one of the plurality of field plate conductor layers (18) farthest from the drain electrode (4) to the ground electrode (8); and the plurality of field plate conductors 3. The semiconductor device according to claim 1, further comprising third coupling means for sequentially capacitively coupling the layers. 3. The first drain region (12 ′) is formed in a circular shape in plan view, and the second drain region (13) is in plan view in the first drain region (12). The source region (15) is disposed in the center of the first drain region (1) via the channel forming region (14) when viewed in plan.
3. The semiconductor device according to claim 1, wherein the semiconductor device is arranged so as to surround 2 '). 4. The first drain region (1)
4. The semiconductor device according to claim 1, further comprising a buried region (50) of the same conductivity type as that of said first drain region (12 ') between said substrate region (2') and said substrate region (11).