JP2000269233A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a vertical bipolar transistor to an irreducible minimum in characteristic variations. SOLUTION: An insulating sidewall, composed of a silicon nitride film 10 and a silicon oxide film 9, is formed on the side face of an opening 101 provided to a base electrode polysilicon film 7. The thickness (=Wsw) of an insulating sidewall is set larger than the maximum thickness (=Wcrystal) of a polycrystalline film 12, which is within a range of variations in thickness and grows on the side of the base electrode polysilicon film 7 (that is, Wsw> Wcrystal). As a result, an opening provided in an intrinsic base region 11, where an emitter electrode polysilicon 16 is deposited, is not controlled is dimensions by the variable overhang of a polycrystalline film 12 toward the inside of an opening provided to a base electrode polysilicon film but by insulating sidewalls 9 and 10, so that an emitter can be greatly restrained from varying in area and exerts less effect on the electrical characteristics of a semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a transistor such as a vertical bipolar transistor and a field effect transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art The inventor of the present application filed Japanese Patent No. 25
In the application related to Japanese Patent No. 51353, a vertical bipolar transistor having a high cutoff frequency and stable interconnection of each film inside and a method of manufacturing the same have been proposed. FIG. 30 is a schematic cross-sectional view of a vertical bipolar transistor similar to the vertical bipolar transistor disclosed in the Japanese Patent Publication No. 2555133.

In FIG. 30, reference numeral 1 denotes a plane of a crystal.
The orientation is (100) and the resistivity is 10 to 20Ω
・ P which is cm^- 1 shows a mold silicon substrate. This
In the surface region of the recon substrate 1, two types of filling with a thickness of several μm are provided.
Embedded layer is formed. The two types of embedded layers are n⁺ 
Mold buried layer 2-a and p for channel stopper ⁺ 
Mold buried layer 2-b, which is separated from each other.
You. The surface of these buried layers and buried layers are present
The surface of the silicon substrate 1 in the area where no ^- Type
An epitaxial layer 3 for a rectifier is formed. Soshi
And p⁺ Silicon to the depth to reach the mold buried layer 2-b
Oxide film 4 is selectively formed to form an element isolation film.
ing. Also, n^- Type collector epitaxial layer 3
By adding impurities at a high concentration to a part of⁺ 
N connected to the mold buried layer 2-a ⁺ Type collector drawer
An area 5 is formed. Repeat the parts described so far.
It is referred to as silicon substrate 100.

A silicon oxide film 6 is formed on a silicon substrate 100, and a p ⁺ -type base electrode polysilicon film 7 is selectively formed thereon. The base electrode polysilicon film 7 is covered with a silicon nitride film 8. The first opening 101 penetrates the silicon nitride film 8 and the base electrode polysilicon film 7.
Is formed, and a second opening 102 is formed to penetrate through silicon oxide film 6, exposing collector epitaxial layer 3. The first opening 101 formed in the polysilicon film 7 protrudes horizontally from the end of the second opening 102 into the second opening 102. That is,
The width of the second opening 102 is larger than the width of the first opening 101.

[0005] Inside the second opening 102, a collector epitaxy
On the xial layer 3, p⁺ Type single crystal intrinsic base region 1
1 is formed. Of the polysilicon film 7 for the base electrode
On the side and exposed lower surface, p⁺ Type polysilicon film 12 is shaped
Has been established. Thus, p ⁺ Type polysilicon film 12
Is the polysilicon film 7 for the base electrode and the single crystal intrinsic base.
The connection with the region 11 is established.

An n ⁺ -type single-crystal emitter region 15 is provided in a central region on the p ⁺ -type single-crystal intrinsic base region 11. A silicon oxide film 13 is formed to cover the side wall of the opening. In the collector epitaxial layer 3 immediately below the base region, the single crystal intrinsic base region 11 and n ⁺
The region between the mold buried layer 2-a includes a collector region 14 made of n-type silicon doped with an impurity at a higher concentration than the original impurity concentration of the epitaxial layer 3 for collector. N ⁺ -type single-crystal emitter region 1 of single-crystal silicon
5, a polysilicon film 16 for an n ⁺⁺ type emitter electrode.
Is provided. All of these regions are covered with the silicon oxide film 17.

Further, contact holes penetrating the silicon oxide film 17 and further penetrating the silicon nitride film 8 and the silicon oxide film 6 depending on the location are formed, and an aluminum alloy or the like is filled so as to fill the contact holes. A metal film is formed and further patterned to form an aluminum alloy electrode for emitter 18-a, an aluminum alloy electrode for base 18-b, and an aluminum alloy electrode for collector 18-c.
Are formed. These aluminum alloy electrode 18-a for emitter and aluminum alloy electrode 18-b for base
The collector aluminum alloy electrode 18-c is in contact with the emitter electrode polysilicon film 16, the base electrode polysilicon film 7, and the collector extraction region 5, respectively.

[0008]

The vertical bipolar transistor having the above-described structure has a correspondingly high-speed operation characteristic, but has a problem that the operating current varies widely. Specifically, in a bipolar transistor circuit, the emitters of adjacent transistors are short-circuited to form a differential pair. The voltages applied to the bases so that the collector current of each transistor of the differential pair becomes the same are VB1 and VB2. This voltage difference, VB1
If the absolute value of −VB2 is defined as ΔVB, it is more advantageous to make ΔVB smaller in order to stabilize the circuit operation. This is because, when ΔVB is small, when several pairs of differential pairs are combined inside the circuit, it is possible to suppress a variation in input potential necessary for switching of the differential pairs. The ΔVB was large in the vertical bipolar transistor having the above-described configuration.

This problem is described in Japanese Patent No. 2555133.
In the vertical bipolar transistor disclosed in the above publication, there is no problem because the side surface of the base electrode polysilicon is completely covered with the insulating film. However, in the vertical bipolar transistor disclosed in Japanese Patent Publication No. 2555133, the thickness WB of the single crystal intrinsic base region formed by the selective crystal growth method.
Is smaller than the distance d between the upper surface of the collector epitaxial layer and the lower surface of the base electrode polysilicon film [WB <
d]. Therefore, if the thickness of the polysilicon film selectively grown on the lower surface of the base electrode polysilicon film is reduced, another problem occurs that the intrinsic base does not connect to the base region polysilicon film. Further, when the single crystal intrinsic base region is in direct contact with the silicon nitride film, an increase in leakage current (in extreme cases, generation of crystal defects) causes an increase in leakage current. Therefore, an object of the present invention is to provide a transistor and a method for manufacturing the transistor, which solve the above-mentioned problems in the conventional technology.

Further, as the transistor size is reduced in recent years, the width of the emitter opening in which the polysilicon film for the emitter electrode is formed is reduced, and the parasitic resistance of the emitter is increased, thereby deteriorating the transistor characteristics. Tend to. The following two reasons can be cited as reasons why the emitter parasitic resistance increases. The first reason is that the thickness of the polysilicon film for the emitter electrode is reduced. The second reason is that the polysilicon for the emitter electrode is usually formed by a so-called in-situ doping method in which arsenic is added during growth, but the aspect ratio of the opening where the polysilicon for the emitter electrode is formed is large. And the high concentration of arsenic to be added results in poor coverage of the film and easy formation of voids in the openings.

[0011]

According to a first feature of the present invention, a single-conductivity-type single-crystal semiconductor substrate and a main surface of the single-crystal semiconductor substrate are covered with each other. A first insulating film having a first opening having a first predetermined width to partially expose the first insulating film, a first semiconductor layer of an opposite conductivity type partially covering the first insulating film, A second insulating film covering the first semiconductor layer, the first semiconductor layer and the second insulating film;
A second opening formed so as to have a second predetermined width aligned with the first opening so as to penetrate through the insulating film of the first and second insulating films. 1 is smaller than the predetermined width of the first semiconductor layer.
The edge of the opening is exposed on the side of the second opening and the side of the second opening which forms an overhanging portion that protrudes into the first opening of the first insulating film. The first
An insulating sidewall formed on a side surface of the second opening of the first semiconductor layer and the second insulating film so as to expose a lower portion of a side surface of the protruding portion of the semiconductor layer; A second semiconductor layer made of a reverse conductivity type single crystal semiconductor formed on the part of the main surface of the single crystal semiconductor substrate in the first opening of the first insulating film; A lower surface of the protruding portion and a lower portion of the side surface of the semiconductor layer;
A third semiconductor layer of the opposite conductivity type, which is coupled to the end of the semiconductor layer of the second conductivity type; a fourth semiconductor layer of the one conductivity type formed in the upper surface region of the second semiconductor layer; A fifth semiconductor layer of one conductivity type formed on an upper surface of the semiconductor layer, wherein a thickness of the insulating side wall is larger than a thickness of the third semiconductor layer. An apparatus is provided.

In one embodiment, the single-crystal semiconductor substrate is a single-crystal silicon substrate, the first semiconductor layer is formed of polysilicon, and the second semiconductor layer is formed of single-crystal silicon; The third semiconductor layer and the fifth semiconductor layer are formed of polysilicon. In another embodiment, the single-crystal semiconductor substrate is a single-crystal silicon substrate, the first semiconductor layer is formed of polysilicon, the second semiconductor layer is formed of single-crystal SiGe,
The third semiconductor layer is formed of polycrystalline SiGe, and the fifth semiconductor layer is formed of polysilicon. In still another embodiment, the single crystal semiconductor substrate is a single crystal silicon substrate, the first semiconductor layer is formed of single crystal silicon, the second semiconductor layer is formed of single crystal silicon, The third semiconductor layer is formed of single crystal silicon, and the fifth semiconductor layer is formed of polysilicon.

Further, the insulating side wall is formed on the first semiconductor layer so as to expose a lower portion of the side surface of the protruding portion of the first semiconductor layer exposed on a side surface of the second opening. A first insulating side wall formed on a side surface of the second opening with the second insulating film; and a first insulating side wall formed on the first insulating side wall and parallel to a side surface of the second opening. A second insulating side wall that is wider than the first insulating side wall. Further, a third insulating film covering the insulating side wall and defining a region of the fourth semiconductor layer may be further provided.

According to a second aspect of the present invention, a single-conductivity type single crystal semiconductor substrate and a second semiconductor substrate which covers a main surface of the single crystal semiconductor substrate and exposes a part of the main surface of the single crystal semiconductor substrate. A first insulating film having a first opening having a predetermined width of 1, a first semiconductor layer of a reverse conductivity type single crystal semiconductor partially covering the first insulating film; A second insulating film covering the first semiconductor layer, and a second predetermined width aligned with the first opening so as to penetrate the first semiconductor layer and the second insulating film. Wherein the second predetermined width is smaller than the first predetermined width, so that the edge of the second opening of the first semiconductor layer is A second opening that forms an overhanging portion that overhangs the first opening of the first insulating film; A side surface of the second opening between the first semiconductor layer and the second insulating film so as to expose a lower portion of the side surface of the protruding portion of the first semiconductor layer exposed on the side surface of the portion; An insulating sidewall formed thereon, and the first side wall;
A second semiconductor layer made of a reverse conductivity type single crystal semiconductor formed on the part of the main surface of the single crystal semiconductor substrate in the first opening of the insulating film; A third semiconductor layer of an opposite conductivity type that couples a lower surface of the protruding portion of the semiconductor layer, a lower portion of the side surface, and an end of the second semiconductor layer; and an upper surface region of the second semiconductor layer. A semiconductor device comprising: a fourth semiconductor layer of one conductivity type; and a fifth semiconductor layer of one conductivity type formed on an upper surface of the fourth semiconductor layer. Provided.

According to a third feature of the present invention, a one-conductivity-type single-crystal semiconductor substrate, and a first-conductivity-type single-crystal semiconductor substrate that covers a main surface thereof and exposes a part of the main surface of the single-crystal semiconductor substrate. A first insulating film having a first opening having a predetermined width of 1, a first semiconductor layer of a reverse conductivity type single crystal semiconductor partially covering the first insulating film; A second insulating film covering the first semiconductor layer, and a second predetermined width aligned with the first opening so as to penetrate the first semiconductor layer and the second insulating film. Wherein the second predetermined width is smaller than the first predetermined width, so that the edge of the second opening of the first semiconductor layer is A second opening for projecting into the first opening of the first insulating film so as to form an overhanging portion; A second semiconductor layer made of a reverse conductivity type single crystal semiconductor formed on the part of the main surface of the single crystal semiconductor substrate in the first opening of the film, and the first semiconductor layer A third semiconductor layer made of a single-crystal semiconductor of an opposite conductivity type that couples a lower surface of the protruding portion, a lower portion of the side surface, and an end of the second semiconductor layer, and an upper surface region of the second semiconductor layer A fourth semiconductor layer of one conductivity type, and a fifth semiconductor layer of one conductivity type formed on the upper surface of the fourth semiconductor layer. A semiconductor device is provided.

According to a fourth aspect of the present invention, a one-conductivity-type single-crystal semiconductor substrate, and a first-conductivity-type single-crystal semiconductor substrate that covers a main surface thereof and exposes a part of the main surface of the single-crystal semiconductor substrate. A first insulating film having a first opening having a predetermined width of 1, a first semiconductor layer of a reverse conductivity type single crystal semiconductor partially covering the first insulating film; A second insulating film covering the first semiconductor layer, and a second predetermined width aligned with the first opening so as to penetrate the first semiconductor layer and the second insulating film. Wherein the second predetermined width is smaller than the first predetermined width, so that the edge of the second opening of the first semiconductor layer is A second opening for projecting into the first opening of the first insulating film so as to form an overhanging portion; A second semiconductor layer made of a reverse conductivity type single crystal semiconductor formed on the part of the main surface of the single crystal semiconductor substrate in the first opening of the film, and the first semiconductor layer Forming a third semiconductor layer made of a reverse-conductivity-type single crystal semiconductor, which couples the lower surface and the side surface of the protruding portion with the end of the second semiconductor layer, and an upper surface region of the second semiconductor layer A fourth semiconductor layer of one conductivity type,
There is provided a semiconductor device comprising: a fifth semiconductor layer of one conductivity type formed on an upper surface of the fourth semiconductor layer.

According to a fifth aspect of the present invention, a one-conductivity-type single-crystal semiconductor substrate, and a first-conductivity-type single-crystal semiconductor substrate that covers a main surface and exposes a part of the main surface of the single-crystal semiconductor substrate. A first insulating film having one opening, and being aligned with the first opening, wherein the width at the lower end is narrower than the width of the first opening and gradually widens upward. A first semiconductor layer of a reverse conductivity type single crystal semiconductor, which has a second opening formed by partially covering the first insulating film;
A third opening having a width substantially equal to or somewhat smaller than a width of an upper end portion of the second opening, the third opening being formed in alignment with the second opening; A second insulating film covering the first semiconductor layer; and a part formed on the part of the main surface of the single crystal semiconductor substrate in the first opening of the first insulating film, A second semiconductor layer made of a reverse conductivity type single crystal semiconductor in contact with a lower surface of the protruding portion of the first semiconductor layer protruding into the first opening;
A third semiconductor layer of one conductivity type formed on an upper surface region of the second semiconductor layer and a fourth semiconductor layer of one conductivity type formed on an upper surface of the fourth semiconductor layer; A semiconductor device is provided.

According to a sixth feature of the present invention, a first insulating film is formed so as to cover a main surface of a single conductivity type single crystal semiconductor substrate, and a reverse insulating film partially covering the first insulating film is formed. A first semiconductor layer of a conductivity type is formed, a second insulating film covering the first semiconductor layer is formed, and a first insulating film is formed so as to penetrate the first semiconductor layer and the second insulating film. Forming a first opening having a predetermined width, forming a third insulating film covering the bottom surface and side surfaces of the first opening and the second insulating film, and forming the third insulating film. Forming a fourth insulating film covering the upper surface and having a property different from that of the third insulating film; etching back the fourth insulating film and the third insulating film to form a second insulating film on the second insulating film; Completely removing the fourth insulating film and the third insulating film, and completely removing the fourth insulating film from the bottom surface of the first opening. The third insulating film is exposed, and insulating sidewalls made of the fourth insulating film and the third insulating film are left on the side surfaces of the first opening, and the first insulating film and the third insulating film are removed. Selectively removing the insulating film to expose a part of the main surface of the single crystal semiconductor substrate, and forming a second opening having a second predetermined width larger than the first predetermined width, The first
The first semiconductor layer is formed in alignment with the opening of the first semiconductor layer, and the edge of the first opening of the first semiconductor layer is
The first opening is formed by forming a protruding portion that protrudes into the opening of the first opening, and partially leaving the third insulating film below the fourth insulating film on a side surface of the first opening. The lower part of the side surface of the protruding portion of the first semiconductor layer exposed on the side surface of the portion is exposed, and the protruding portion of the first semiconductor layer exposed on the side surface of the first opening is formed. A semiconductor is grown on a lower portion of a side surface and on a part of the main surface of the single crystal semiconductor substrate exposed in the second opening, and the one of the main surface of the single crystal semiconductor substrate is grown. A second semiconductor layer made of a reverse-conductivity-type single-crystal semiconductor on the portion, and from the lower surface of the protruding portion and the lower portion of the side surface of the first semiconductor layer to an end of the second semiconductor layer. A third semiconductor layer of opposite conductivity type having a thickness less than the thickness of the insulating sidewall Forming a fourth semiconductor layer of one conductivity type formed on the upper surface region of the second semiconductor layer and a fifth semiconductor layer formed on the upper surface of the fourth semiconductor layer. A method for manufacturing a semiconductor device is provided.

In one embodiment, the single crystal semiconductor substrate is formed of a single crystal silicon substrate, the first semiconductor layer is formed of polysilicon, and silicon is grown as the semiconductor to form the second crystal. Is selectively formed of single-crystal silicon, and the third semiconductor layer is selectively formed of polysilicon. In another embodiment, the second semiconductor layer is formed by forming the single crystal semiconductor substrate from a single crystal silicon substrate, forming the first semiconductor layer from polysilicon, and growing SiGe as the semiconductor. Is selectively formed of single-crystal SiGe, and the third semiconductor layer is selectively formed of polycrystalline SiGe. In still another embodiment, the single-crystal semiconductor substrate is formed of a single-crystal silicon substrate, the first semiconductor layer is formed of single-crystal silicon, and silicon is grown as the semiconductor. The semiconductor layer is selectively formed using single crystal silicon, and the third semiconductor layer is selectively formed using single crystal silicon.

Further, a polycrystalline semiconductor containing a high-concentration one-conductivity-type impurity is deposited on the upper surface of the second semiconductor layer, so that the first-conductivity-type second conductivity-type impurity is deposited on the upper surface of the second semiconductor layer. And forming a fourth semiconductor layer of one conductivity type in an upper surface region of the second semiconductor layer by diffusing impurities of one conductivity type from the fifth semiconductor layer of one conductivity type. be able to. Furthermore, after further forming a fifth insulating film covering the insulating side wall and defining the exposed surface of the part of the main surface of the single crystal semiconductor substrate, a high-level insulating film is formed on the upper surface of the second semiconductor layer. The polycrystalline semiconductor containing a concentration of one conductivity type impurity may be deposited.

According to a seventh aspect of the present invention, a first insulating film is formed so as to cover a main surface of a single conductivity type single crystal semiconductor substrate, and a reverse insulating film partially covering the first insulating film is formed. A conductive semiconductor layer is formed and monocrystallized, a monocrystallized first semiconductor layer is formed, a second insulating film covering the first semiconductor layer is formed, and the monocrystallized first semiconductor layer is formed. Forming a first opening having a first predetermined width so as to penetrate the semiconductor layer and the second insulating film, and a bottom surface and a side surface of the first opening and the second insulating film Forming a third insulating film covering the third insulating film, forming a fourth insulating film covering the third insulating film and having a property different from that of the third insulating film; The third insulating film is etched back to completely remove the fourth insulating film and the third insulating film on the second insulating film, From the bottom of the mouth portion to expose the third insulating film is completely removed the fourth insulating film, wherein the side surface of the first opening, the said fourth insulating film 3
The first insulating film and the third insulating film are selectively removed while leaving an insulating side wall made of the insulating film of FIG. A second opening having a second predetermined width larger than the predetermined width is formed in alignment with the first opening, and an edge of the first opening of the first semiconductor layer is formed. Forming a protrusion that protrudes into the second opening of the first insulating film, and the third insulating film below the fourth insulating film on a side surface of the first opening; Exposing a lower portion of a side surface of the protruding portion of the first semiconductor layer exposed on a side surface of the first opening, and exposing the lower portion of the first semiconductor layer on a side surface of the first opening. The single crystal semiconductor substrate exposed on a lower portion of the side surface of the protruding portion of the first semiconductor layer and in the second opening; A semiconductor is grown on the part of the main surface and a second semiconductor layer made of a reverse conductivity type single crystal semiconductor is formed on the part of the main surface of the single crystal semiconductor substrate. Forming a third semiconductor layer made of a reverse conductivity type single crystal semiconductor reaching an end of the second semiconductor layer from a lower surface of the protruding portion of the first semiconductor layer and an end of the second semiconductor layer from a lower portion of the side surface; A fourth semiconductor layer of one conductivity type formed in an upper surface region of the first semiconductor layer and a fifth semiconductor layer formed on an upper surface of the fourth semiconductor layer. A manufacturing method is provided.

According to an eighth feature of the present invention, a first insulating film is formed so as to cover a main surface of a single-conductivity type single crystal semiconductor substrate, and a reverse insulating film partially covering the first insulating film is formed. A conductive semiconductor layer is formed and monocrystallized, a monocrystallized first semiconductor layer is formed, a second insulating film covering the first semiconductor layer is formed, and the monocrystallized first semiconductor layer is formed. Forming a first opening having a first predetermined width so as to penetrate the semiconductor layer and the second insulating film, and selectively removing the first insulating film in the first opening; Forming a second opening having a second predetermined width larger than the first predetermined width in the first insulating film in alignment with the first opening; A part of the main surface of the substrate is exposed, and an edge of the first opening of the first semiconductor layer is connected to the second opening of the first insulating film. The single crystal is formed so as to form a protruding portion, and on the side surface of the protruding portion of the first semiconductor layer exposed on the side surface of the first opening, and on the side surface of the protruding portion in the second opening. A second semiconductor layer made of a reverse conductivity type single crystal semiconductor on the part of the main surface of the single crystal semiconductor substrate by growing a semiconductor on the part of the main surface of the semiconductor substrate; And forming the second semiconductor layer from the lower surface and the side surface of the protruding portion of the first semiconductor layer.
Forming a third semiconductor layer made of a reverse conductivity type single crystal semiconductor reaching an end of the semiconductor layer, and forming a fourth semiconductor layer of one conductivity type formed in an upper surface region of the second semiconductor layer; A method for manufacturing a semiconductor device, comprising forming a fifth semiconductor layer formed on an upper surface of a fourth semiconductor layer.

According to a ninth feature of the present invention, a first insulating film is formed so as to cover a main surface of a single conductivity type single crystal semiconductor substrate, and partially covers the first insulating film. Forming a single-crystallized opposite-conductivity-type first semiconductor layer having a {100} plane parallel to the main surface, the second semiconductor film having a second insulating film having the same pattern as the upper surface thereof; Forming a third insulating film covering the second insulating film;
A first opening having a first predetermined width is formed in the semiconductor layer and a second opening larger than the first predetermined width aligned with the first opening in the second insulating film. Forming a second opening having a predetermined width, and exposing the {111} plane to the surface of the first semiconductor layer exposed on the side of the first opening by heat treatment; A third layer having a third predetermined width smaller than the second predetermined width on the lower side and a width substantially equal to the second predetermined width on the upper side;
Is formed, the first insulating film below the third opening is removed, and the first insulating film is laterally etched to form a fourth opening in the first insulating film. Forming a part of the main surface of the single-crystal semiconductor substrate, and a part of the lower surface of the first semiconductor layer, and exposing the upper surface of the fourth opening. A reverse conductive layer that grows a semiconductor on a lower surface of the first semiconductor layer and on a main surface of the single crystal semiconductor substrate exposed in the fourth opening, and fills at least the inside of the fourth opening; Forming a third semiconductor layer made of a single-crystal semiconductor of a type, forming a fourth semiconductor layer of one conductivity type formed in an upper surface region of the second semiconductor layer, and forming an upper surface of the fourth semiconductor layer; And a method of manufacturing a semiconductor device, characterized by forming a fifth semiconductor layer. It is.

According to a tenth feature of the present invention, a first insulating film is formed so as to cover a main surface of a single conductivity type single crystal semiconductor substrate, and a single insulating film partially covering the first insulating film is formed. Forming a crystallized first semiconductor layer of a reverse conductivity type, forming a third insulating film covering the first semiconductor layer, and forming a first insulating film having a first predetermined width on the second insulating film; Is formed to expose a part of the surface of the first semiconductor layer, the first semiconductor layer is etched by a wet method, and the first semiconductor layer is formed on the lower side of the first semiconductor layer. A second opening having a second predetermined width smaller than the predetermined width and having a width substantially equal to the second predetermined width is formed on the upper side, and the first insulating film below the second opening is formed. Removing and etching the first insulating film laterally to form a third opening in the first insulating film; A part of the main surface of the single crystal semiconductor substrate is exposed, and a part of the lower surface of the first semiconductor layer is exposed. A reverse conductivity type single crystal semiconductor in which a semiconductor is grown on a lower surface and on a main surface of the single crystal semiconductor substrate exposed in the third opening to fill at least the third opening; A fourth semiconductor layer of one conductivity type formed on the upper surface region of the second semiconductor layer and a fifth semiconductor layer formed on the upper surface of the fourth semiconductor layer. A method for manufacturing a semiconductor device, comprising forming a semiconductor layer.

[0025]

The present inventor has studied the causes of the above-mentioned problems in the prior art. Hereinafter, a vertical bipolar transistor will be described as an example, but the same applies to a field effect transistor.

In the manufacturing process of the vertical bipolar transistor shown in FIG. 30, a first opening 101 is formed to penetrate silicon nitride film 8 and polysilicon film 7, and a second opening 101 is formed to penetrate silicon oxide film 6. In the state where the opening 102 is formed and the epitaxial layer 3 for the collector is exposed, the p ⁺ type single crystal silicon single crystal intrinsic base region 11 is formed on the epitaxial layer 3 for the collector by the vapor phase epitaxial growth method. A p ⁺ -type polysilicon film 12 is formed on the side surface and the exposed lower surface of the base electrode polysilicon film 7. Since the collector epitaxial layer 3 is a single crystal, the single crystal intrinsic base region 11 formed on the collector epitaxial layer 3 is similarly a single crystal. On the other hand, since the base electrode polysilicon film 7 is polycrystalline, the p ⁺ type silicon film 12 formed on the side surface and the exposed lower surface of the base electrode polysilicon film 7 is also polycrystalline. Further, after a silicon oxide film is formed so as to cover the whole, the silicon oxide film 13 is formed so as to cover the side wall of the opening by etching back by anisotropic etching. Thereafter, n ⁺⁺ polysilicon is deposited and further patterned to form a polysilicon film 16 for the emitter electrode. Thereafter, by performing a heat treatment, the n-type impurities in the polysilicon film 16 for the emitter electrode diffuse into the surface region of the single-crystal intrinsic base region 11 to form the n ⁺ -type single-crystal emitter region 15.

Here, considering the base electrode polysilicon film 7, no addition (= no impurity is added)
If the polysilicon is deposited at a temperature range of about 600-650 ° C., the grain size of the polysilicon is between 0.03 and
It is reported that the orientation is {110}. In other words, preferentially $ 1 parallel to the substrate surface
A 10 ° plane is formed. Then, when a heat treatment for activating the impurity atoms is performed after the introduction of the impurity, the grain size becomes 0.5 to 3 μm, which is larger than the initial size. On the other hand, as in the case where the first opening 101 is formed, the crystal plane orientation of the side surface formed by dry-etching the polysilicon substantially perpendicularly is a plane orientation perpendicular to the {110} plane. If you consider the next plane orientation, it is infinite.

On the other hand, various dimensions are required for the dimensions of the emitter region in the circuit configuration. For example, the dimension in the longitudinal direction of the emitter is about 2 μm to 16 μm or 32 μm.
Sometimes used up to the size of. Moreover, it is desirable in circuit design that the effective emitter area corresponds to the designed emitter area, and that the collector current increases and decreases in proportion to the effective emitter area. Further, it is desirable that substantially the same collector current flows in transistors having the same dimensions.

Therefore, when the size of the emitter in the longitudinal direction is small, not a large number of a plurality of crystal grains (grains) are formed on the inner surface of the opening 101 formed in the polysilicon film 7.
Are exposed. As described above, the crystal plane orientation of the surface of each crystal grain exposed on the inner surface of the opening 101 is {11}.
Although the plane orientation is perpendicular to the 0 ° plane, if different plane orientations are taken into consideration, the orientation differs in the same opening 101, and if each opening 101 is compared, it differs for each opening 101. The epitaxial growth of silicon differs considerably depending on the crystal plane orientation of the seed plane for growth. Therefore, if the comparison is made for each opening 101, when the first opening 101 is small, the crystal plane orientation exposed on the inner surface of the opening 101 is different. As a result, from the side surface of the base electrode polysilicon film 7 and the exposed lower surface, The protruding dimension of the growing polysilicon film 12 greatly differs for each opening 101.

That is, in the conventional example, when the intrinsic base region is formed by the selective epitaxial growth method, since the side surface of the base electrode polysilicon is completely exposed, the side surface of the base electrode polysilicon is formed. The thickness of the polysilicon film 12 that has grown in each of the openings 101 varies from one opening 101 to another. After that, after the silicon oxide film is formed so as to cover the entire surface, the silicon oxide film 13 is etched back by anisotropic etching to form the silicon oxide film 13 so as to cover the side wall of the opening. In the size of the opening defined by the above, there is also variation for each opening 101. That is, the exposed surface area of the single crystal intrinsic base region 11 exposed by the opening defined by the silicon oxide film 13 varies. Then, by heat treating the n ⁺⁺ polysilicon n ⁺⁺ type emitter electrode polysilicon film 16 which is formed by further patterning by depositing, the n-type impurity in the emitter electrode polysilicon film 16, Since n ⁺ -type single-crystal emitter region 15 is formed by diffusing into the surface region of single-crystal intrinsic base region 11,
The size of the n ⁺ -type single crystal emitter region 15 also
Variations occur every time. That is, the emitter area varies. As a result, the electrical characteristics of the vertical bipolar transistor having the above configuration vary, and the above-described ΔVB increases.

Therefore, the present inventor has proposed a method of manufacturing a transistor and a structure of a transistor having less variation in electrical characteristics without being affected by variation in selective epitaxial growth of a polycrystalline film from the side surface of polysilicon for a base electrode. It was invented. That is, as in the first and sixth aspects of the present invention, an insulating side wall is formed on a part of the side surface of the first semiconductor layer corresponding to the base electrode polysilicon, and the thickness of the insulating side wall (= Wsw ) Grown on the side surface of the electrode polysilicon (corresponding to the third semiconductor layer)
(Wsw> Wcrystal) than the maximum thickness (= Wcrystal) in the range of thickness variation.

Due to this feature, even if the thickness of the polycrystalline film epitaxially grown from the side surface of the base electrode polysilicon film varies, that is, the polycrystalline film toward the inside of the opening formed in the base electrode polysilicon film. Even if the protrusion size of the film varies, the size of the opening on the intrinsic base region (corresponding to the fourth semiconductor layer) where the polysilicon for the emitter electrode (corresponding to the fifth semiconductor layer) is deposited is:
Variations in the emitter area are not limited by the protrusion of the polycrystalline film toward the inside of the opening formed in the base electrode polysilicon film, but by the side wall formed on a part of the side surface of the base electrode polysilicon. It is greatly suppressed, and the effect on electrical characteristics is reduced. Further, as in the second to fifth and seventh to tenth features of the present invention, the first semiconductor layer corresponding to the base electrode polysilicon is monocrystallized. As a result, variation in the protrusion dimension of the semiconductor film toward the inside of the opening formed in the polysilicon film for the base electrode is suppressed, variation in the emitter area is significantly suppressed, and the influence on the electrical characteristics is reduced.

The thickness WB of the single crystal film for the intrinsic base region formed by the selective crystal growth method is made larger than the distance d between the upper surface of the epitaxial layer for the collector and the lower surface of the polysilicon film for the base electrode. By [WB>
d), the intrinsic base and the polysilicon film for the base electrode can be connected only by growing a single crystal. Therefore, it is possible to avoid the problem that the intrinsic base is not connected to the base electrode polysilicon film as in the case of the vertical bipolar transistor disclosed in Japanese Patent No. 2555133. Furthermore, an insulating film (other than silicon nitride) that first covers the side surface of the base electrode polysilicon film which is simultaneously etched when the surface of the collector epitaxial layer is exposed by etching the insulating film immediately before selective crystal growth. By setting the relationship between the film thickness x and WB and d as d <WB <d + x, the single crystal film for the intrinsic base region does not directly contact the silicon nitride film.
It is possible to prevent an increase in leakage current as in the case of the vertical bipolar transistor disclosed in Japanese Patent Publication No. 551353.

Further, the fourth, fifth and ninth and tenth aspects of the present invention are described.
As described above, when the shape of the opening formed in the first semiconductor layer is expanded upward in a funnel shape,
Even when the emitter is miniaturized, the step coverage when depositing the polysilicon for the emitter electrode can be improved. Therefore, it is possible to prevent the occurrence of voids of the polysilicon for the emitter electrode in the emitter opening, thereby preventing the emitter parasitic resistance from increasing. Further, since the emitter electrode polysilicon film is formed thick at the upper end of the emitter opening, the emitter parasitic resistance can be reduced.

[0035]

Embodiments of the present invention will be described below with reference to the accompanying drawings. First, np implementing the present invention
I will explain about n-type bipolar transistor,
The present invention is also applicable to a pnp type bipolar transistor. As will be described later as another embodiment, the present invention is also applicable to a field effect transistor such as a JFET.

FIG. 1 is a longitudinal sectional view of a semiconductor device according to a first embodiment of the present invention. A few μm of the surface of the p ⁻ -type silicon substrate 1 having a crystal orientation of (100) and a resistivity of 10 to 20 Ω · cm.
Two types of buried layers are formed in the region having the thickness of m. The two types of buried layers are n ⁺ type buried layers 2-a
And ap ⁺ type buried layer 2-b for a channel stopper
And exist separately from each other. The n ⁻ -type collector epitaxial layer 3 is provided on the surface of these buried layers and on the surface of the silicon substrate in a region where no buried layer exists.

During epitaxial growth, due to autodoping and diffusion from the buried layer to the growth layer, the impurities are slightly more diffused into the epitaxial layer than from the original buried layer region. If the effective thickness of the epitaxial layer for the collector is defined by the thickness of the region where the n-type impurity concentration is 5 × 10 ¹⁶ cm ⁻³ or less, the thickness of the epitaxial layer for the collector is about 0.60 μm. there were. LOCOS (LOCal Oxidation)
The silicon oxide film 4 formed by the (n of Silicon) method converts the collector epitaxial layer into a silicon oxide film to a depth reaching the p ⁺ -type buried layer 2-b.

By adding a high concentration of impurity to a part of the n ⁻ -type collector epitaxial layer, n
An n ⁺ -type collector lead-out region 5 connected to the ⁺ -type buried layer 2-a is formed. The portions described so far are collectively referred to as a silicon substrate 100, but the silicon substrate 100 may be regarded as a substrate. A silicon oxide film 6 is formed on a base 100, and ap ⁺ -type base electrode polysilicon film 7 is selectively formed thereon. The first opening 101 formed in the polysilicon film 7 for the base electrode and the second opening 102 formed in the silicon oxide film 6 expose the epitaxial layer 3 for the collector. The first opening 101 formed in the polysilicon film 7 protrudes horizontally from the end of the second opening 102 into the second opening.

The base electrode polysilicon film 7 is covered with a silicon nitride film 8. First opening 101
There is an insulating side wall formed by depositing a silicon oxide film 9 and a silicon nitride film 10 in this order. Second
The single crystal intrinsic base region 11 is located on the collector epitaxial layer 3 inside the opening 102. A p ⁺ -type polysilicon film 12 is formed below the side surface of the base electrode polysilicon film 7 (that is, a portion not covered by the side wall of the silicon oxide film 9). p ⁺ type polysilicon film 1
Numeral 2 connects between the base electrode polysilicon film 7 and the single crystal intrinsic base region 11. Intrinsic base region 11
In the upper central region, there is an n ⁺ -type single crystal emitter region 15.

The silicon oxide film 13 serves as a side wall of the opening. The region between the base and the n ⁺ -type buried layer in the collector epitaxial layer immediately below the base region is an n-type collector region 14 doped with an impurity at a higher concentration than the original impurity concentration of the collector epitaxial layer. There is. N ⁺ -type single-crystal emitter region 1 of single-crystal silicon
The emitter electrode polysilicon film 16 exists on 5. All of these regions are covered with the silicon oxide film 17.

Further, contact holes are formed penetrating the silicon oxide film 17 and further penetrating the silicon nitride film 8 and the silicon oxide film 6 at some places. A metal film is formed and further patterned to form an aluminum alloy electrode for emitter 18-a, an aluminum alloy electrode for base 18-b, and an aluminum alloy electrode for collector 18-c.
Is formed. These aluminum alloy electrode 18-a for emitter and aluminum alloy electrode 18-b for base
The collector aluminum alloy electrode 18-c is in contact with the emitter electrode polysilicon film 16, the base electrode polysilicon film 7, and the collector extraction region 5, respectively.

The method of manufacturing the semiconductor device according to the first embodiment will be described below with reference to FIGS.
FIG. 2 is a vertical cross-sectional view at the stage when the silicon oxide film 6 is formed on the base 100. First, n ⁺ type buried layers 2-a and p ^{+
A +} -type buried layer 2-b is formed. The method is as follows, on a silicon substrate 1 by a normal CVD method or a thermal oxidation method.
A silicon oxide film (not shown) is formed. The thickness of the silicon oxide film is several 100 nm (from 300 nm to 70 nm).
A thickness of 0 nm is suitable, for example, 500 nm is described below as an example). After forming the silicon oxide film, a photoresist is patterned on the silicon oxide film by a normal photolithography method.

Using this photoresist as a mask material, the silicon oxide film on the surface is selectively removed by an ordinary wet etching method (ie, using an HF-based solution). Subsequently, after removing the photoresist using an organic solution, the silicon substrate surface inside the silicon oxide film opening is oxidized by 20 nm to 50 nm for alignment in the photolithography process, and then silicon is implanted by arsenic ion implantation. Arsenic is selectively introduced into the silicon substrate where the oxide film is thin.

The acceleration energy of the ion implantation needs to be low enough not to penetrate the silicon oxide film serving as the mask material. The amount of the impurity to be ion-implanted is suitably set so that the impurity concentration of the buried layer is on the order of 1 × 10 ¹⁹ cm ⁻³ , the energy is 70 keV, and the dose is 5 × 1.
0 ¹⁵ cm ^-2 (implantation conditions include, for example, an energy of 50 keV to 120 keV and a dose of 1 × 10
^{15 to} 2 × 10 ¹⁶ cm ⁻² is appropriate). Next, a treatment is performed at a temperature of 1000 ° C. to 1150 ° C. (here, heat treatment is performed in a nitrogen atmosphere at 1100 ° C. for 2 hours) in order to recover damage, activate arsenic, and press in during ion implantation. . Thus, an n ⁺ type buried layer 2-a is formed.

The silicon oxide film having a thickness of 500 nm is entirely removed with an HF solution, and a silicon oxide film having a thickness of, for example, 100 nm (appropriate thickness of 50 nm to 250 nm) is formed by oxidation, patterning of a photoresist, and ion implantation of boron. (Energy 50 keV, dose 1 × 10 ¹⁴ c
m ^-2 ), heat treatment for resist removal and activation (1000
C. for 1 hour in a nitrogen atmosphere) to form ap ⁺ type buried layer 2-b for a channel stopper.

Next, after the silicon oxide film is completely removed,
N ^- type silicon epitaxial layer 3 by a usual method
To form The growth temperature is preferably 950 ° C. to 1050 ° C., and SiH ₄ or SiH ₂ Cl ₂ is used as a source gas, and PH ₃ is used as a doping gas. The collector epitaxial layer 3 is 5 × 10 ^{15 to} 5 × 10 ¹⁶ cm
^-3 impurities (= phosphorus) and thickness 0.3μm ~
1.3 μm is appropriate. Here, 5 × 10 ¹⁶ cm ⁻³
The thickness of the following concentrations was about 0.6 μm. Thus, the collector epitaxial layer 3 is formed on the buried layer.
To form

Next, a silicon oxide film 4 is formed by the LOCOS method for element isolation. First, the epitaxial layer 3
A thermal oxide film (not shown) having a thickness of 20 nm to 50 nm is formed on the surface of the substrate, and a silicon nitride film (not shown) having a thickness of 70 nm to 1 nm is formed.
It is formed to a thickness of 50 nm. Subsequently, a photoresist (not shown) is deposited, the photoresist is patterned by photolithography, and the silicon nitride film and the silicon oxide film are selectively removed by dry etching using the photoresist as a mask.

Subsequently, the collector epitaxial layer 3
Is also etched to obtain a table of the epitaxial layer 3 for the collector.
A groove is formed on the surface. Groove depth (= silicon to be etched
Of the oxide film thickness formed by the LOCOS method.
Minutes are appropriate. After removing the photoresist,
Oxidation while the area is protected by the silicon nitride film.
As a result, a silicon oxide film for element isolation, ie, L
An OCOS oxide film 4 is formed. LOCOS oxide film
P for channel stopper⁺ Reached the mold buried layer 2-b
Is suitable, for example, 300 nm to 1300
nm. Here, it was about 600 nm. Silico
The nitride film is removed by hot phosphoric acid. Next
N to reduce the⁺ Mold collector drawer area
5 is formed. Methods include diffusion and ion implantation.
To dope this region with phosphorus. That is,
In the lithography, only the collector opening area was opened.
A photoresist is formed and phosphorus is accelerated at an energy of 100k.
eV, dose 5 × 10¹⁵cm ^-2Ion implantation under the conditions
You.

After removing the photoresist, a heat treatment is performed in a nitrogen atmosphere at 1000 ° C. for 30 minutes for activation of the implanted phosphorus and recovery from damage due to ion implantation. The silicon substrate 100 is configured as described above. Next, the surface of the silicon substrate 100 is covered with the silicon oxide film 6. The film thickness is suitably about the same as the thickness of the intrinsic base, and is 50 nm here.

Next, as shown in FIG. 3, a polysilicon film is deposited. The thickness of the polysilicon film is 150 n
m-350 nm is suitable, here 250 nm. This polysilicon film is ion-implanted with boron. The implantation energy is low enough not to penetrate the polysilicon, and the dose needs to be high enough so that the impurity concentration becomes about 1 × 10 ²⁰ cm ⁻³ . Here, an implantation energy of 10 keV and a dose of 1
× 10 ¹⁶ cm ^-2 . Next, after depositing and patterning a photoresist, unnecessary polysilicon is removed by dry etching. Thus, the p ⁺ -type base electrode polysilicon film 7 is formed.

After a silicon nitride film 8 is formed on the entire surface including the base electrode polysilicon film 7, photolithography patterning for forming an opening is performed. That is, the silicon nitride film 8 is formed by LPCVD to about 30
0 nm is deposited (the thickness of the silicon nitride film is 100 nm
５００500 nm is appropriate). Next, after the photoresist is deposited, openings are formed by conventional photolithography in the portions of the photoresist that will form the future intrinsic base. Subsequently, the silicon nitride film 8 and the base electrode polysilicon film 7 are successively removed by anisotropic dry etching using the photoresist as a mask. Here, the opening formed by the base electrode polysilicon film 7 is referred to as a first opening 101.

The description will be continued with reference to FIGS. FIGS. 4A to 6B are diagrams illustrating only a region near the first opening 101 in an enlarged manner.
As shown in FIG. 4A, a silicon oxide film 9 is formed on the entire surface of the wafer by LPCVD. The thickness of the silicon oxide film is equal to or greater than the maximum thickness variation of the polycrystalline layer that grows on the side surface of the base electrode polysilicon when the intrinsic base is epitaxially grown. Here, it was about 50 nm. Subsequently, a silicon nitride film 10 is formed by the LPCVD method. The thickness of the nitride film is 80
nm.

Next, as shown in FIG. 4B, the silicon nitride film 10 and the silicon oxide film 9 are etched back by anisotropic dry etching to expose the silicon oxide film 6. Here, a side wall composed of the silicon nitride film 10 and the silicon oxide film 9 remains on the side surface of the first opening 101.
The silicon nitride film 1 remaining on the side surface of the first opening 101
The thickness Wsw of the side wall composed of the silicon oxide film 9 and 0 is naturally larger than the thickness of the silicon oxide film 9 of about 50 nm. That is, the thickness Wsw of the side wall is larger than the maximum thickness variation of the polycrystalline layer that grows on the side surface of the base electrode polysilicon at the same time when the intrinsic base is epitaxially grown.

Further, as shown in FIG. 5A, the silicon oxide film 6 is etched with an HF-based solution to expose the collector epitaxial layer 3. At this time, the silicon oxide film 9 is also etched, and the lower portion of the side surface of the base electrode polysilicon film 7 is exposed. By this etching, the silicon oxide film 6 retreats in the lateral direction from the end surface of the base electrode polysilicon film 7 (that is, the first opening 101). The end face of the silicon oxide film 6 is the second opening 102 described above.

Next, an intrinsic base is formed by a selective crystal growth method. FIG. 5B is a cross-sectional view of a stage during the formation of the intrinsic base by the selective crystal growth method. As the growth method, LPCVD method, gas source MB
The E method is also possible, but here, UHV (Ultra
(High Vacuum) / CVD method will be described as an example. An example of the condition is that the substrate temperature is 605 ° C. and the flow rate of Si ₂ H _{6 is 3} sccm, and silicon doped with low-concentration boron is selectively grown. At this time, the p ⁺ -type polysilicon film 12 is removed from the side and lower surfaces of the base electrode polysilicon film 7.
a grows. On the other hand, a p ⁺ type single crystal silicon film 11a grows on the exposed portion of the silicon collector layer 3.

FIG. 6A shows a single crystal intrinsic base region 11 and ap ⁺ type polysilicon film 12 connecting the intrinsic base region 11 to the base electrode polysilicon film 7 by a selective crystal growth method. It is sectional drawing of the stage which performed. P ⁺ -type polysilicon film 12 grown from the side and bottom surfaces of base electrode polysilicon film 7, and silicon collector layer 3
Are connected to each other as a result of the growth.
The concentration of boron as an impurity is, for example, 5 × 10 ¹⁸
cm ^-3 , and the thickness of the intrinsic base region 11 is, for example, 6
0 nm. On the other hand, the average thickness of the p ⁺ -type polysilicon film 12 in which the thickness varies due to the growth from the polycrystalline surface is, for example, 40 nm.

Thereafter, a silicon oxide film having a thickness of 100 nm is formed on the surface including the single crystal intrinsic base region 11 by LPCVD. Subsequently, anisotropic dry etching is performed to form a silicon oxide film 13 having a thickness of about 100 nm as a side wall inside the opening as shown in FIG. Next, phosphorus is ion-implanted to form an n-type collector region 14 immediately below the intrinsic base region, as shown in FIG. An example of phosphorus implantation conditions is an acceleration energy of 200 keV,
The dose amount was 4 × 10 ¹² cm ⁻² .

Subsequently, about 250 nm of phosphorus-added polysilicon is deposited by LPCVD. Further, the polysilicon is patterned by photolithography and anisotropic dry etching. In this way, as shown in FIG. 9, n ⁺⁺ type emitter electrode polysilicon film 16
Is formed. By diffusing impurities contained in the polysilicon film 16 for the emitter electrode into the surface region of the intrinsic base region 11, an n ⁺ -type single-crystal emitter region 15 is formed.

Subsequently, the entire silicon wafer is
Cover with 7. Further, as an opening for forming a metal electrode, an opening reaching the polysilicon film 16 for the emitter electrode, the polysilicon film 7 for the base electrode, and the collector lead-out region 5 is formed by photolithography and anisotropic dry etching. After the removal of the photoresist, the aluminum alloy electrode 18-a for the emitter and the aluminum alloy electrode 18-a for the base can be formed by patterning the aluminum alloy by sputtering or photoresist and dry etching.
b, the collector aluminum alloy electrode 18-c is formed, and the semiconductor device of FIG. 1 is obtained.

Here, reference is made to FIG. 7 and FIG. FIG.
FIG. 8 is a plan view of a grain boundary (crystal grain boundary) of polysilicon for a base electrode, and FIG.
For the planar arrangement of the grain boundary shown in
FIG. 3 is a diagram showing a positional relationship of a first opening 101.

The side surface of the first opening 101 is arranged so as to cross several grain boundaries. That is, different crystal plane orientations appear on the side surface of the first opening 101 in different grains (crystal grains). Therefore, the thickness of the p-type polysilicon film 12 grown from the side surface and the lower surface of the base electrode polysilicon film 7 is affected by the crystal plane orientation that appears on the side surface of the first opening 101, and When 101 is small, variation occurs for each opening. However, as shown in FIG. 4B, by etching back the silicon nitride film 10 and the silicon oxide film 9 by anisotropic dry etching, the silicon nitride film 10 and the silicon nitride film 10 remaining on the side surface of the first opening 101 are removed. The thickness Wsw of the side wall composed of the silicon oxide film 9 is varied from the p-type polysilicon film 12 grown from the side surface and the lower surface of the base electrode polysilicon film 7 exposed through the first opening 101. By making the thickness larger than the maximum value Wcrystal, the size of the opening defined by the silicon oxide film 13, that is, the contact area between the polysilicon film 16 for the emitter electrode and the single-crystal intrinsic base region 11 is reduced to the p-type polysilicon. Silicon film 1
2 can be made almost as designed without being affected by the variation of the film thickness.

Next, effects obtained by the above configuration will be described. This effect is, as described above, a reduction in variation in operating current. Hereinafter, numerical values are specifically shown. As described above, in a bipolar transistor circuit, a differential pair is formed by short-circuiting the emitters of adjacent transistors. Since the collector current of each transistor of the differential pair becomes the same, the voltage applied to the base is VB1,
VB2. This voltage difference, that is, VB1-VB2
Is defined as ΔVB. In order to stabilize the circuit operation, it is more advantageous that ΔVB is smaller. because,
This is because, when several stages of differential pairs are combined in the circuit, the input potential required for switching of the differential pairs varies.

Table 1 shows the magnitude (mV) of ΔVB in the case where the prior art and the present invention were used.
x2.0 μm, 0.6 × 8.0 μm, 0.6 × 16.0
The average value of 9 points on the wafer surface is shown for three types of μm. [Table 1] The magnitude of ΔVB (mV) Conventional technology Present invention 0.6 × 2.0 μm: 12.3 mV 0.7 mV 0.6 × 8.0 μm: 7.8 mV 0.8 mV 0.6 × 16.0 μm: 4.5 mV 6mV

It should be noted that the reason why the variation is slightly reduced as the size of the transistor of the prior art increases as the size increases is because the number of polysilicon crossing the first opening 101 increases, resulting in averaged characteristics. You. The thickness WB [= 60 nm] of the single crystal intrinsic base region 11 formed by the selective crystal growth method is equal to the distance d between the upper surface of the collector epitaxial layer 3 and the lower surface of the base electrode polysilicon film 7, ie, Film thickness of silicon oxide film 6 [= 50 n
m] and [WB> d], the intrinsic base and the polysilicon film for the base electrode can be connected only by growing a single crystal. Further, an insulating film, that is, a silicon oxide film 9 that first covers the side surface of the base electrode polysilicon film 7 that is simultaneously etched when the surface of the collector epitaxial layer 3 is exposed by etching the insulating film immediately before selective crystal growth. Since the relationship between the film thickness x [= 50 nm] and WB and d satisfies d <WB <d + x, the single crystal intrinsic base region 11 does not directly contact the silicon nitride film 10, so that the single crystal intrinsic base region 1
1 can be prevented from increasing due to direct contact between silicon nitride film 10 and silicon nitride film 10.

[Second Embodiment] (SiGe Base) Next, a second embodiment of the present invention will be described. The second embodiment is the same as the first embodiment except that the base is made of a SiGe base. Therefore, only steps specific to the second embodiment will be described below. FIG.
Corresponds to the first opening 101 of FIG. 9 in the first embodiment.
It is sectional drawing of the stage which expanded only the vicinity.

As shown in FIG. 5A, after the second opening 102 in which the end face of the silicon oxide film 6 has receded in the lateral direction, and the side wall composed of the silicon nitride film 10 and the silicon oxide film 9 are formed. Then, a p-type polycrystalline SiGe film 21 is formed which grows from the side surface and the lower surface of the base electrode polysilicon film 7. The formation of the p-type polycrystalline SiGe film 21 is performed by using UHV
/ CVD method was used. As growth conditions, a substrate temperature of 60
5 ° C., Si ₂ H ₆ flow rate 3 sccm, GeH ₄ flow rate 2 sc
cm is an example of the condition.

On the other hand, a SiGe alloy intrinsic base region 22 made of a p-type single crystal SiGe alloy is formed in an exposed portion of the silicon collector layer 3. These polycrystalline Si
The Ge film 21 and the SiGe alloy intrinsic base region 22 are in contact with each other. The details will be described. The intrinsic base region consists of two layers. By selective epitaxial growth method,
An undoped SiGe layer is grown on the silicon collector 3 inside the first opening 101. The Ge concentration was about 10%. The grown film thickness is about 25 nm. Of course, it is possible to increase the film thickness within a range in which no defect occurs by a heat treatment in a later step. In consideration of the fact that the lattice constant of the SiGe film does not match that of Si, instead of the SiGe film having a constant Ge concentration (for example, about 10%), the Ge content gradually increases to about 10%. May be used.

At this time, an undoped polycrystalline SiGe film is simultaneously formed on the lower and side surfaces of the p ⁺ -type polysilicon. By heat-treating this polycrystalline film to add boron at a high concentration, boron diffuses from the polysilicon film 7 to form a p ⁺ -type polycrystalline SiGe film. Next, the additive-free SiGe
A p ⁺ -type SiGe layer having a gradient Ge profile is formed on the film. Examples of a Ge profile, a boron concentration profile as an impurity, and a film thickness thereof will be described. Si
The thickness of the layer having a profile in which the Ge concentration in Ge decreases from 10% to 0% linearly toward the surface is 40 nm. This layer contains 5 × 10 ¹⁹ boron.
cm ^{-3 is} added. Thus, a thickness of 65 nm (= 2
An intrinsic base region 22 of (5 nm + 40 nm) is formed.

FIG. 10 is a cross-sectional view showing a state where the single crystal silicon film 23 and the polycrystalline silicon have been formed by the selective crystal growth method. That is, a single-crystal silicon film 23 made of pure Si containing no Ge and having a thickness of about 30 nm exists on the intrinsic base region 22. In FIG. 10, the intrinsic base region 22 originally having a two-layer structure is shown.
The polycrystalline layer 21 is shown as one layer for convenience.

Subsequently, the silicon oxide film 13 serving as a side wall
After depositing polysilicon with phosphorus added, FIG.
As shown in FIG. 0, the n ⁺ -type emitter electrode polysilicon film 16 is formed by patterning, and the n ⁺ -type single crystal emitter region 24 is formed in the single crystal silicon film 23.
Subsequent steps are the same as in the first embodiment.

[Third Embodiment] (JFET) Next, a third embodiment of the present invention will be described. The third embodiment relates to a junction FET. FIG. 11 is a plan view of a semiconductor device according to the third embodiment, FIG. 12 is a longitudinal sectional view taken along line BB of FIG. 11, and FIG. 13 is a line CC of FIG. FIG. 14 is a vertical cross-sectional view as seen from DD in FIG. 11. The direction of the current of the FET is in the horizontal direction of the paper in FIG. 12 and in the direction perpendicular to the paper in FIGS.

First, reference is made to FIG. In the third embodiment, the source electrode polysilicon film 32 and the drain electrode polysilicon film 33 are divided into two parts by gate patterning. Since only the main surface of the n ⁻ -type silicon substrate 31 inside the LOCOS end is exposed, the selective epitaxial growth grows only in the element formation region.

As shown in FIG. 12, a silicon oxide film 4 for element isolation is formed on the main surface of n ⁻ type silicon substrate 31 by the LOCOS method, and n ⁻ type silicon surrounded by silicon oxide film 4. The main surface of the substrate 31 is exposed to define an element formation region. N on which the silicon oxide film 4 is formed
^The structure formed on the main surface of the-type silicon substrate 31 is the same as the structure formed on the surface of the silicon substrate 100 in FIG. This corresponds to the formed structure. That is, the main surface of the silicon substrate 31 is covered with the silicon oxide film 6. It is appropriate that the film thickness is approximately the same as the thickness of the p-type channel silicon 34 described later. Next, a polysilicon film is deposited, and a p-type impurity such as boron is ion-implanted. Further, after depositing and patterning a photoresist, unnecessary polysilicon is removed by dry etching, and a source which has not been isolated yet becomes a polysilicon film 32 for the source electrode and a polysilicon film 33 for the drain electrode in the future. / Drain electrode polysilicon film is formed.

After a silicon nitride film 8 is formed on the entire surface including the source / drain electrode polysilicon film, a photoresist is formed. Next, an opening is formed in the photoresist at a portion where a p-type channel will be formed in the future by ordinary photolithography. Subsequently, using this photoresist as a mask, the silicon nitride film 8 and the underlying polysilicon film for source / drain electrodes are selectively removed continuously by anisotropic dry etching. Where the source /
The opening formed in the drain electrode polysilicon film is referred to as a first opening 101, as in the first embodiment. The first opening 101 allows the source / drain electrode polysilicon film to be converted to the source electrode polysilicon film 3.
2 and a polysilicon film 33 for a drain electrode.

As in FIG. 4A of the first embodiment,
A silicon oxide film 9 is formed on the entire surface of the wafer, and a silicon nitride film 10 is formed thereon. Next, similarly to FIG. 4B of the first embodiment, the silicon oxide film 6 is exposed by etching back the silicon nitride film 10 and the silicon oxide film 9 by anisotropic dry etching. As a result, the side wall including the silicon nitride film 10 and the silicon oxide film 9 and having the thickness Wsw remains on the side surface of the first opening 101 as in the first embodiment.

Further, as shown in FIG. 5A of the first embodiment, the main surface of the silicon substrate 31 is exposed by etching with an HF solution. At this time, the silicon oxide film 9 is also etched, and the lower portions of the side surfaces of the polysilicon film 32 for the source electrode and the polysilicon film 33 for the drain electrode are exposed. By this etching, the silicon oxide film 6 retreats in the lateral direction from the end faces (that is, the first openings 101) of the polysilicon film 32 for the source electrode and the polysilicon film 33 for the drain electrode. The end face of the silicon oxide film 6 is the second opening 102 described above.

Next, as in the first embodiment, the p ⁺ -type single-crystal silicon film 34 and the p ⁺ -type channel silicon film 34 are converted into the source electrode polysilicon film 32 by the selective crystal growth method. And p-type polysilicon films 35 and 36 connected to respective side surfaces of the drain electrode polysilicon film 33 are formed. After that, LPCVD
The silicon oxide film by the p-type channel silicon film 3
4 on the surface including the top. Subsequently, anisotropic dry etching is performed, and as in FIG. 6B of the first embodiment,
A silicon oxide film 13 is formed as a side wall inside the opening.

Subsequently, phosphorus-added polysilicon is deposited by LPCVD. Further, the polysilicon is patterned by photolithography and anisotropic dry etching. In this way, as shown in FIG.
The gate electrode polysilicon film 37 is formed. At this time, an n ⁺ -type single-crystal silicon film 38 is formed in the surface region of the p-type single-crystal silicon film 34 for contact with the gate-electrode polysilicon film 37. Subsequently, the entire wafer is covered with the silicon oxide film 17. Further, as an opening for forming a metal electrode, an opening reaching the polysilicon film 32 for the source electrode, the polysilicon film 37 for the gate electrode, and the polysilicon film 33 for the drain electrode is formed by photolithography and anisotropic dry etching. .

After removal of the photoresist, if aluminum alloy is sputtered and patterned by photoresist and dry etching, the aluminum alloy electrode 3 for the gate can be formed.
9-a, an aluminum alloy electrode 39-b for a source and an aluminum alloy electrode 39-c for a drain were formed.
1 semiconductor device. In the third embodiment, the variation in the dimensions of the n ⁺ -type single crystal silicon film 38 can be effectively suppressed, so that the variation in the characteristics of the junction FET can be minimized.

[Fourth Embodiment] Next, a fourth embodiment of the present invention will be described.
An embodiment will be described. The fourth embodiment is the same as the first embodiment except that the base electrode polysilicon film is formed of a single crystal.
Only steps specific to the above embodiment will be described. FIG. 15 is a vertical cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention, and FIG. 16 is a vertical cross-sectional view of main processes of manufacturing the semiconductor device according to the fourth embodiment. In FIGS. 15 and 16, parts corresponding to the parts shown in FIG.
The same reference numerals are given and the description is omitted.

The method of forming the base electrode single crystal silicon film 51 will be described below. The fourth embodiment of the present invention is the same as the first embodiment until the silicon oxide film 6 is formed on the silicon substrate 100. Next, as shown in FIG. 16, a third opening 503 is formed in the silicon oxide film 6 at a portion from which a collector electrode is drawn. After this opening is formed, amorphous (= amorphous) silicon is deposited.

Next, solid-phase epitaxial growth is performed using the collector epitaxial layer 3 inside the third opening 503 as a nucleus. As the solid phase epitaxial growth method, for example, a laser annealing method is used. In this manner, amorphous silicon within a distance of about 10 μm from the third opening 503 can be made into a silicon single crystal having the same crystal plane orientation as the substrate. The single-crystallized silicon film is patterned to form a single-crystal silicon film 51 for the base electrode and a single-crystal silicon film 5 for the collector electrode.
2 is formed.

Thereafter, a silicon nitride film 8 is formed on the entire surface, and if a photoresist patterning mask is designed, for example, as shown in FIG. The first opening 501 can be formed within. Therefore, the first opening 501 is
It is sufficiently contained in the single crystallized region. The first opening 501 penetrates through the silicon nitride film 8 and the single-crystal silicon film 51 for a base electrode. In other words, the side surface of the silicon film 51 exposed at the first opening 501 is a single crystal plane. After that, the second opening 50 is formed in the silicon oxide film 6.
2 is formed, and the lower surface of the base electrode silicon film 51 exposed in the second opening 502 is also a single crystal plane.

Since the subsequent steps are the same as those of the first embodiment, a detailed description is omitted, but the first and second openings 50 are omitted.
Since the surface of the single-crystal silicon film 51 exposed at 1, 502 is a single-crystal surface, the single crystal silicon film 51 for base electrode is not exposed at the time of selective epitaxial growth when the single-crystal intrinsic base region 11 is formed. Crystal silicon grows, and the single crystal intrinsic base region 11 and the base electrode single crystal silicon film 51 are connected by the p ⁺ type single crystal silicon film 53. Since the first opening 501 formed in the single-crystal silicon film for the base electrode as described above is a single crystal on all side surfaces, the thickness of the crystal grown on the side surface is uniform. In this case, the first opening 5
The thickness Wsw of the side wall composed of the silicon nitride film 10 and the silicon oxide film 9 remaining on the side surface of the first opening 501
It is not necessary to make the thickness Wcrystal of the silicon film grown from the side surface of the single crystal silicon film for the base electrode exposed by the above step larger than Wcrystal. Further, in some cases, the side wall composed of the silicon nitride film 10 and the silicon oxide film 9 remaining on the side surface of the opening 501 can be omitted.

[Fifth Embodiment] FIG. 17 is a longitudinal sectional view of a semiconductor device according to a fifth embodiment of the present invention.
An n ⁺ -type buried layer 2-a as a collector buried layer and a p ⁺ -type buried layer 2 for a channel stopper are provided on the surface of a p ⁻ -type silicon substrate 1 having a main surface having a (100) plane orientation.
-B are formed separately from each other. On these, an n ⁻ -type collector epitaxial layer 3 is formed. The silicon oxide film 4 for element isolation is formed by the LOCOS method so as to penetrate the epitaxial layer 3 for the collector and reach the p ⁺ -type buried layer 2-b. A silicon oxide film 6 is formed on these.

In the future, where the base and emitter are not formed, the concentration of the n ⁻ -type collector epitaxial layer 3 at a position overlapping with a part of the n ⁺ -type buried layer 2-a is increased.
^{A +} -type collector lead-out region 5 is formed. Portions below the silicon oxide film 6 are collectively referred to as a silicon substrate 100. An opening is formed in the silicon oxide film 6 on the collector lead-out region 5 and is in contact with the collector lead-out region 5 so as to be an n ⁺ -type single-crystal silicon film 5 for collector electrode.
2 are formed. On the silicon oxide film 6, p is provided to electrically connect the intrinsic base and the metal electrode.
^{A +} -type single crystal silicon film 51 for a base electrode is formed.

The silicon oxide film 21 covers the single-crystal silicon film 52 for the collector electrode and the single-crystal silicon film 51 for the base electrode. Further, a silicon nitride film 8 covers these and the silicon oxide film 6. A first opening 301 penetrating both the silicon nitride film 8 and the p ⁺ -type single-crystal silicon film 51 for base electrode is formed. A second opening 302 is formed in the silicon oxide film 6 under the first opening 301, and is formed on the collector epitaxial layer 3 inside the second opening 302 by a selective crystal growth method. A p-type single crystal intrinsic base region 11 is formed. The single crystal intrinsic base region 11
Is formed via a p ⁺ -type single-crystal silicon film 53 formed on an exposed portion in the opening of the single-crystal silicon film for base electrode 51.
It is connected to the base electrode single crystal silicon film 51.

An n-type silicon region 14 formed by selective ion implantation of phosphorus is provided in the collector epitaxial layer 3 under the first opening 301. The inside of the first opening 301 is highly doped with n-type (n
⁺⁺ ) An emitter electrode polycrystalline silicon film 16 is formed, and an n ⁺ type single crystal emitter region 15 is formed in the surface region of the single crystal intrinsic base region 11 by impurity diffusion therefrom.

The whole is covered with a silicon oxide film 17 and is opened in the silicon oxide film 17.
Polysilicon film 16 for emitter electrode, single crystal silicon film 51 for base electrode, single crystal silicon film 5 for collector electrode
2. Tungsten electrodes 19-a, 19-b, 19 including a laminated barrier film of Ti and TiN inside the opening reaching
-C is formed. An aluminum alloy electrode for emitter 20-a, an aluminum alloy electrode for base 20-b, and an aluminum alloy electrode for collector 20-c are formed in contact with the tungsten electrode.

Next, main steps for fabricating the semiconductor device of the present invention will be described with reference to the drawings. FIG.
8 (a) completes element isolation and further forms amorphous S
It is a longitudinal cross-sectional view which shows the state at the stage of depositing i. Using a p ⁻ type silicon substrate 1 having a resistivity of about 10 to 20 Ω · cm and having a (100) plane orientation, an n ⁺ type buried layer 2-a and a p ⁺ type buried in an island shape on the surface of this substrate. Layer 2-
b is formed. As a formation method, formation is performed by selectively diffusing (ion implantation or vapor phase diffusion) using a mask material (insulating film or photoresist). That is, a silicon oxide film of about 500 nm is formed on the substrate surface by a thermal oxidation method or a CVD method.
Form. An opening is formed in the silicon oxide film by ordinary photolithography and etching. The photoresist is removed and the silicon surface at the bottom of the opening is further oxidized to 20
A thermal oxide film of about nm is formed. Then, arsenic is, for example, accelerated energy = 50 keV, dose amount = 1 × 10
Ion implantation is performed under the condition of ¹⁶ cm ⁻² , and a treatment is performed at 1100 ° C. for 2 hours. As a result, an n ⁺ -type buried layer 2-a is formed in the region at the bottom of the opening.

Subsequently, buffered hydrofluoric acid (B) which is a mixed solution of a buffer solution of ammonium fluoride and hydrofluoric acid is used.
By HF), the entire silicon oxide film is removed. Next, a silicon oxide film of about 100 nm is deposited by a CVD method, a photoresist mask is formed using a normal photolithography method, and boron is
For example, acceleration energy = 70 keV, dose = 1 ×
Ion implantation is performed under the condition of 10 ¹³ cm ^-2 . The photoresist was removed, and a heat treatment was performed at 1000 ° C. for one hour in a nitrogen atmosphere to activate the implanted ions. Subsequently, the silicon oxide film on the surface is entirely removed with a BHF solution.

On the silicon substrate on which the buried layers 2-a and 2-b are formed, n ⁻ -type silicon is epitaxially grown by a normal low-pressure epitaxial growth method to form the collector epitaxial layer 3. After that, LOC
By the OS method, a silicon oxide film 5 penetrating through the collector epitaxial layer 3 and reaching the p ⁺ -type buried layer 2-b is formed. After depositing a silicon oxide film 6 thereon, an opening is formed on the collector epitaxial layer which is a collector extraction region of the silicon oxide film 6. Subsequently, amorphous silicon is deposited in an ultra-high vacuum to form an amorphous silicon film 50 a on the silicon oxide film 6.

FIG. 18B is a longitudinal sectional view showing a state in which amorphous silicon is grown on single crystal silicon in a solid phase. First, solid phase growth of amorphous silicon is performed on single crystal silicon. The processing temperature is suitably from 575 ° C. to 600 ° C., and the time is about 10 to 20 hours. Details of these conditions are described in the following two papers. H. Ishiwara et al., “Lateral solid phase epitaxy
of amorphous Si filmson Si substrates with SiO ₂ pa
tterns, "Appl. Phys. Lett., vol. 43, p. 1028 (1983). Y. Kunii et al.," Lateral solid-phase epitaxy of v.
acuum-deposited amorphous Si film over recessed Si
O ₂ patterns, "Jpn. J. Appl. Phys., Vol.24, p.L352
(1985). By this solid phase crystal growth process, the single crystal silicon film 50b is solid phase grown on the silicon oxide film from the opening end of the silicon oxide film to a distance of about 6 μm to 7 μm. A portion farther than this distance becomes a polycrystalline silicon film 50c having a random crystal orientation. The (100) plane is exposed on the surface of the single crystal silicon film 50b.

FIG. 19A is a longitudinal sectional view showing a state in which single crystallized silicon is doped. By normal photolithography and dry etching,
Pattern the silicon film. The surface of the silicon film patterned by the silicon nitride film deposited by the LPCVD method is covered. By photolithography and anisotropic dry etching, an opening is formed in the silicon nitride film immediately above the single-crystal silicon film 50b in the region where the base extraction electrode is to be formed in the future. Boron is diffused from the gas phase to form a p ⁺ -type single crystal silicon film for base electrode 51. Continued
After once removing the silicon nitride film with heated phosphoric acid, the surface of the silicon film is covered again with a silicon nitride film deposited by LPCVD. An opening is formed in the silicon nitride film immediately above the opening of the silicon oxide film 6 by photolithography and anisotropic dry etching. Then, phosphorus is diffused from the gas phase to form an n ⁺ -type single-crystal silicon film 52 for the collector electrode, and phosphorus is also diffused into the collector epitaxial layer 3 to form the n ⁺ -type collector lead-out region 5. . Portions below the silicon oxide film 6 are collectively referred to as a silicon substrate 100 (see FIG. 17). The impurity may be doped by an ion implantation method.

FIG. 19B is a longitudinal sectional view showing a stage in which an opening for positioning a region where a base and an emitter are to be formed in the future is formed. A silicon nitride film 8 is deposited by the LPCVD method. Then, the silicon nitride film on the base formation region is removed by photolithography and anisotropic dry etching. Subsequently, anisotropic dry etching is performed to selectively remove the single crystal silicon film 51 for the base electrode. Then, a first opening 301 penetrating both films is formed. After that, the photoresist is removed.

FIG. 20A is a longitudinal sectional view showing a stage where the silicon oxide film at the bottom of the first opening 301 is removed. B
The silicon oxide film 6 at the bottom of the first opening 301 is removed with an HF solution, and further etched laterally by a predetermined distance to form a second opening 302 in the silicon oxide film 6.
Thereby, a part of the bottom surface of the base electrode single crystal silicon film 51 is exposed in the second opening 302. FIG.
(B) is a longitudinal sectional view showing a stage in which the base region is epitaxially grown. Using ultra-high vacuum CVD equipment
Single crystal intrinsic base region 1
Form one. At this time, silicon crystal grows simultaneously from the side surface and the lower surface of the base electrode single crystal silicon film 51, and ap ⁺ type single crystal silicon film 53 is formed.

FIG. 21A is a longitudinal sectional view showing a state at the stage when the impurity concentration of the collector region is increased. LP
After a silicon oxide film (54) is formed by the CVD method, phosphorus is ion-implanted to form an n-type collector region 1 in the collector epitaxial layer 3 immediately below the single crystal intrinsic base region 11.
4 is formed. Then, anisotropic dry etching and BH
By combining wet etching with F, side wall silicon oxide films 54 are formed on the side surfaces of silicon nitride film 8 and p ⁺ -type single crystal silicon film 53. FIG. 21 (b) is a longitudinal sectional view showing a state at the stage when the emitter polysilicon is formed. By arsenic highly doped polysilicon is deposited by the LPCVD method, and the polysilicon is patterned by photolithography and dry etching.
An n ⁺⁺ type polysilicon film 16 for an emitter electrode is formed. Subsequently, an n ⁺ -type single-crystal emitter region 15 is formed in the surface region of the intrinsic base region 11 by diffusion by heat treatment.

Subsequently, a silicon oxide film is deposited by the CVD method, the whole wafer is covered with the silicon oxide film 17, and the surface is flattened by the chemical mechanical polishing method (CMP). By photolithography and dry etching,
Polysilicon film 16 for emitter electrode, single crystal silicon film 51 for base electrode, single crystal silicon film 5 for collector electrode
2 is formed. Ti and TiN are sputtered to react Ti and Si to form Ti silicide. Subsequently, tungsten electrodes 19-a, 19-b and 19-c are formed inside the contact holes by depositing and etching back tungsten. Continued
In contact with the tungsten electrode by sputtering of aluminum alloy, photolithography, dry etching,
An aluminum alloy electrode for emitter 20-a, an aluminum alloy electrode for base 20-b, and an aluminum alloy electrode for collector 20-c are formed. By the above steps, FIG.
7 can be manufactured.

The emitter area on the mask in photolithography manufactured as described above = 0.6 × 8 μm
With respect to the transistor of m ^{2 and} the transistor formed by the conventional method (see FIG. 30), 13 points were measured in the wafer surface, and when a current of 1 mA flows, the variation of the voltage applied between the emitter and the base is compared. did. In the prior art, the standard deviation σ = 2.1 mV. On the other hand, in the first embodiment of the present invention, the standard deviation σ = 1.3.
mV. The reason for obtaining such an effect is that the silicon film grown on the side wall of the base electrode silicon film is monocrystallized, so that the thickness of the grown silicon film varies as compared with the case where the polysilicon film is grown. This does not occur, and the variation in the formed emitter area can be reduced.

[Sixth Embodiment] In the above-described fifth embodiment, there is still some variation in the emitter area. The cause of the variation is the deformation of the single-crystal silicon film for the base electrode in the pretreatment stage of the intrinsic base crystal growth. This deformation is due to the fact that a clean silicon surface is exposed on the crystal surface,
This occurs because atoms migrate to form a crystal plane having a low surface energy, and as a result, the crystal plane easily becomes a {111} plane. This phenomenon is particularly remarkable in ultra-high vacuum. According to the sixth embodiment described below, it is possible to reduce the variation caused by this phenomenon.

FIG. 22 is a longitudinal sectional view of a semiconductor device according to a sixth embodiment of the present invention. An n ⁺ -type buried layer 2-a and a p ⁺ -type buried layer 2-b are formed in an island shape on the surface of the p ⁻ -type silicon substrate 1 whose main surface is the (100) plane. ^- type collector epitaxial layer 3
Are formed. A silicon oxide film 4 penetrating through the n ⁻ -type collector epitaxial layer 3 and reaching the p ⁺ -type buried layer 2-b is formed by the LOCOS method.
A silicon oxide film 6 is formed on these.

Region where no base or emitter is formed
Where n⁺ N at a position overlapping a part of the mold buried layer 2-a^- 
This epitaxial layer 3
N with high concentration⁺ Collector extraction area 5 for mold
Are formed. The portion below the silicon oxide film 6
Collectively, it is referred to as a silicon substrate 100. Silicon oxide film
An opening is formed on the collector extraction region 5 of FIG.
, N ⁺ In contact with the collector drawer area 5 of the mold
A single crystal silicon film 52 for the data electrode is formed. Siri
On the oxide layer 6, an intrinsic base region and a metal electrode
Single crystal for base electrode for electrical connection between
A silicon film 51 is formed. For base electrode
The first opening 201 formed in the single crystal silicon film 51
The {111} plane of the single crystal silicon film 51 is exposed on the side surface.
ing.

The silicon oxide film 21 covers the single crystal silicon film 52 for the collector electrode and the single crystal silicon film 51 for the base electrode. Further, the silicon nitride film 8 covers these and the silicon oxide film 6. On the side surfaces of the openings formed in the silicon nitride film 8 and the silicon oxide film 21, and on the {11} of the base electrode single crystal silicon film 51
The side wall silicon nitride film 55 covers the side surface of the first opening 201 where the 1 ° surface is exposed. On the collector epitaxial layer 3 inside the second opening 202 formed in the silicon oxide film 6, a p-type single crystal intrinsic base region 11 formed by a selective crystal growth method is provided. The single crystal intrinsic base region 11 is connected to the single-crystal silicon film 51 for the base electrode.

On side wall silicon nitride film 55 in first opening 201, side wall silicon oxide film 56 is formed. An n-type collector region 14 in which phosphorus is selectively ion-implanted is formed in the n ⁻ -type collector epitaxial layer 3 below the first opening 201. In the first opening 201, there is an n ⁺⁺ type polysilicon film 16 for the emitter electrode surrounded by the side wall silicon oxide film 56, and by diffusion therefrom, an n ⁺ type polysilicon film is formed in the surface region of the intrinsic base region. A single crystal emitter region 15 is formed. The whole is covered with a silicon oxide film 17. Contact holes reaching the polysilicon film 16 for the emitter electrode, the single crystal silicon film 51 for the base electrode, and the single crystal silicon film 52 for the collector electrode are formed in the silicon oxide film 17. , TiN are formed, and tungsten electrodes 19-a, 19-b, 19-c are formed on the barrier film. An aluminum alloy electrode for emitter 20-a, an aluminum alloy electrode for base 20-b, and an aluminum alloy electrode for collector 20-c are formed in contact with the tungsten electrode.

Next, the main steps for fabricating the semiconductor device according to the present embodiment shown in FIG.
This will be described with reference to the drawings. FIG. 23A is a vertical cross-sectional view showing a state at the stage when the element isolation is completed. Resistivity, of about 10~20Ω · cm (100) plane orientation p ^-
Using the silicon substrate 1 and the same method as in the fifth embodiment, an n ⁺ -type buried layer 2-
a and ap ⁺ type buried layer 2-b are formed. Then, silicon is epitaxially grown thereon by a normal low-pressure epitaxial growth method to form an n ⁻ -type collector epitaxial layer 3.

The collector epitaxy is performed by the LOCOS method.
Penetrating through the Char layer 3⁺ Reaches the mold buried layer 2-b
After the silicon oxide film 5 is formed, a silicon
An oxide film 6 is formed. FIG. 23B shows an amorphous state.
FIG. 4 is a longitudinal sectional view showing a state in which silicon is deposited.
You. First, future photolithography
Where no base or emitter is formed, n⁺ Embedding type
A photoresist is applied only to a position overlapping a part of the only layer 2-a.
Opening, phosphorus, acceleration energy = 70 keV,
Dose amount = 1 × 10 ¹⁴cm^-2The ion implantation was performed under the following conditions.
After removing the photoresist, 1000 ℃, 1 minute rapid
Thermal annealing (Rapid Thermal Annnea)
l, RTA) to remove and activate crystal defects.
In the epitaxial layer 3 for collector, n⁺ Embedding type
N reaching the layer 2-a⁺ Collector extraction area 5 for mold
Was formed. Summarize the parts below the silicon oxide film 6
Therefore, it is referred to as a silicon substrate 100.

An opening is formed in the silicon oxide film 6 immediately above the n ⁺ -type collector lead-out region 5. Subsequently, amorphous silicon is deposited in an ultra-high vacuum to form an amorphous silicon film 50a. FIG. 23C is a longitudinal sectional view showing a state in which amorphous silicon is grown in solid phase on single crystal silicon. First, from 575 ° C to 600
The amorphous silicon film 50a is solid-phase grown on the single-crystal silicon film 50b by performing a heat treatment at a processing temperature of 10 ° C. for about 10 to 20 hours. By this heat treatment for solid-phase crystal growth, single-crystal silicon is solid-phase grown on the silicon oxide film to a distance of about 6 to 7 μm from the opening end of the silicon oxide film. The portion of the silicon film farther than this distance has a random crystal orientation.

FIG. 24A is a longitudinal sectional view showing a state in which a single-crystallized silicon film is doped with impurities. A nitride film is deposited by the LPCVD method, and the entire surface is covered with a silicon nitride film. An opening is provided in the silicon nitride film immediately above the n ⁺ -type collector lead-out region 5 by photolithography and anisotropic dry etching to diffuse phosphorus from the gas phase. Subsequently, the silicon nitride film is once removed with heated phosphoric acid, and a nitride film is deposited again by the LPCVD method, and the entire surface is covered with the silicon nitride film. An opening is formed in the silicon nitride film on the base electrode silicon film formation region by photolithography and anisotropic dry etching, and boron is diffused from the gas phase. After removing the silicon nitride film, a silicon oxide film 21 is deposited by a CVD method, and the silicon oxide film 21 and the single-crystal silicon film are patterned by photolithography and anisotropic dry etching so as to be in contact with the collector lead-out region 5. A single-crystal silicon film for base electrode 51 is formed on single-crystal silicon film for collector electrode 52 and silicon oxide film 6. At this time, assuming that the direction of the groove of the emitter opening (the direction perpendicular to the paper surface) is the <110> direction of the crystal of the single crystal silicon film 51, that is, the opening is rectangular (rectangular or square), and the four sides are [01].
1], [0-1-1], [0-11], and [01-1].

FIG. 24B is a sectional view showing a stage in which an opening for positioning a region where a base and an emitter region will be formed in the future is formed. A silicon nitride film 8 is deposited by the LPCVD method. The silicon nitride film 8 and the silicon oxide film 21 are formed by photolithography and anisotropic dry etching.
Are continuously and selectively removed. The silicon oxide film 21 is laterally etched with BHF. Subsequently, the single crystal silicon film for the base electrode is selectively removed by anisotropic dry etching, and the photoresist is removed.

FIG. 25A is a cross-sectional view showing a stage in which a specific crystal orientation is exposed on an opening side surface of a single crystal silicon film for a base electrode. The same process as the pretreatment for crystal growth by the molecular beam epitaxy method is performed. That is, an extremely thin (about 1 nm) silicon oxide film is chemically formed on the silicon surface. The formation method is described in detail in the following literature.・ A. Ashizaka, and Y. Shiraki, “Low temperature
surfacce cleaning of silicon and its application t
o silicon MBE, "J. Electrochem. Soc., vol.133, No.
4, pp.666-671, (1986). ・ Yasuhiro Shiraki, "Silicon Molecular Beam Epitaxy," Applied Physics, Vol. 57, No. 11, pp. 1620-1643, 1
988.

Immediately, the wafer is put into the ultrahigh vacuum apparatus.
Subsequently, the wafer is heated inside the apparatus. An appropriate heating temperature is about 850 ° C to 900 ° C. The time may be about 10 minutes. As a result, the protective ultra-thin silicon oxide film formed on the side surface of the p ⁺ -type single-crystal silicon film evaporates, and further heating continues, so that the plane orientation of the crystal surface changes and the first opening 201 The specific crystal plane orientation of the base electrode single crystal silicon film 51, that is,
The 1｝ surface is exposed. FIG. 25B is a longitudinal sectional view showing a state in which a side wall is formed in the opening with a silicon nitride film and the silicon oxide film at the bottom of the opening is removed. After a silicon nitride film is deposited on the entire surface by LPCVD, the silicon nitride film is etched back by anisotropic dry etching to form a sidewall silicon nitride film 55 on the side surface of the opening. Subsequently, with the BHF solution,
Silicon oxide film 6 exposed at the bottom of first opening 201
Is removed and laterally etched for a predetermined distance to form a second opening 202 in the silicon oxide film 6.

FIG. 26A is a longitudinal sectional view showing a state at the stage when the base region is epitaxially grown. Silicon is crystal-grown using an ultra-high vacuum CVD apparatus to form a p-type single crystal intrinsic base region 11. Then LP
A silicon oxide film is deposited by a CVD method, and phosphorus is ion-implanted to form an n-type collector region 14 in the collector epitaxial layer 3. Thereafter, the sidewall silicon oxide film 56 is formed by combining anisotropic dry etching and etching with BHF. FIG. 26 (b) is a longitudinal sectional view showing a state at the stage when the emitter polysilicon is formed.
Arsenic-doped polysilicon is deposited by the LPCVD method, and the polysilicon is patterned by photolithography and dry etching to form n.
^{An ++} type polysilicon film 16 for an emitter electrode is formed.
Subsequently, the intrinsic base region 1 is diffused by heat treatment.
An n ⁺ -type single-crystal emitter region 15 is formed in the surface region of No. 1.

Subsequently, a silicon oxide film is deposited by the CVD method, the whole wafer is covered with the silicon oxide film 17, and the surface is flattened by the chemical mechanical polishing method (CMP). By photolithography and dry etching,
Polysilicon film 16 for emitter electrode, single crystal silicon film 51 for base electrode, single crystal silicon film 5 for collector electrode
2 is formed. Ti and TiN are sputtered to react Ti and Si to form Ti silicide. Subsequently, tungsten electrodes 19-a, 19-b and 19-c are formed inside the contact holes by depositing and etching back tungsten. Continued
In contact with the tungsten electrode by sputtering of aluminum alloy, photolithography, dry etching,
An aluminum alloy electrode for emitter 20-a, an aluminum alloy electrode for base 20-b, and an aluminum alloy electrode for collector 20-c are formed. By the above steps, FIG.
2 can be manufactured.

The emitter area on the mask in photolithography manufactured as described above = 0.6 × 8 μm
respect m ² of the transistor and the transistor formed by the conventional method of the same size (see FIG. 30), it was measured 13 points in the wafer surface. The average value of the emitter resistance according to the prior art was 15Ω, whereas the average value of the emitter resistance according to the present embodiment was 9Ω. The reason why the effect of reducing the emitter resistance is obtained is that, in the present invention, at the stage of depositing the polysilicon for the emitter electrode, the shape of the opening is tapered so as to become narrower toward the bottom of the opening. is there. Moreover, since this taper has a specific crystal plane orientation, the reproducibility of the finished size is high.

[Seventh Embodiment] FIG. 27 is a longitudinal sectional view of a semiconductor device according to a seventh embodiment of the present invention.
FIGS. 28 and 29 are sectional views in the order of the manufacturing steps. The difference from the sixth embodiment is that the method of exposing the {111} plane to the side surface of the first opening 201 of single crystal silicon for a base electrode uses wet etching. Therefore, the following description focuses on differences from the sixth embodiment. FIG. 28A shows an opening for positioning a region where a base and an emitter region will be formed in the future.
FIG. 4 is a cross-sectional view showing a stage formed in FIG. As in the case of the sixth embodiment, after a single crystal silicon film 51 for a base electrode and a single crystal silicon film 52 for a collector electrode are formed on a silicon oxide film 6, the entire wafer is covered with a silicon nitride film 8. The silicon nitride film is selectively removed by photolithography and anisotropic dry etching. FIG. 28 (b)
FIG. 4 is a cross-sectional view showing a stage where a specific crystal orientation is exposed on the side surface of the opening of the single crystal silicon film for a base electrode. KOH
Thereby, the single crystal silicon film 51 is etched.
This etching liquid has a remarkable difference in the etching rate depending on the crystal plane orientation. That is, since the etching rate of the {111} plane is low, this plane orientation is finally exposed. In this embodiment, the etching is performed by using the wet method. However, since the etching rate of the {111} plane is extremely low, the processing accuracy of the opening width is maintained.

FIG. 29A is a longitudinal sectional view showing a state at the stage when the intrinsic base region is epitaxially grown.
A silicon oxide film is deposited by the LPCVD method. Next, the silicon oxide film is etched by a combination of anisotropic dry etching and wet etching with BHF. As a result, a side wall silicon oxide film 57 covering the upper portion of the first opening and the side surface of the silicon nitride film 8 is formed, and the silicon oxide film 6 at the bottom of the first opening 201 is removed. A second opening 202 exposing the surface of collector epitaxial layer 3 is formed.
Subsequently, silicon is selectively epitaxially grown,
A single crystal intrinsic base region 11 is formed. FIG. 29 (b)
FIG. 4 is a longitudinal sectional view showing a state at a stage when an emitter polysilicon is formed. A silicon oxide film is deposited by the LPCVD method, and anisotropic dry etching and wet etching with BHF are sequentially performed on the silicon oxide film, thereby forming a sidewall silicon oxide film 58 covering the sidewall silicon oxide film 57 and the intrinsic base region 11.
To form Then, a polysilicon film 16 for an emitter electrode and an n ⁺ -type single crystal emitter region 15 are formed by depositing, patterning, and heat-treating the emitter polysilicon by the LPCVD method. Hereinafter, the structure shown in FIG. 27 is obtained through a manufacturing process similar to that of the sixth embodiment.

As in the above-described fourth to seventh embodiments, the use of the electrode portion (single-crystal silicon film 51) which is monocrystallized is the same as that of the bipolar transistor and the third transistor of the second embodiment. It is needless to say that the present invention can be applied to the field effect transistor (FET) of the embodiment. Also,
In the above embodiment, the npn bipolar transistor and the p-channel JFET have been described. However, the present invention can be applied to the bipolar transistor and the FET whose conductivity types are all reversed. Further, in the embodiment, L is used for the element isolation method.
Although the OCOS method has been used, the present invention is not limited to this, and another isolation technique such as a trench method may be adopted.

[0118]

As described above, according to the present invention, even if the thickness of the polycrystalline film epitaxially grown from the side surface of the polysilicon film for the base electrode or the source / drain electrode varies, the emitter electrode The size of the opening on the intrinsic base region where the polysilicon film is deposited or on the channel layer where the polysilicon film for the gate electrode is deposited is within the opening formed in the polysilicon film for the base electrode or the source / drain electrode. The variation in the emitter area or the gate region area is large as a result of being regulated by the side wall formed on a part of the side surface of the polysilicon for the base electrode or the source / drain electrode, rather than the protrusion dimension of the polycrystalline film toward the substrate. And the influence on the electrical characteristics is reduced.

Further, according to the embodiment of the present invention in which the first semiconductor layer for the base electrode or the source / drain electrode is a single crystal semiconductor layer, the semiconductor layer epitaxially grown from the side surface of the first semiconductor layer. Becomes a single crystal, so that there is no variation in the grown film thickness. Therefore, there is no variation in the size of the opening on the intrinsic base region where the polysilicon film for the emitter electrode is deposited or on the channel layer where the polysilicon film for the gate electrode is deposited. Variation is greatly suppressed, and the effect on electrical characteristics is reduced.

Further, according to the embodiment in which the shape of the opening formed in the first semiconductor layer is expanded upward in a funnel shape, even when the emitter or the gate is miniaturized. That the step coverage at the time of depositing the polysilicon for the emitter electrode or the polysilicon for the gate electrode can be improved, and that the thickness at the upper end of the polysilicon film for the electrode can be increased. Thereby, it becomes possible to suppress the emitter parasitic resistance or the gate parasitic resistance.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a vertical cross-sectional view illustrating main processes for manufacturing the semiconductor device according to the first embodiment;

FIG. 3 is a longitudinal sectional view illustrating a step following FIG. 2 in a main step of manufacturing the semiconductor device according to the first embodiment;

FIG. 4 is a longitudinal sectional view illustrating a step following FIG. 3 in a main step of manufacturing the semiconductor device according to the first embodiment;

FIG. 5 is a longitudinal sectional view illustrating a step following FIG. 4 in a main step of manufacturing the semiconductor device according to the first embodiment;

FIG. 6 is a longitudinal sectional view illustrating a step following FIG. 5 in a main step of manufacturing the semiconductor device according to the first embodiment;

FIG. 7 is a diagram illustrating a grain boundary of polysilicon.

FIG. 8 is a diagram illustrating a grain boundary of polysilicon in which an opening is formed.

FIG. 9 is a longitudinal sectional view illustrating a step following FIG. 6 in a main step of manufacturing the semiconductor device according to the first embodiment;

FIG. 10 is a longitudinal sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 11 is a plan view of a semiconductor device according to a third embodiment of the present invention.

FIG. 12 is a longitudinal sectional view of the semiconductor device according to the third embodiment of the present invention, taken along line BB in FIG. 11;

FIG. 13 is a vertical cross-sectional view of the semiconductor device according to the third embodiment of the present invention, taken along line CC in FIG. 11;

FIG. 14 is a longitudinal sectional view of the semiconductor device according to the third embodiment of the present invention, taken along line DD in FIG. 11;

FIG. 15 is a longitudinal sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 16 is a longitudinal sectional view illustrating main steps of manufacturing a semiconductor device according to a fourth embodiment;

FIG. 17 is a longitudinal sectional view of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 18 is a vertical cross-sectional view illustrating main processes for manufacturing a semiconductor device according to a fifth embodiment;

FIG. 19 is a longitudinal sectional view illustrating a step following FIG. 18 in a main step of manufacturing the semiconductor device according to the fifth embodiment;

FIG. 20 is a longitudinal sectional view illustrating a step following FIG. 19 in a main step of manufacturing the semiconductor device according to the fifth embodiment;

FIG. 21 is a longitudinal sectional view illustrating a step following FIG. 20 in a main step of manufacturing the semiconductor device according to the fifth embodiment;

FIG. 22 is a longitudinal sectional view of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 23 is a longitudinal sectional view illustrating a main step of manufacturing a semiconductor device according to a sixth embodiment;

FIG. 24 is a longitudinal sectional view illustrating a step following FIG. 23 in a main step of manufacturing the semiconductor device according to the sixth embodiment;

FIG. 25 is a longitudinal sectional view illustrating a step following FIG. 24 in a main step of manufacturing the semiconductor device according to the sixth embodiment;

FIG. 26 is a longitudinal sectional view illustrating a step following FIG. 25 in a main step of manufacturing the semiconductor device according to the sixth embodiment;

FIG. 27 is a longitudinal sectional view of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 28 is a longitudinal sectional view illustrating a main step of manufacturing the semiconductor device according to the seventh embodiment;

FIG. 29 is a longitudinal sectional view illustrating a step following FIG. 28 in a main step of manufacturing the semiconductor device according to the seventh embodiment;

FIG. 30 is a longitudinal sectional view of a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 p ^- type silicon substrate 2-an ⁺ type buried layer 2-bp ⁺ type buried layer 3 Epitaxial layer for collectors 4 Silicon oxide film 5 Collector extraction region 6 Silicon oxide film 7 Polysilicon film for base electrode 8 Silicon nitride film Reference Signs List 9 silicon oxide film 10 silicon nitride film 11 single crystal intrinsic base region 11a p ⁺ type single crystal silicon film 12, 12a p ⁺ type polysilicon film 13 silicon oxide film 14 n type collector region 15 n ⁺ type single crystal emitter region 16 emitter Polysilicon film for electrode 17 Silicon oxide film 18-a, 20-a Aluminum alloy electrode for emitter 18-b, 20-b Aluminum alloy electrode for base 18-c, 20-c Aluminum alloy electrode for collector 19-a, 19 -B, 19-c Tungsten electrode 21 Polycrystalline SiGe film 22 Si Ge alloy intrinsic base region 23 single crystal silicon film 24 n ⁺ type single crystal emitter region 31 n ⁻ type silicon substrate 32 polysilicon film for source electrode 33 polysilicon film for drain electrode 34 silicon film for p-type channel 35, 36 p-type Polysilicon film 37 Polysilicon film for gate electrode 38 n ⁺ -type single crystal silicon film 39-a Aluminum alloy electrode for gate 39-b Aluminum alloy electrode for source 39-c Aluminum alloy electrode for drain 50a Amorphous silicon film 50b Single crystal silicon Film 50c polycrystalline silicon film 51 single-crystal silicon film for base electrode 52 single-crystal silicon film for collector electrode 53 p ⁺ -type single-crystal silicon film 54, 56, 57, 58 sidewall silicon oxide film 55 sidewall silicon nitride film 100 silicon substrate 101 , 201, 30 , 501 first opening 102,202,302,502 second opening 503 third opening

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Claims (34)

[Claims] A first conductivity type single crystal semiconductor substrate; a first conductivity type single crystal semiconductor substrate having a first predetermined width covering a main surface of the single crystal semiconductor substrate and exposing a part of the main surface of the single crystal semiconductor substrate; A first insulating film having an opening, a first semiconductor layer of a reverse conductivity type partially covering the first insulating film, a second insulating film covering the first semiconductor layer, A second opening formed to have a second predetermined width aligned with the first opening so as to penetrate the first semiconductor layer and the second insulating film, The second predetermined width is smaller than the first predetermined width;
A second opening in which an edge of the second opening of the first semiconductor layer forms a protrusion protruding into the first opening of the first insulating film; So as to expose a lower portion of a side surface of the protruding portion of the first semiconductor layer that is exposed at a side surface of the opening portion.
An insulating side wall formed on a side surface of the second opening of the first semiconductor layer and the second insulating film; and the single crystal in the first opening of the first insulating film. A second semiconductor layer formed of a reverse conductivity type single crystal semiconductor formed on the part of the main surface of the semiconductor substrate; a lower surface of the protruding portion of the first semiconductor layer; a lower portion of the side surface; A third semiconductor layer of the opposite conductivity type that is coupled to an end of the second semiconductor layer; a fourth semiconductor layer of one conductivity type formed in an upper surface region of the second semiconductor layer; And a fifth semiconductor layer of one conductivity type formed on the upper surface of the fourth semiconductor layer, wherein the thickness of the insulating side wall is larger than the thickness of the third semiconductor layer. Semiconductor device. 2. The single-crystal semiconductor substrate is a single-crystal silicon substrate, wherein the first semiconductor layer is formed of polysilicon, the second semiconductor layer is formed of single-crystal silicon, and the third semiconductor 2. The semiconductor device according to claim 1, wherein said layer and said fifth semiconductor layer are formed of polysilicon. 3. The single-crystal semiconductor substrate is a single-crystal silicon substrate, the first semiconductor layer is formed of polysilicon, and at least a part of the second semiconductor layer is a single-crystal silicon substrate.
2. The semiconductor device according to claim 1, wherein the third semiconductor layer is made of iGe, at least a part of the third semiconductor layer is made of polycrystalline SiGe, and the fifth semiconductor layer is made of polysilicon. 4. The single crystal semiconductor substrate is a single crystal silicon substrate, wherein the first semiconductor layer is formed of single crystal silicon, the second semiconductor layer is formed of single crystal silicon, and the third semiconductor layer is formed of single crystal silicon. The semiconductor layer is formed of single crystal silicon,
2. The semiconductor device according to claim 1, wherein said fifth semiconductor layer is formed of polysilicon. 5. The semiconductor device according to claim 1, wherein the insulating side wall is formed on the first semiconductor layer so as to expose a lower portion of the side surface of the protrusion of the first semiconductor layer exposed on a side surface of the second opening. A first insulating side wall formed on a side surface of the second opening with the second insulating film; and a first insulating side wall formed on the first insulating side wall and parallel to a side surface of the second opening. 5. The semiconductor device according to claim 1, wherein the semiconductor device is formed of a second insulating side wall that is wider than the first insulating side wall. 6. 6. The semiconductor device according to claim 1, further comprising a third insulating film covering the insulating side wall and defining a region of the fourth semiconductor layer formed in an upper surface region of the second semiconductor layer. Item 6. The semiconductor device according to any one of Items 1 to 5. 7. A single-conductivity-type single-crystal semiconductor substrate, and a first single-crystal semiconductor substrate having a first predetermined width that covers a main surface of the single-crystal semiconductor substrate and exposes a part of the main surface of the single-crystal semiconductor substrate. A first insulating film having an opening, a first semiconductor layer of a reverse conductivity type single crystal semiconductor partially covering the first insulating film, and a second insulating film covering the first semiconductor layer A second opening formed to have a second predetermined width aligned with the first opening so as to penetrate the film and the first semiconductor layer and the second insulating film; Wherein the second predetermined width is smaller than the first predetermined width, so that
A second opening in which an edge of the second opening of the first semiconductor layer forms a protrusion protruding into the first opening of the first insulating film; So as to expose a lower portion of a side surface of the protruding portion of the first semiconductor layer that is exposed at a side surface of the opening portion.
An insulating side wall formed on a side surface of the second opening of the first semiconductor layer and the second insulating film; and the single crystal in the first opening of the first insulating film. A second semiconductor layer formed of a reverse conductivity type single crystal semiconductor formed on the part of the main surface of the semiconductor substrate; a lower surface of the protruding portion of the first semiconductor layer; a lower portion of the side surface; A third semiconductor layer of the opposite conductivity type that is coupled to an end of the second semiconductor layer; a fourth semiconductor layer of one conductivity type formed in an upper surface region of the second semiconductor layer; And a fifth semiconductor layer of one conductivity type formed on the upper surface of the fourth semiconductor layer. 8. A single-crystal semiconductor substrate of one conductivity type, and a first single-crystal semiconductor substrate having a first predetermined width that covers a main surface of the single-crystal semiconductor substrate and exposes a part of the main surface of the single-crystal semiconductor substrate. A first insulating film having an opening, a first semiconductor layer of a reverse conductivity type single crystal semiconductor partially covering the first insulating film, and a second insulating film covering the first semiconductor layer A second opening formed to have a second predetermined width aligned with the first opening so as to penetrate the film and the first semiconductor layer and the second insulating film; Wherein the second predetermined width is smaller than the first predetermined width, so that
A second opening in which an edge of the second opening of the first semiconductor layer protrudes into the first opening of the first insulating film; A second semiconductor layer made of a reverse conductivity type single crystal semiconductor formed on the part of the main surface of the single crystal semiconductor substrate in the first opening of the insulating film; A third semiconductor layer made of a reverse conductivity type single crystal semiconductor that couples a lower surface of the protruding portion of the semiconductor layer, a lower portion of the side surface, and an end of the second semiconductor layer; A fourth semiconductor layer of one conductivity type formed in the upper surface region; and a fifth semiconductor layer of one conductivity type formed on the upper surface of the fourth semiconductor layer. Semiconductor device. 9. A single conductivity type single crystal semiconductor substrate, and a first predetermined width which covers a main surface of the single crystal semiconductor substrate and exposes a part of the main surface of the single crystal semiconductor substrate. A first insulating film having an opening, a first semiconductor layer of a reverse conductivity type single crystal semiconductor partially covering the first insulating film, and a second insulating film covering the first semiconductor layer A second opening formed to have a second predetermined width aligned with the first opening so as to penetrate the film and the first semiconductor layer and the second insulating film; Wherein the second predetermined width is smaller than the first predetermined width, so that
A second opening in which an edge of the second opening of the first semiconductor layer protrudes into the first opening of the first insulating film; A second semiconductor layer made of a reverse conductivity type single crystal semiconductor formed on the part of the main surface of the single crystal semiconductor substrate in the first opening of the insulating film; A third semiconductor layer made of a reverse conductivity type single crystal semiconductor that couples a lower surface and a side surface of the protruding portion of the semiconductor layer to an end of the second semiconductor layer, and an upper surface region of the second semiconductor layer And a fourth semiconductor layer of one conductivity type, and a fifth semiconductor layer of one conductivity type formed on the upper surface of the fourth semiconductor layer. Semiconductor device. 10. The fourth semiconductor device, wherein the fourth insulating film covers a side surface of the second insulating film and a side surface of the second semiconductor layer exposed in the second opening, and is formed in an upper surface region of the second semiconductor layer. 10. The semiconductor device according to claim 9, further comprising an insulating side wall defining a region of the semiconductor layer. 11. A first semiconductor device comprising: a single-crystal semiconductor substrate of one conductivity type; and a first opening covering a main surface of the single-crystal semiconductor substrate and exposing a part of the main surface of the single-crystal semiconductor substrate. An insulating film, and a second opening formed in alignment with the first opening, wherein the width at the lower end is narrower than the width of the first opening and gradually widens upward. And a first semiconductor layer of a reverse conductivity type single crystal semiconductor partially covering the first insulating film; and a width substantially equal to or greater than a width of an upper end of the second opening. A second insulating film having a somewhat narrower third opening formed so as to be aligned with the second opening and covering the first semiconductor layer; A part formed on the part of the main surface of the single crystal semiconductor substrate in the first opening is partly formed by the first opening. A second semiconductor layer made of a reverse conductivity type single crystal semiconductor in contact with a lower surface of the protruding portion of the first semiconductor layer protruding inside; a one conductivity type formed in an upper surface region of the second semiconductor layer; And a fourth semiconductor layer of one conductivity type formed on the upper surface of the fourth semiconductor layer. 12. Covering at least an upper portion of a side surface of the second insulating film exposed in the third opening and a side surface of the second semiconductor layer exposed in the third opening.
The semiconductor device according to claim 11, further comprising an insulating side wall formed in an upper surface region of the second semiconductor layer and defining a region of the third semiconductor layer. 13. The first semiconductor layer and the insulating side wall cover substantially the entire side surface of the first semiconductor layer exposed inside the second opening or an upper portion thereof. A first insulating side wall formed on the side surface of the second opening with the second insulating film and on a side surface of the third opening; and formed on the first insulating side wall and And a second insulating side wall having a lower end contacting the upper surface of the second semiconductor layer and defining a region of the fourth semiconductor layer formed in an upper surface region of the second semiconductor layer. 13. The semiconductor device according to claim 12, wherein: 14. The second semiconductor layer is formed so that an upper end thereof rides on a lower side portion of a side surface of the first semiconductor layer that is exposed to the second opening. The semiconductor device according to any one of claims 11 to 13, wherein: 15. An upper surface of the first semiconductor layer is covered with a third insulating film having substantially the same area as the first semiconductor layer, and an upper surface of the third opening of the second insulating film formed thereon is formed. 14. The semiconductor device according to claim 11, wherein the width is slightly smaller than the width of the upper end of the second opening. 16. The single crystal semiconductor substrate is a single crystal silicon substrate having the main surface as a (100) plane, and the first semiconductor layer is a single crystal silicon having a plane parallel to the main surface as a (100) plane. 16. The crystalline silicon layer, wherein a surface of the first semiconductor layer exposed on a side surface of the second opening is a {111} plane. Semiconductor device. 17. The semiconductor device according to claim 7, wherein the single crystal semiconductor substrate is a single crystal silicon substrate, and at least a part of a lower side of the second semiconductor layer is formed of single crystal SiGe. 17. The semiconductor device according to any one of 16. 18. The second semiconductor layer is characterized in that the lower end is made of single-crystal SiGe, the Ge content gradually decreases toward the upper side, and the upper end is made of single-crystal Si. The semiconductor device according to claim 17, wherein: 19. A first insulating film is formed so as to cover a main surface of a single-conductivity-type single-crystal semiconductor substrate, and a reverse-conductivity-type first semiconductor layer partially covering the first insulating film is formed. Forming a second insulating film covering the first semiconductor layer; forming a first insulating film having a first predetermined width so as to penetrate the first semiconductor layer and the second insulating film; Forming an opening, forming a third insulating film covering the bottom surface and side surfaces of the first opening and the second insulating film, covering the third insulating film; Forming a fourth insulating film having a property different from that of the film; etching back the fourth insulating film and the third insulating film to form the fourth insulating film on the second insulating film; Third
Is completely removed, and the fourth insulating film is completely removed from above the bottom surface of the first opening to expose the third insulating film, and a side surface of the first opening is formed. The fourth
The first insulating film and the third insulating film are selectively removed while leaving an insulating side wall composed of the insulating film and the third insulating film, and a part of the main surface of the single crystal semiconductor substrate is removed. Expose it,
A second having a second predetermined width larger than the first predetermined width;
Forming an opening in alignment with the first opening;
The edge of the first opening of the first semiconductor layer forms an extruding portion that protrudes into the second opening of the first insulating film, and is formed on a side surface of the first opening. Partially leaving the third insulating film below the fourth insulating film,
The lower part of the side surface of the protruding part of the first semiconductor layer exposed on the side surface of the first opening is exposed, and the lower part of the first semiconductor layer exposed on the side surface of the first opening is exposed. A semiconductor is grown on the lower part of the side surface of the protruding part and on the part of the main surface of the single crystal semiconductor substrate exposed in the second opening, and Forming a second semiconductor layer made of a reverse conductivity type single crystal semiconductor on the part of the main surface,
Forming a third semiconductor layer of a reverse conductivity type, which reaches an end of the second semiconductor layer from a lower surface of the protruding portion and a lower portion of the side surface of the semiconductor layer and has a thickness smaller than a thickness of the insulating side wall; A semiconductor, comprising: a fourth semiconductor layer of one conductivity type formed in an upper surface region of a second semiconductor layer; and a fifth semiconductor layer formed on an upper surface of the fourth semiconductor layer. Device manufacturing method. 20. The second semiconductor layer is formed by forming the single crystal semiconductor substrate with a single crystal silicon substrate, forming the first semiconductor layer with polysilicon, and growing silicon as the semiconductor. 20. The method according to claim 19, wherein the third semiconductor layer is selectively formed of crystalline silicon, and the third semiconductor layer is selectively formed of polysilicon. 21. The method according to claim 21, wherein the single crystal semiconductor substrate is formed of a single crystal silicon substrate, the first semiconductor layer is formed of polysilicon, and SiGe is grown as at least a part of the semiconductor. 20. The semiconductor device according to claim 19, wherein at least a part of the semiconductor layer is selectively formed of single-crystal SiGe, and at least a part of the third semiconductor layer is selectively formed of polycrystalline SiGe. Production method. 22. The second semiconductor layer is formed by forming the single crystal semiconductor substrate with a single crystal silicon substrate, forming the first semiconductor layer with single crystal silicon, and growing silicon as the semiconductor. 20. The method according to claim 19, wherein the third semiconductor layer is selectively formed of single crystal silicon, and the third semiconductor layer is selectively formed of single crystal silicon. 23. depositing a polycrystalline semiconductor containing a high-concentration one-conductivity-type impurity on the upper surface of the second semiconductor layer, thereby forming the one-conductivity-type And forming a fourth semiconductor layer of one conductivity type in an upper surface region of the second semiconductor layer by diffusing impurities of one conductivity type from the fifth semiconductor layer of one conductivity type. The method of manufacturing a semiconductor device according to claim 19, wherein the method comprises: 24. After further forming a fifth insulating film covering the insulating side wall and defining a partially exposed surface of the upper surface of the second semiconductor layer, on the upper surface of the second semiconductor layer, The method of manufacturing a semiconductor device according to claim 23, wherein the polycrystalline semiconductor containing a high concentration of one conductivity type impurity is deposited. 25. A first insulating film is formed so as to cover a main surface of a single conductivity type single crystal semiconductor substrate, and a reverse conductivity type semiconductor layer partially covering the first insulating film is formed. A single-crystallized first semiconductor layer is formed, a second insulating film is formed to cover the first semiconductor layer, and the single-crystallized first semiconductor layer and the second insulating layer are formed. A first opening having a first predetermined width is formed so as to penetrate through the film, and a third insulating film covering a bottom surface and side surfaces of the first opening and the second insulating film is formed. Forming a fourth insulating film covering the third insulating film and having a property different from that of the third insulating film; and etching back the fourth insulating film and the third insulating film. The fourth insulating film on the second insulating film and the third
Is completely removed, and the fourth insulating film is completely removed from above the bottom surface of the first opening to expose the third insulating film, and a side surface of the first opening is formed. The fourth
The first insulating film and the third insulating film are selectively removed while leaving an insulating side wall composed of the insulating film and the third insulating film, and a part of the main surface of the single crystal semiconductor substrate is removed. Expose it,
A second having a second predetermined width larger than the first predetermined width;
Forming an opening in alignment with the first opening;
The edge of the first opening of the first semiconductor layer forms an extruding portion that protrudes into the second opening of the first insulating film, and is formed on a side surface of the first opening. Partially leaving the third insulating film below the fourth insulating film,
The lower part of the side surface of the protruding part of the first semiconductor layer exposed on the side surface of the first opening is exposed, and the lower part of the first semiconductor layer exposed on the side surface of the first opening is exposed. A semiconductor is grown on the lower part of the side surface of the protruding part and on the part of the main surface of the single crystal semiconductor substrate exposed in the second opening, and Forming a second semiconductor layer made of a reverse conductivity type single crystal semiconductor on the part of the main surface;
Forming a third semiconductor layer made of a reverse conductivity type single crystal semiconductor that reaches an end of the second semiconductor layer from a lower surface of the protruding portion of the semiconductor layer and an end of the second semiconductor layer from a lower portion of the side surface; A method for manufacturing a semiconductor device, comprising: forming a fourth semiconductor layer of one conductivity type formed in an upper surface region and a fifth semiconductor layer formed on an upper surface of the fourth semiconductor layer. 26. A first insulating film is formed so as to cover a main surface of a single conductivity type single crystal semiconductor substrate, and a semiconductor layer is formed and monocrystallized to partially cover the first insulating film. Forming a single-crystallized first semiconductor layer of a reverse conductivity type, forming a second insulating film covering the first semiconductor layer, and forming the single-crystallized first semiconductor layer and the second insulating film; Forming a first opening having a first predetermined width so as to penetrate the film, selectively removing the first insulating film in the first opening, and forming the first predetermined width; A second opening having a larger second predetermined width is aligned with the first opening to form a first opening.
And a part of the main surface of the single-crystal semiconductor substrate is exposed, and the edge of the first opening of the first semiconductor layer is formed on the second surface of the first insulating film. The first semiconductor layer is exposed on the side surface of the first opening, and is exposed in the second opening on the side surface of the first semiconductor layer exposed on the side surface of the first opening. A semiconductor is grown on the part of the main surface of the single crystal semiconductor substrate, and a second crystal of a reverse conductivity type single crystal semiconductor is formed on the part of the main surface of the single crystal semiconductor substrate. And a third semiconductor layer made of a reverse conductivity type single crystal semiconductor reaching the end of the second semiconductor layer from the lower surface and the side surface of the protruding portion of the first semiconductor layer. Forming a fourth layer of one conductivity type formed in an upper surface region of the second semiconductor layer. Method of manufacturing a semiconductor device, and forming a fifth semiconductor layer which is formed on the upper surface of the conductive layer and the fourth semiconductor layer. 27. A first insulating film is formed so as to cover a main surface of a single-conductivity type single crystal semiconductor substrate, and partially covers the first insulating film. A single crystallized reverse conductivity type first having a {100} plane parallel to the main surface, the first conductivity type having a second insulating film;
Forming a third insulating film covering the second insulating film; forming a first opening having a first predetermined width in the third insulating film and the first semiconductor layer; And forming the second part.
The first opening aligned with the first opening in the insulating film of FIG.
Forming a second opening having a second predetermined width larger than the predetermined width, and exposing the {111} plane to the surface of the first semiconductor layer exposed to the first opening by heat treatment Then, a third opening having a third predetermined width smaller than the second predetermined width on the lower side and having a width substantially equal to the second predetermined width on the upper side is formed in the first semiconductor layer. Forming a fourth opening in the first insulating film by removing the first insulating film below the third opening and further etching the first insulating film in a lateral direction. Exposing a part of a main surface of the single-crystal semiconductor substrate,
A part of the lower surface of the semiconductor layer is exposed, the lower surface of the first semiconductor layer exposed in the fourth opening, and the single crystal semiconductor substrate exposed in the fourth opening Forming a second semiconductor layer made of a reverse conductivity type single crystal semiconductor that fills at least the fourth opening on the main surface of the second semiconductor layer; and an upper surface region of the second semiconductor layer. Forming a third semiconductor layer of one conductivity type formed on the first semiconductor layer and a fourth semiconductor layer formed on an upper surface of the third semiconductor layer. 28. The step of forming the first opening and the second opening comprises: forming a first opening penetrating the third insulating film and the second insulating film.
A second opening is formed in the second insulating film by laterally etching the second insulating film; and a first semiconductor is formed by etching the first semiconductor. 28. The method for manufacturing a semiconductor device according to claim 27, comprising a step of forming a first opening in the layer. 29. A first insulating film is formed so as to cover a main surface of a single-conductivity-type single-crystal semiconductor substrate, and a single-crystallized reverse-conductivity-type second crystal partially covers the first insulating film. Forming a first insulating layer covering the first semiconductor layer; forming a first opening having a first predetermined width in the second insulating film; Exposing a part of the surface of the first semiconductor layer, etching the first semiconductor layer by a wet method, and forming a second predetermined width narrower than the first predetermined width below the first semiconductor layer. A second opening having a width and having a width substantially equal to the first predetermined width is formed on the upper side, a part of the surface of the first insulating film is exposed, and exposed below the second opening. The first insulating film is removed, and the first insulating film is laterally etched to form a third insulating film on the first insulating film. Forming the opening to expose a part of the main surface of the single crystal semiconductor substrate and to expose a part of the lower surface of the first semiconductor layer; A semiconductor is grown on the lower surface and side surfaces of the first semiconductor layer and on the main surface of the single crystal semiconductor substrate exposed in the third opening, and at least the inside of the third opening is filled. Forming a second semiconductor layer made of a single-crystal semiconductor of the opposite conductivity type, and forming a third semiconductor layer of one conductivity type formed in a partial region on the upper surface of the second semiconductor layer and the third semiconductor layer. Forming a fourth semiconductor layer formed on an upper surface of the semiconductor layer. 30. A plane parallel to a main surface of the single crystal semiconductor substrate of the first semiconductor layer is defined as {100} plane,
30. The method according to claim 29, wherein, in the step of forming the second opening in the semiconductor layer, the {111} plane of the first semiconductor layer is exposed. 31. depositing a polycrystalline semiconductor containing a high-concentration one-conductivity-type impurity on the upper surface of the second semiconductor layer, thereby forming the one-conductivity-type second impurity on the upper surface of the second semiconductor layer. 4 semiconductor layer is formed, and the one conductivity type third semiconductor layer is formed in the upper surface region of the second semiconductor layer by diffusing one conductivity type impurity from the one conductivity type fourth semiconductor layer. 31. The method of manufacturing a semiconductor device according to claim 27, wherein: 32. Prior to forming a fourth opening or a third opening in the first insulating film, the second and third openings are formed.
Forming a first insulating sidewall covering at least an upper portion of the opening of the insulating film or the opening of the second insulating film and the opening of the first semiconductor layer; and forming the second semiconductor layer. After that, the first insulating side wall is covered,
Forming a second insulating side wall that defines an exposed portion of the surface of the semiconductor layer, and depositing the polycrystalline semiconductor containing a high concentration of one conductivity type impurity on an upper surface of the second semiconductor layer. The method for manufacturing a semiconductor device according to claim 31, wherein: 33. The semiconductor device according to claim 25, wherein the single crystal semiconductor substrate is formed of a single crystal silicon substrate, and at least a part of the second semiconductor layer is formed of a single crystal SiGe layer. 2. The method for manufacturing a semiconductor device according to claim 1. 34. The step of forming the second semiconductor layer, comprising:
forming a single crystal SiGe layer in which the e content is constant or the Ge content gradually increases; and forming a transition single crystal SiGe layer in which the Ge content gradually decreases. The method for manufacturing a semiconductor device according to claim 33, wherein: