JP2000268591A - Rom driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make increasable the ROM operation margin by lengthening a ROMTr forming period to solve such a problem that read-out in ROM operation may be failed and ROM operation margin may not be given during a ROMTr forming period, namely margin is not given at a 'High' level of a pre-charge signal in a ROM driving circuit. SOLUTION: The number of stages of a N-MOS transistor 21 is made more than the number of stages of a N-MOSTy 31 of a MainROM 13. Thereby after pre-charge of the MainROM 13 is finished, pre-charge of the N-MOSTr 21 of the gate circuit 14 is finished later (pre-charge signal 43 is at 'High' level), and thus, the ROM operation margin is increased by lengthening the ROMTr forming period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a ROM drive circuit for increasing the operation margin of a ROM.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional ROM drive circuit. The clock generator 51 divides the frequency of the basic clock signal 62 of the LSI and generates a precharge signal 63 and a latch signal 6.
4 is a circuit for creating the same. The MainROM 52 is driven by the clock generator 51 to read stored contents.

FIG. 6 shows the drive timing of the MainROM 52 (a ROM operation period is constituted by a precharge period and a period in which a ROMTr (transistor) is established).

[0004] As shown in FIG.
Is a precharge period at a "Low" level for two widths of the basic clock signal 62, and then the basic clock signal 6
The “High” level corresponding to two widths of 2 is a ROMTr establishment period.

[0005]

SUMMARY OF THE INVENTION Such a conventional RO
In the M driving circuit, “Lo” of the precharge signal 63 is used.
Although the “w” level (precharge period) has a sufficient margin, if there is no margin in the ROMTr establishment period, that is, if there is no margin in the “High” level of the precharge signal 63, RO
The ROM cannot operate during the MTr establishment period, and the reading as the ROM operation fails after all.
Therefore, there is no ROM operation margin, and there is a problem that high-speed reading cannot be performed.

Accordingly, the present invention has been made in view of the above circumstances, and has as its object to provide a ROM drive circuit capable of solving the above-mentioned problems and increasing a ROM operation margin.

[0007]

A ROM drive circuit according to the present invention comprises a clock generator for dividing a basic clock to generate a latch signal, and an RO to which the latch signal is supplied.
M, and a gate circuit to which an inverted signal of the latch signal is supplied and which generates a precharge signal to be supplied to the ROM from the signal, wherein the ROM has an output side to which an address signal is supplied to each gate. Multi-stage MO
An output gate comprising an S transistor connected in series;
The gate circuit is configured such that an inverted signal of the latch signal is supplied to a commonly connected gate electrode, and a delay circuit comprising a serial connection of a first conductivity type MOS transistor having a greater number of stages than a MOS transistor constituting an output gate of the ROM. A second conductivity type MOS transistor having a source electrode and a drain electrode connected between one end of the delay circuit and a power supply, and a first conductivity type MOS transistor having a source electrode and a drain electrode connected between the other end of the delay circuit and ground. Conductive MOS
A transistor, an inverter circuit having an input terminal connected to a connection point of the first conductivity type MOS transistor and the delay circuit, and an output of the inverter circuit and an inverted signal of the latch signal are supplied as input signals; A NAND gate circuit whose output is supplied to the gate electrodes of the first conductivity type MOS transistor and the second conductivity type MOS transistor.
The output of the gate circuit is supplied to the ROM as a precharge signal.

In the ROM drive circuit of the present invention, the first conductivity type MOS transistor is an N-channel MOS transistor, and the second conductivity type MOS transistor is an N-channel MOS transistor.
The transistor is a P-channel MOS transistor.

According to such a configuration, in the gate circuit, the precharge is completed with a delay after the MainROM is precharged. Therefore, compared to the conventional example, the ROM
The period for forming Tr can be lengthened, and the ROM operation margin can be increased.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a ROM according to an embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a drive circuit. It should be noted that components necessary for the description of the present embodiment are shown, and other components are omitted.

A clock generator 11 generates a latch signal 12 by dividing the frequency of a basic clock signal 10 of the LSI.

The MainROM 13 is a ROM driven by the clock generator 11. The gate circuit 14 generates a precharge signal 43 and outputs
It has a function to send to M13.

FIG. 2 is a circuit diagram of the gate circuit 14.

The gate circuit 14 has a MainROM
13 N-channel MOS transistors (hereinafter referred to as N-MO
A series-connected N-MOSTr 21 is provided in which more N-MOSTrs than the number of stages (STr) are connected. This series connection N-
The MOSTr 21 constitutes a delay circuit. A plurality of NMs constituting the series-connected N-MOS Tr 21
The gates of the OSTr are commonly connected, and an address signal input to these common connection gates is an inverted signal 42 of a latch signal (a signal having one cycle of the address period is acceptable).
And

When a precharge signal 43 is supplied to each gate electrode, a P-channel MOS transistor (hereinafter, P-MOSTr) 24 and an N-MOSTr 25
Is provided.

A power supply 27 is connected to the drain of the P-MOS Tr 24. The source of the P-MOS Tr 24 has one end N-MOS Tr 21 included in the series-connected N-MOS Tr 21.
The drain of the MOSTr is connected. The drain of the N-MOS Tr 25 is connected to the source of the N-MOS Tr 25 at the other end included in the series connection N-MOS Tr 21. The source of the N-MOS Tr 25 is GND 26
Is connected.

The drain signal of the N-MOS Tr 25 is set to NO.
The inverted signal is obtained by the T gate circuit 22, and the inverted signal and the inverted signal 42 of the latch signal are input to the NAND gate circuit 23. A precharge signal 43 is obtained at the output side of the NAND gate circuit 23.

FIG. 3 is an output circuit diagram of the MainROM 13.

The P-MOS Tr 33 has a precharge signal 43 as a gate and a drain connected to a power supply 35. The source is an end N-MOS of a series-connected N-MOS Tr 31 in which a plurality of N-MOS Trs are connected in series.
The drain of Tr is connected. This series connection NM
The N-MOS Tr at the other end of the OSTr 31 uses the precharge signal 43 as a gate, and has a source connected to the GND 34.

In the series-connected N-MOS Tr 31, the address signal 41 is supplied to the gate electrode of each N-MOS Tr (N-MOS Tr 31 whose source is connected to GND 34).
MOSTr).

An output signal from the source electrode of the N-MOS Tr 34 is input to the NOT gate circuit 32 and output to the gate circuit 14 as an inverted signal 42 of a latch signal. X point 45
Is a ROM output signal.

FIG. 4 shows a drive timing chart of the MainROM 13.

The ROMTr operation period is composed of a precharge period and a ROMTr (transistor) establishment period.
The precharge period means that the precharge signal 43 is “Lo”
This is a period that is at the “w” level. Further, the ROMTr establishment period is a period in which the precharge signal 43 is at the “High” level.

Here, in the timing chart of FIG. 4, the series-connected N-MOS Tr 21 of the gate circuit 14
Since the number of stages is larger than that of the series-connected N-MOS Trs 31 of the main ROM 13, the N-MOS Tr 21 of the gate circuit 14 is pre-charged with a delay after the main ROM 13 is precharged.

That is, the point A in FIG.
At time "h", the MainROM 13 completes precharge, sets the precharge signal 43 to "High", and shifts to the ROMTr establishment period.

As a result, the "High" period of the precharge signal 43 can be made longer as shown in FIG. In other words, the period for forming the ROMTr can be lengthened, and the ROM operation margin can be increased.

The present embodiment is a case where there is a margin in the precharge period, but is also effective in a case where there is no margin in the precharge period and there is a margin in the period of ROMTr establishment.

This will be described with reference to FIG.

When a precharge signal is generated by the basic clock signal 62, the precharge signal 71 (A)
, "Low" (precharge period) for two basic clock widths and "High" (ROMTr establishment period) for two basic clocks, and a basic clock such as a precharge signal 72 (B). "Low" for one width of signal 62
(Precharge period) “High” for 3 minutes (ROM
Tr establishment period).

In the conventional example of the present embodiment, as shown in FIG. 6, a waveform example similar to the precharge signal 71 (A) is described, but as in the case of the precharge signal 72 (B). ROMT because there is no margin in the precharge period
Even if there is a margin in the period of r establishment, point A in FIG.
Becomes "High", the MainROM 13 has completed precharge, and the precharge signal 43 is changed to "Hi".
gh ”, and the process proceeds to the ROMTr establishment period, so that the present invention is effective.

[0032]

As described above in detail, according to the present invention, the N-MOS MTr 21 of the gate circuit 14 has a MainR
Since the number of N-MOS Trs 31 of the OM 13 is larger than the number of stages,
After the MainROM 13 is precharged, the N-MOS MTr 21 of the gate circuit 14 is precharged with a delay. That is, when the point A has already become "High", the precharging of the MainROM 13 is completed, the precharge signal is set to "High", and the ROMT
It shifts to the r establishment period. Therefore, compared with the conventional example, RO
The MTr establishment period can be lengthened, and the ROM operation margin can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a ROM drive circuit according to one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a gate circuit according to the embodiment.

FIG. 3 is an exemplary circuit diagram showing a configuration of a circuit of a MainROM according to the embodiment.

FIG. 4 is a ROM drive timing chart of the ROM drive circuit according to the embodiment;

FIG. 5 is a block diagram showing a configuration of a conventional ROM drive circuit.

FIG. 6 is a ROM drive timing chart of the conventional ROM drive circuit.

FIG. 7 is a ROM drive timing chart of another conventional ROM drive circuit.

[Explanation of symbols]

10: basic clock signal, 11: clock generator, 12: latch signal, 13: MainROM, 14 ...
Gate circuits, 21... N-MOSTr of the number of stages of N-MOSTr of MainROM + α, 22... NOT gate circuit,
23: NAND gate circuit, 24: P-MOS Tr, 2
5 N-MOS Tr, 26 GND, 27 power supply, 31
... N-MOSTr, 32 ... NOT gate circuit, 33 ... P
MOSTr, 34 GND, 35 power supply, 41 address signal, 42 inverted latch signal, 43 precharge signal, 44 point A signal, 45 ROM output signal (X point) 51 clock generator, 52 ... Main
ROM, 61 ... address signal, 62 ... basic clock signal, 63 ... precharge signal, 64 ... latch signal, 65
... ROM output signal (X point), 71 ... precharge signal (A), 72 ... precharge signal (B).

Claims (2)

[Claims] A clock generator for generating a latch signal by dividing a basic clock; a ROM to which the latch signal is supplied; an inverted signal of the latch signal;
A gate circuit for generating a precharge signal to be supplied to the ROM from the signal, wherein the ROM has an output gate formed by a series connection of a plurality of stages of MOS transistors whose respective gates are supplied with an address signal. Wherein the gate circuit is configured such that an inverted signal of the latch signal is supplied to a commonly connected gate electrode, and a serial connection of a first-conductivity-type MOS transistor having a greater number of stages than the MOS transistors forming the output gate of the ROM. And a second conductivity type MO having a source electrode and a drain electrode connected between one end of the delay circuit and a power supply.
An S transistor, a first conductivity type MOS transistor having a source electrode and a drain electrode connected between the other end of the delay circuit and ground, and an input terminal at a connection point between the first conductivity type MOS transistor and the delay circuit. And an output of the inverter circuit and an inverted signal of the latch signal are supplied as input signals, and the output of the inverter circuit is the gate of the first conductivity type MOS transistor and the second conductivity type MOS transistor. And a NAND gate circuit supplied to the electrodes, wherein an output of the NAND gate circuit is supplied to the ROM as a precharge signal. 2. The method according to claim 1, wherein the first conductivity type MOS transistor is N-type.
2. The ROM drive circuit according to claim 1, wherein said second MOS transistor is a P-channel MOS transistor.