JP2000268072A - Semiconductor device, automatic wiring method for the same and recording medium recording automatic wiring program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily design narrow wiring in which thick wiring is divided by prescribed clearance grooves while including crossing regions as well. SOLUTION: In this automatic wiring method, the number and width of narrow wiring conductors and the number and width of clearance grooves between adjacent narrow wiring conductors are calculated concerning L-shaped orthogonal two thick wiring conductors on the basis of an allowable wiring width value and the lower limit value of clearance between adjacent wiring conductors, the virtual width of said two wiring conductors is found on the basis of these calculated results, the length of wiring to a crossing is expanded just by 1/2 of mutual virtual width and on the basis of the number and width of two expanded wiring conductors and the narrow wiring conductors and the number and width of clearance grooves between adjacent narrow wiring conductors, thick wiring is divided and bundled into narrow wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, an automatic wiring method for the semiconductor device, and a computer-readable recording medium storing an automatic wiring program.

[0002]

2. Description of the Related Art Ultra-highly integrated semiconductor devices employing a multi-layer wiring structure have appeared with the development of the miniaturization technology of the LSI process. Multilayer wiring substantially reduces the wiring area, increases the degree of freedom in wiring layout, prevents an increase in the number of chips, shortens the average wiring length, and suppresses the delay in operation speed due to wiring resistance. . One of the important technologies for realizing a multilayer wiring structure is a wiring flattening technology. In the multilayer wiring structure, it is necessary to form an interlayer insulating film between the upper and lower wirings, and the interlayer insulating film has unevenness caused by a lower wiring pattern.
This unevenness may cause a step coverage (step coverage) failure, leading to a disconnection failure of the wiring. Further, in order to secure an exposure margin in a photolithography process for forming an upper wiring pattern, it is desired that the interlayer insulating film be as flat as possible.

As a general method of flattening the interlayer insulating film, a portion having a high surface step of the interlayer insulating film formed by the HDP (High Density Plasma) method is used.
A method of polishing by a CMP (Chemical Mechanical Polishing) method is used. here,
The HDP method is a CVD method in which a reactive gas is decomposed by using an ion source that generates high-density plasma by microwaves and a high magnetic field to form a film at a low temperature. Also, CM
The P method is a method in which chemical polishing and mechanical polishing are combined, and is a method of performing a polishing treatment using a polishing cloth together with a chemical polishing agent having an etching ability. However,
It is known that the thickness and shape of the interlayer insulating film formed by the HDP method vary depending on the width of the wiring. For example, 2μm for power supply or ground line
In the case of a wiring structure (FIG. 14A) having a cross section in which the width (height) of the wiring is about 1 μm, the wiring is CM
It is known that even after the P polishing step (FIG. 14B), several thousand angstroms of the step of the interlayer insulating film remain in the upper region of the wide wiring (FIG. 14).
(C)). In this case, there is a problem that the global step, which is the amount of the step in the entire semiconductor device, becomes extremely large, the amount of the insulating film to be removed by polishing becomes large, and a long time is required for the CMP polishing step.

In order to reduce the global step, a clearance groove is provided in a wiring portion having a large wiring width, and when the wiring width is divided, an insulating film surface to be cut is also divided, so that the time of the CMP polishing step can be shortened. Have been. Techniques of these wiring design methods include, for example, Japanese Patent Laid-Open No. 09-1621.
A method described in Japanese Patent Publication No. 88 is known. In the semiconductor device design method described in the publication, a large number of clearance grooves having a predetermined shape are formed in a wiring patterned to a predetermined width, and an interlayer insulating film is formed so as to cover the clearance groove. Only a small protrusion is formed in the interlayer insulating film in the upper region, the interlayer insulating film in the upper region of the clearance groove becomes almost flat, and the amount of CMP, which is the amount removed in the CMP polishing process, is significantly less. After the CMP polishing step, the global step is significantly reduced, the step coverage (step coverage) is good, and the DOF (depth of focus) required in the photolithography step for forming the upper layer pattern is small. That is, a large margin can be obtained.

[0005]

However, in the conventional method described in the above publication, a slit-shaped clearance groove extending in the longitudinal direction of the wiring and a rectangular non-wiring concave portion have been proposed. There is a problem that the place where the cross-shaped wiring crosses is not considered. Therefore, when designing the wiring pattern of two intersecting wirings, it is necessary to form no non-wiring recess in the intersection area or to design each wiring and clearance groove one by one. There is a problem that the polishing amount of the interlayer insulating film in the upper part in the intersection region cannot be reduced, and in the latter case, there is a problem that the number of design steps is increased or automatic design is not possible. Also, for example, even if a wiring pattern is formed as shown in FIG. 15, the wirings 14, 15, 16, and 17 in which the wiring pattern is divided by the clearance grooves are originally the same wiring pattern, so that any It is necessary to perform a bundling process of electrically connecting these divided wirings at a location.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has been made into divided bundles that have the same wiring width at the intersections of the wirings and satisfy desired parameters and design rules. It is possible to provide a semiconductor device including a narrow wiring including an intersection area, an automatic wiring method of the semiconductor device, and a computer-readable recording medium in which an automatic wiring program is recorded.

[0007]

According to an aspect of the present invention, there is provided an automatic wiring method for a semiconductor device in which a wide wiring is divided and bundled into a plurality of narrow wirings to perform wiring processing. In the meantime, in the intersecting region where the wide wires intersect in an L-shape, a process of extending the interconnect length of the interconnect reaching the intersection of the intersecting region by １ ／ of the other virtual interconnect width is performed. Either for both wirings, or in a T-shaped crossing area, a processing to extend the wiring length of the non-stop side wiring by half of the other virtual wiring width The method includes the step of performing one of them, and the step of dividing the wide wiring into the narrow wiring and providing a clearance groove between the narrow wirings.

According to a second aspect of the present invention, there is provided the automatic wiring method for a semiconductor device according to the first aspect, wherein the dividing and bundling step is such that the total value of the widths of the narrow wirings is the value before the division. The bundling calculation is performed so as to satisfy a preset current density design value for the wide wiring.

Further, the invention according to claim 3 relates to an automatic wiring method for a semiconductor in which a wide wiring is divided and bundled into a plurality of narrow wirings to perform wiring processing, and a wiring width tolerance defining an upper limit value of the wiring width. From the viewpoint of avoiding value and spacing rule violations, a clearance allowable lower limit value that defines the lower limit value of the clearance between adjacent narrow wirings is set, and the wide wiring is extracted based on the set wiring width allowable value. After that, for each of the extracted thick wires, based on the set allowable upper limit value of the wire width and the allowable lower limit value of the clearance, the number of the narrow wires, the line width thereof, and the distance between the adjacent narrow wires. The number and width of the clearance grooves are calculated, and a virtual wiring width is obtained from the calculation result. In the intersection area where the wide wirings intersect in an L-shape, the intersection point of the intersection area is reached. Other wiring length of each wiring Is performed on both wirings by a process of extending by １ ／ of the virtual wiring width, based on the number of narrow wirings, their line widths, and the number and width of clearance grooves between adjacent narrow wirings. And processing for dividing and dividing the wide wiring into a plurality of narrow wirings.

According to a fourth aspect of the present invention, there is provided the automatic wiring method for a semiconductor device according to the third aspect, wherein the wide wirings are different from each other in an intersection region where the wide wirings cross each other in an L-shape. It is characterized by having a line width.

According to a fifth aspect of the present invention, there is provided an automatic wiring method for a semiconductor device according to the third aspect, wherein when the wide wirings have an intersecting region intersecting in a T-shape, the intersecting region is formed. Of the wires reaching the intersection, a process of extending the wire length of the stop-side wire by half of the other virtual wire width is performed, and the number of the narrow wires, their line widths, The method is characterized by including a process of dividing and dividing the wide wiring into a plurality of narrow wirings based on the number and width of the clearance grooves between the wide wirings.

According to a sixth aspect of the present invention, there is provided the automatic wiring method for a semiconductor device according to the fifth aspect, wherein the wide wirings are different from each other in an intersection region where the wide wirings cross each other in a T-shape. It is characterized by having a line width.

According to a seventh aspect of the present invention, there is provided a computer-readable recording medium having recorded thereon a semiconductor automatic wiring program for dividing a wide wiring into a plurality of narrow wirings and performing wiring processing. In order to avoid a violation of a spacing rule and a wiring width allowable value defining an upper limit of a wiring width, a clearance allowable lower limit value defining a lower limit value of a clearance between adjacent narrow wirings is set, and the set wiring width is set. After allowing the wide wiring to be extracted based on the allowable value, for each extracted wide wiring, the narrow wiring is set based on the set allowable upper limit value of the wiring width and the allowable lower limit value of the clearance. And the line width thereof, and the number and width of the clearance grooves between adjacent narrow wirings are calculated. From the calculation result, a virtual wiring width is obtained. In the intersecting region intersecting the pattern, a process of extending the wiring length of the wiring reaching the intersection of the intersecting region by 幅 of the other virtual wiring width is performed on both wirings, In a crossing region where the width wirings cross each other in a T-shape, of the wirings reaching the crossing point of the crossing region, the wiring length of the non-stop side wiring is extended by １ ／ of the other virtual wiring width. A program for dividing the wide wiring into a plurality of narrow wirings based on the number and width of the narrow wirings and the number and width of the clearance grooves between adjacent narrow wirings. It is characterized by including.

The invention according to claim 8 relates to a semiconductor device in which a wide wiring is divided and bundled into a plurality of narrow wirings, and the narrow wirings are L-shaped, T-shaped, The crossing area orthogonal to the cross shape includes a grid-shaped wiring portion and a plurality of rectangular non-wiring recesses, and the narrow wirings are bundled in the crossing area.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. The description will be made specifically using an embodiment. First Embodiment FIG. 1 is a block diagram schematically showing an electric configuration of an automatic wiring device according to a first embodiment of the present invention, and FIG. 2 is a schematic diagram showing characteristics of a wiring path created by the automatic wiring device. 3 and 4 are flowcharts for explaining the operation (automatic wiring processing) of the embodiment, and FIGS. 5 to 8 are diagrams for explaining the operation of the embodiment. 7 and 8 are enlarged views of the area of the circle A in FIG. The automatic wiring apparatus 11 of this example relates to an apparatus for automatically designing a wiring path of a semiconductor integrated circuit. As shown in FIG. 1, a library 5 storing parameters, design rules, and various graphic information, and an automatic wiring apparatus of this example. (Layout)
A recording medium 6 on which a program is recorded, an arithmetic processing unit (computer body) 7 for executing the automatic wiring processing of this example under the control of the automatic wiring program, and a working area for setting a work area of the arithmetic processing device 7 A storage device 8 having various data necessary for processing and a data area in which processing results are recorded; a display device 9 for displaying artwork data such as a detailed wiring diagram created by the arithmetic processing device 7; Input device 1 such as mouse and mouse
0. The recording medium 6 may be a magnetic disk, a semiconductor memory, an optical memory, or another recording medium.

Next, the operation of this example will be described with reference to FIGS. First, as shown in FIG. 3, in step SP1, the circuit designer prepares block graphic information and terminal graphic information such as primitive blocks such as flip-flops and macro blocks such as multipliers prepared in the library 5 in step SP1. To design a circuit by CAD. In addition, the above-mentioned block figure and terminal figure are, for example, “layer”,
It is composed of a rectangular figure or a set of rectangular figures whose size, shape and position are specified by parameters such as “lower left coordinates” and “upper right coordinates”. Next, while looking at the circuit diagram displayed on the screen of the display device 9, the circuit designer sets a net list (inter-terminal connection information, wiring width information) with the internal area set inside the semiconductor chip as a wiring target area. Then, the base information (the lattice size (interval between the wiring tracks), the number of wiring layers, etc.) and the wiring prohibition information are created (step SP2), and the created various kinds of information are stored in the storage device 8.

Next, the circuit designer causes the display device 9 to display a screen of the internal area of the semiconductor chip, and further displays the internal area of the semiconductor chip in the internal area of FIG. (The wiring tracks T, T...) Are displayed, and the macro block 12 and the primitive block are displayed with reference to the netlist and the wiring prohibition information created in step SP2 as shown in FIG. 13 in the internal area of the semiconductor chip and
(Step SP3) The power supply (Vdd) net 20, the ground net 21, and the minimum cost search of the wide wiring such as the clock net are performed, and the wiring route is stored in the storage device 8 as layout information (Step SP4).

Next, the circuit designer causes the layout information to be displayed on a screen. Power supply for all corners (Vdd)
The net 20 and the grand net 21 are stored in the storage device 8 as the layout information created above. For example, as shown in FIG.
Center line 1 of two mutually orthogonal wiring segments 1 and 2
c and 2c are defined by end points 1a and C and 2a and C, respectively, and the end point C is shared by the wiring segments 1 and 2. Further, the circuit designer displays the vicinity of the corner A in order to set the virtual wiring width of the wiring segment 1 and to set the clearance groove in the wiring segment 1 (step SP5). When the circuit designer selects the wiring segment 1, the arithmetic processing unit 7 executes the following processing according to an instruction of a program stored in the recording medium 6. Individual narrow wiring width W divided by the clearance groove in equation (1)
The values to be satisfied by C1 and the wiring segment height H from the CMP polishing step and the like are determined, and the arithmetic processing unit 7 reads them from the library 5. The arithmetic processing unit 7
Reads the parameters and design rules stored in the library 5 and calculates the allowable current density Ia of the wiring segment 1 and the maximum current value It flowing through the wiring segment 1 in equation (1). Further, the calculation of the expression (1) is performed from these values, and M1, that is, the number of narrow wirings after division is calculated (step SP6). Ia = It ÷ (WC1 × M1 × H) (1) Ia: Allowable current density of wiring segment 1 It: Maximum current value flowing through wiring segment 1 WC1: Individual narrow wiring width divided by clearance groove M1: Divided Similarly, the arithmetic processing unit 7 reads out the parameters and design rules stored in the library 5 according to the instructions of the program stored in the recording medium 6, and reads the clearance and the clearance. The groove width WS1 is calculated. The individual narrow wiring widths WC1 divided by the clearance grooves and the number of narrow wirings M1 after division have already been calculated as described above, and the arithmetic processing unit 7 executes the calculation of the equation (2) 8, the virtual wiring width W11 of the wiring segment 1 is calculated.
(Step SP6). W11 = WC1 × M1 + N1 × WS1 (2) W11: Virtual wiring width of wiring segment 1 N1: Number of clearance grooves WS1: Groove width of clearance groove Similarly, when the circuit designer selects wiring segment 2,
The arithmetic processing unit 7 sets the number N2 of the clearance grooves set in the wiring segment 2 (or the number M2 of the narrow wirings after division), and the virtual wiring width W of the wiring segment 2 shown in FIG.
12 is calculated (step SP7).

Next, the arithmetic processing unit 7 performs the following wiring design in accordance with the instructions of the program stored in the recording medium 6. The center line 1c is extended toward the point C by W12 / 2 to set a point C1. Similarly, the center line 2c is extended toward the point C by W11 / 2 to set the point C2. A center line 1a-C1, a wiring segment 1 having a virtual wiring width of W11, and a center line 1b-C2, W
Based on a wiring segment 2 having a virtual wiring width of 12,
The pattern outer shape is calculated (step SP9). Pattern 1
Then, the clearance grooves having the N1 groove widths WS1 calculated as described above are set in a range from the point 1a to C1 (step SP10). Similarly, the clearance grooves having the N2 groove widths WS2 set in the pattern 2 as described above are set in a range from the point 1b to C2 (step SP11). FIG. 2 is a diagram schematically illustrating the semiconductor device designed in the present embodiment.

When the above procedure is completed at all points where the wide wirings intersect in an L-shape with respect to the target wiring, the automatic wiring processing ends (step SP12). in this way,
According to the configuration of this example, it is possible to easily set the narrow bundles divided into bundles satisfying the desired parameters and the design rules, including the intersection area, and to reduce the number of design steps by automatic wiring design. Can be.

Second Embodiment This embodiment is different from the above-described first embodiment in that an intersection region where two mutually orthogonal wiring segments 3 and 4 intersect in a T-shape is described in the first embodiment. This is a point added to the example, and corresponds to the area of the circle B in FIG. FIG. 1 is a block diagram showing the outline of the electrical configuration of the present embodiment, as in the first embodiment. FIG. 9 is a partial wiring diagram schematically showing the characteristics of the wiring path created by the automatic wiring device. Figure,
10 and 11 are flowcharts for explaining the operation (automatic wiring processing) of the embodiment, and FIGS. 5, 6, 12 and 13 are diagrams for explaining the operation of the embodiment. 12, FIG. 13 and FIG. 13 are enlarged views of the area of the circle B in FIG. 6, and all show additional parts to the first embodiment. Next, FIG. 1, FIG. 5, FIG. 6, FIG.
With reference to FIG. 3, an additional operation of this example with respect to the first example will be described. In FIG. 10, steps SQ1 to SQ
The operation of Q4 is based on steps SP1 to S1 of the first embodiment.
The operation is exactly the same as that of P4. Next, the layout information stored in the storage device 8 is displayed. In the intersection area B of the power supply nets in FIG. 6, a center line 3c of the wiring segment 3 is defined by end points 3a and C as shown in FIG. The circuit designer displays the vicinity of the corner B in order to set the virtual wiring width of the wiring segment 3 and to set the clearance groove in the wiring segment 3 (step SQ).
5). When the circuit designer selects the wiring segment 3, the arithmetic processing unit 7 executes the following processing according to an instruction of a program stored in the recording medium 6. First, Library 5
Is read out, and the number M3 of the narrow wirings after the division of the wiring segment 3 is calculated as in the first embodiment. Similarly, the arithmetic processing unit 7
Reads the parameters and design rules stored in the library 5 in accordance with the instructions of the program stored in the recording medium 6, and reads the groove width WS3 of the clearance groove.
Is calculated. The individual narrow wiring widths WC3 divided by the clearance grooves and the number of narrow wirings M3 after the division have already been calculated as described above, and the arithmetic processing unit 7 performs the processing shown in FIG. Is calculated (step SQ6). Similarly, when the wiring segment 4 is selected, the arithmetic processing unit 7 sets the number N4 of the clearance grooves set in the wiring segment 4 as shown in FIG.
4), calculate the virtual wiring width W14 of the wiring segment 4
(Step SQ7).

Next, the arithmetic processing unit 7 performs the following wiring design according to the instructions of the program stored in the recording medium 6, as shown in FIG. The center line 3c is extended toward the point C by W14 / 2, and a point C3 is set.
(Step SQ8). The pattern outer shape is calculated based on the center line 3a-C3, the wiring segment 3 having the virtual wiring width of W13, and the wiring segment 4 having the virtual wiring width of W14 (step SQ9). The clearance grooves having the N3 groove widths WS3 calculated as described above are set in the wiring segment 3 in the range from the point 3a to the point C3 (Step S).
Q10). Similarly, a clearance groove having N4 groove widths WS4 set as described above is set in the wiring segment 4 over the entire length of the wiring segment 4 (step SQ1).
1). When the above procedure is completed at all the places where the thick wirings intersect in a T-shape with respect to the target wiring, the automatic wiring processing ends (Step SQ12). As described above, according to the configuration of this example, it is possible to easily set the divided bundled narrow wiring satisfying the desired parameters and the design rules, including the intersection area, and to reduce the number of design steps by the automatic wiring design. Reduction can be achieved.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and there are design changes and the like without departing from the gist of the present invention. Even this is included in the present invention. For example, in the above-described embodiment, two orthogonal wires are L-shaped or T-shaped.
Although they intersect in the shape of a letter, even if they intersect in the shape of a cross, automatic design can be easily performed as is clear from the above-described embodiment. In the above-described embodiment, the widths of the two intersecting wiring segments are different from each other, but may be the same.

[0024]

As described above, according to the present invention, it is possible to easily set a divided bundle of narrow wires satisfying parameters and design rules not only at a straight line portion but also at an orthogonal crossing portion. And the number of design steps can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing an electrical configuration of an automatic wiring device for a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a partial wiring diagram schematically showing characteristics of a wiring path created by the automatic wiring device.

FIG. 3 is a flowchart for explaining the operation (automatic wiring processing) of the embodiment.

FIG. 4 is a flowchart for explaining the operation (automatic wiring processing) of the embodiment.

FIG. 5 is a diagram which is used for describing the operation of the embodiment and is a diagram showing an arrangement state of wiring tracks and grids.

FIG. 6 is a diagram used for describing the operation of the embodiment, and is a diagram illustrating an arrangement state of macro blocks, primitive blocks, power supply nets, and ground nets.

FIG. 7 is an enlarged view showing a region of a circle A in FIG. 6;
It is a figure showing the center line of a wiring segment.

FIG. 8 is a diagram provided for describing the operation of the embodiment, and is a diagram illustrating a method of setting a virtual wiring width and a narrow wiring.

FIG. 9 is a partial wiring diagram schematically showing characteristics of a wiring path created by an automatic wiring method for a semiconductor device according to a second embodiment of the present invention.

FIG. 10 is a flowchart for explaining the operation (automatic wiring processing) of the embodiment.

FIG. 11 is a flowchart for explaining the operation (automatic wiring processing) of the embodiment.

FIG. 12 is an enlarged view of a region of a circle B in FIG. 6, showing a center line of a wiring segment;

FIG. 13 is a diagram which is used for describing the operation of the embodiment and is a diagram illustrating a method of setting a virtual wiring width and a narrow wiring.

FIG. 14 is a diagram showing a cross-sectional shape of a semiconductor designed by a processing procedure of a conventional wiring design method.

FIG. 15 is a diagram showing a wiring route calculated by a processing procedure of a conventional wiring design method.

[Explanation of symbols]

1, 2, 3, 4 Wiring segment 5 Library 6 Recording medium 7 Arithmetic processing unit 8 Storage device 9 Display device 10 Input device 11 Automatic wiring device 12 Macro block 13 Primitive block 14, 15, 16, 17 Clearance groove in case of failure 20 Power net 21 Ground net G Grid T Wiring track

Claims (8)

[Claims] 1. An automatic wiring method for a semiconductor device in which a wide wiring is divided and bundled into a plurality of narrow wirings to perform a wiring process, wherein the wide wirings intersect in an L-shape. A process of extending the wiring length of the wiring reaching the intersection of the intersection area by 幅 of the other virtual wiring width is performed on both wirings, or in a T-shaped intersection area,
Make the wiring length of the dimension stop side wiring 1/1 of the other virtual wiring width.
Performing a process of extending by two widths or performing at least one of the processes; and dividing the wide wiring into narrow wirings and providing a clearance bundle between the narrow wirings. An automatic wiring method for a semiconductor device. 2. The dividing and bundling step includes performing a dividing and bundling calculation such that a total value of each width of the narrow wiring satisfies a design value of a current density set in advance for the wide wiring before the division. 2. The automatic wiring method for a semiconductor device according to claim 1, wherein: 3. A semiconductor automatic wiring method for performing wiring processing by dividing and bundling a wide wiring into a plurality of narrow wirings, wherein a wiring width allowable value defining an upper limit value of a wiring width and a spacing rule violation are defined. From the viewpoint of avoidance, a clearance allowable lower limit value that defines the lower limit value of the clearance between adjacent narrow wirings is set, and based on the set wiring width allowable value, the wide wiring is extracted, and then each extracted wiring is extracted. For the thick wiring, based on the set allowable upper limit value of the wiring width and the allowable lower limit value of the clearance, the number and the line width of the narrow wiring, the number and the width of the clearance groove between the adjacent narrow wiring. From the calculation result, a virtual wiring width is obtained. In an intersection area where the thick wirings intersect in an L-shape, the wiring length of each wiring reaching the intersection of the intersection area is determined by the other 1 of the virtual wiring width of A process of extending by two widths is performed on both wirings, and based on the number and width of the narrow wirings, and the number and width of the clearance grooves between adjacent narrow wirings, a plurality of the wide wirings are formed. An automatic wiring method for a semiconductor device, comprising a process of dividing and bundling into narrow wires. 4. The automatic wiring method for a semiconductor device according to claim 3, wherein the wide wirings have different line widths in an intersection region where the wide wirings intersect in an L-shape. 5. When the wide wires have an intersecting region that intersects in a T-shape, of the wires reaching the intersection of the intersecting region, the wire length of the non-stop side wire is set to the other virtual length. A process of extending by a half width of the wiring width is performed, and based on the number of the narrow wirings and the line width thereof, and the number and width of the clearance grooves between adjacent narrow wirings, a plurality of the wide wirings are formed. 4. The automatic wiring method for a semiconductor device according to claim 3, further comprising a process of dividing and bundling into narrow wires. 6. The automatic wiring method for a semiconductor device according to claim 5, wherein the wide wirings have different line widths in an intersection region where the wide wirings cross each other in a T-shape. 7. A computer-readable recording medium on which a semiconductor automatic wiring program for dividing and bundling a wide wiring into a plurality of narrow wirings and performing wiring processing is provided. From the viewpoint of avoiding the specified wiring width allowable value and spacing rule violation, a clearance allowable lower limit value defining the lower limit value of the clearance between adjacent narrow wirings is set, and based on the set wiring width allowable value, After extracting the wide wiring, for each extracted wide wiring, based on the set upper limit of the wiring width and the allowable lower limit of the clearance, the number of the narrow wiring and its line width, The number of clearance grooves between adjacent narrow wirings and the width thereof are calculated, a virtual wiring width is obtained from the calculation result, and an intersection area where the wide wirings intersect in an L-shape. Then, a process of extending the wiring length of the wiring reaching the intersection of the intersection area by 幅 of the other virtual wiring width is performed on both wirings. In the intersecting region intersecting in the shape of a letter, of the wires reaching the intersection of the intersecting region, a process of extending the wiring length of the non-stop side wiring by half of the other virtual wiring width is performed. A program for dividing and bundling the wide wiring into a plurality of narrow wirings based on the number and width of the narrow wirings and the number and width of clearance grooves between adjacent narrow wirings. A computer-readable recording medium in which an automatic wiring program for a semiconductor device is recorded. 8. A semiconductor device in which a wide wiring is divided and bundled into a plurality of narrow wirings and wired, wherein the narrow wirings intersect each other in an L-shape, a T-shape or a cross shape. A semiconductor device comprising a grid-shaped wiring portion and a plurality of rectangular non-wiring recesses, wherein the narrow wiring is bundled in the intersection region.